allwinner-a10.c 4.7 KB

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  1. /*
  2. * Allwinner A10 SoC emulation
  3. *
  4. * Copyright (C) 2013 Li Guang
  5. * Written by Li Guang <lig.fnst@cn.fujitsu.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15. * for more details.
  16. */
  17. #include "qemu/osdep.h"
  18. #include "exec/address-spaces.h"
  19. #include "qapi/error.h"
  20. #include "qemu/module.h"
  21. #include "cpu.h"
  22. #include "hw/sysbus.h"
  23. #include "hw/arm/allwinner-a10.h"
  24. #include "hw/misc/unimp.h"
  25. #include "sysemu/sysemu.h"
  26. static void aw_a10_init(Object *obj)
  27. {
  28. AwA10State *s = AW_A10(obj);
  29. object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
  30. ARM_CPU_TYPE_NAME("cortex-a8"),
  31. &error_abort, NULL);
  32. sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
  33. TYPE_AW_A10_PIC);
  34. sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
  35. TYPE_AW_A10_PIT);
  36. sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC);
  37. sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
  38. TYPE_ALLWINNER_AHCI);
  39. }
  40. static void aw_a10_realize(DeviceState *dev, Error **errp)
  41. {
  42. AwA10State *s = AW_A10(dev);
  43. SysBusDevice *sysbusdev;
  44. uint8_t i;
  45. qemu_irq fiq, irq;
  46. Error *err = NULL;
  47. object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  48. if (err != NULL) {
  49. error_propagate(errp, err);
  50. return;
  51. }
  52. irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
  53. fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
  54. object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
  55. if (err != NULL) {
  56. error_propagate(errp, err);
  57. return;
  58. }
  59. sysbusdev = SYS_BUS_DEVICE(&s->intc);
  60. sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
  61. sysbus_connect_irq(sysbusdev, 0, irq);
  62. sysbus_connect_irq(sysbusdev, 1, fiq);
  63. for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
  64. s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
  65. }
  66. object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
  67. if (err != NULL) {
  68. error_propagate(errp, err);
  69. return;
  70. }
  71. sysbusdev = SYS_BUS_DEVICE(&s->timer);
  72. sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
  73. sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
  74. sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
  75. sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
  76. sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
  77. sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
  78. sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
  79. memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
  80. &error_fatal);
  81. memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
  82. create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
  83. /* FIXME use qdev NIC properties instead of nd_table[] */
  84. if (nd_table[0].used) {
  85. qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
  86. qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
  87. }
  88. object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
  89. if (err != NULL) {
  90. error_propagate(errp, err);
  91. return;
  92. }
  93. sysbusdev = SYS_BUS_DEVICE(&s->emac);
  94. sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
  95. sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
  96. object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
  97. if (err) {
  98. error_propagate(errp, err);
  99. return;
  100. }
  101. sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
  102. sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
  103. /* FIXME use a qdev chardev prop instead of serial_hd() */
  104. serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
  105. 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
  106. }
  107. static void aw_a10_class_init(ObjectClass *oc, void *data)
  108. {
  109. DeviceClass *dc = DEVICE_CLASS(oc);
  110. dc->realize = aw_a10_realize;
  111. /* Reason: Uses serial_hds and nd_table in realize function */
  112. dc->user_creatable = false;
  113. }
  114. static const TypeInfo aw_a10_type_info = {
  115. .name = TYPE_AW_A10,
  116. .parent = TYPE_DEVICE,
  117. .instance_size = sizeof(AwA10State),
  118. .instance_init = aw_a10_init,
  119. .class_init = aw_a10_class_init,
  120. };
  121. static void aw_a10_register_types(void)
  122. {
  123. type_register_static(&aw_a10_type_info);
  124. }
  125. type_init(aw_a10_register_types)