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qemu-cpu-models.texi 16 KB

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  1. @c man begin SYNOPSIS
  2. QEMU / KVM CPU model configuration
  3. @c man end
  4. @set qemu_system_x86 qemu-system-x86_64
  5. @c man begin DESCRIPTION
  6. @menu
  7. * recommendations_cpu_models_x86:: Recommendations for KVM CPU model configuration on x86 hosts
  8. * recommendations_cpu_models_MIPS:: Supported CPU model configurations on MIPS hosts
  9. * cpu_model_syntax_apps:: Syntax for configuring CPU models
  10. @end menu
  11. QEMU / KVM virtualization supports two ways to configure CPU models
  12. @table @option
  13. @item Host passthrough
  14. This passes the host CPU model features, model, stepping, exactly to the
  15. guest. Note that KVM may filter out some host CPU model features if they
  16. cannot be supported with virtualization. Live migration is unsafe when
  17. this mode is used as libvirt / QEMU cannot guarantee a stable CPU is
  18. exposed to the guest across hosts. This is the recommended CPU to use,
  19. provided live migration is not required.
  20. @item Named model
  21. QEMU comes with a number of predefined named CPU models, that typically
  22. refer to specific generations of hardware released by Intel and AMD.
  23. These allow the guest VMs to have a degree of isolation from the host CPU,
  24. allowing greater flexibility in live migrating between hosts with differing
  25. hardware.
  26. @end table
  27. In both cases, it is possible to optionally add or remove individual CPU
  28. features, to alter what is presented to the guest by default.
  29. Libvirt supports a third way to configure CPU models known as "Host model".
  30. This uses the QEMU "Named model" feature, automatically picking a CPU model
  31. that is similar the host CPU, and then adding extra features to approximate
  32. the host model as closely as possible. This does not guarantee the CPU family,
  33. stepping, etc will precisely match the host CPU, as they would with "Host
  34. passthrough", but gives much of the benefit of passthrough, while making
  35. live migration safe.
  36. @node recommendations_cpu_models_x86
  37. @subsection Recommendations for KVM CPU model configuration on x86 hosts
  38. The information that follows provides recommendations for configuring
  39. CPU models on x86 hosts. The goals are to maximise performance, while
  40. protecting guest OS against various CPU hardware flaws, and optionally
  41. enabling live migration between hosts with heterogeneous CPU models.
  42. @menu
  43. * preferred_cpu_models_intel_x86:: Preferred CPU models for Intel x86 hosts
  44. * important_cpu_features_intel_x86:: Important CPU features for Intel x86 hosts
  45. * preferred_cpu_models_amd_x86:: Preferred CPU models for AMD x86 hosts
  46. * important_cpu_features_amd_x86:: Important CPU features for AMD x86 hosts
  47. * default_cpu_models_x86:: Default x86 CPU models
  48. * other_non_recommended_cpu_models_x86:: Other non-recommended x86 CPUs
  49. @end menu
  50. @node preferred_cpu_models_intel_x86
  51. @subsubsection Preferred CPU models for Intel x86 hosts
  52. The following CPU models are preferred for use on Intel hosts. Administrators /
  53. applications are recommended to use the CPU model that matches the generation
  54. of the host CPUs in use. In a deployment with a mixture of host CPU models
  55. between machines, if live migration compatibility is required, use the newest
  56. CPU model that is compatible across all desired hosts.
  57. @table @option
  58. @item @code{Skylake-Server}
  59. @item @code{Skylake-Server-IBRS}
  60. Intel Xeon Processor (Skylake, 2016)
  61. @item @code{Skylake-Client}
  62. @item @code{Skylake-Client-IBRS}
  63. Intel Core Processor (Skylake, 2015)
  64. @item @code{Broadwell}
  65. @item @code{Broadwell-IBRS}
  66. @item @code{Broadwell-noTSX}
  67. @item @code{Broadwell-noTSX-IBRS}
  68. Intel Core Processor (Broadwell, 2014)
  69. @item @code{Haswell}
  70. @item @code{Haswell-IBRS}
  71. @item @code{Haswell-noTSX}
  72. @item @code{Haswell-noTSX-IBRS}
  73. Intel Core Processor (Haswell, 2013)
  74. @item @code{IvyBridge}
  75. @item @code{IvyBridge-IBRS}
  76. Intel Xeon E3-12xx v2 (Ivy Bridge, 2012)
  77. @item @code{SandyBridge}
  78. @item @code{SandyBridge-IBRS}
  79. Intel Xeon E312xx (Sandy Bridge, 2011)
  80. @item @code{Westmere}
  81. @item @code{Westmere-IBRS}
  82. Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010)
  83. @item @code{Nehalem}
  84. @item @code{Nehalem-IBRS}
  85. Intel Core i7 9xx (Nehalem Class Core i7, 2008)
  86. @item @code{Penryn}
  87. Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007)
  88. @item @code{Conroe}
  89. Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006)
  90. @end table
  91. @node important_cpu_features_intel_x86
  92. @subsubsection Important CPU features for Intel x86 hosts
  93. The following are important CPU features that should be used on Intel x86
  94. hosts, when available in the host CPU. Some of them require explicit
  95. configuration to enable, as they are not included by default in some, or all,
  96. of the named CPU models listed above. In general all of these features are
  97. included if using "Host passthrough" or "Host model".
  98. @table @option
  99. @item @code{pcid}
  100. Recommended to mitigate the cost of the Meltdown (CVE-2017-5754) fix
  101. Included by default in Haswell, Broadwell & Skylake Intel CPU models.
  102. Should be explicitly turned on for Westmere, SandyBridge, and IvyBridge
  103. Intel CPU models. Note that some desktop/mobile Westmere CPUs cannot
  104. support this feature.
  105. @item @code{spec-ctrl}
  106. Required to enable the Spectre v2 (CVE-2017-5715) fix.
  107. Included by default in Intel CPU models with -IBRS suffix.
  108. Must be explicitly turned on for Intel CPU models without -IBRS suffix.
  109. Requires the host CPU microcode to support this feature before it
  110. can be used for guest CPUs.
  111. @item @code{stibp}
  112. Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some
  113. operating systems.
  114. Must be explicitly turned on for all Intel CPU models.
  115. Requires the host CPU microcode to support this feature before it
  116. can be used for guest CPUs.
  117. @item @code{ssbd}
  118. Required to enable the CVE-2018-3639 fix
  119. Not included by default in any Intel CPU model.
  120. Must be explicitly turned on for all Intel CPU models.
  121. Requires the host CPU microcode to support this feature before it
  122. can be used for guest CPUs.
  123. @item @code{pdpe1gb}
  124. Recommended to allow guest OS to use 1GB size pages
  125. Not included by default in any Intel CPU model.
  126. Should be explicitly turned on for all Intel CPU models.
  127. Note that not all CPU hardware will support this feature.
  128. @item @code{md-clear}
  129. Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130,
  130. CVE-2019-11091) fixes.
  131. Not included by default in any Intel CPU model.
  132. Must be explicitly turned on for all Intel CPU models.
  133. Requires the host CPU microcode to support this feature before it
  134. can be used for guest CPUs.
  135. @end table
  136. @node preferred_cpu_models_amd_x86
  137. @subsubsection Preferred CPU models for AMD x86 hosts
  138. The following CPU models are preferred for use on Intel hosts. Administrators /
  139. applications are recommended to use the CPU model that matches the generation
  140. of the host CPUs in use. In a deployment with a mixture of host CPU models
  141. between machines, if live migration compatibility is required, use the newest
  142. CPU model that is compatible across all desired hosts.
  143. @table @option
  144. @item @code{EPYC}
  145. @item @code{EPYC-IBPB}
  146. AMD EPYC Processor (2017)
  147. @item @code{Opteron_G5}
  148. AMD Opteron 63xx class CPU (2012)
  149. @item @code{Opteron_G4}
  150. AMD Opteron 62xx class CPU (2011)
  151. @item @code{Opteron_G3}
  152. AMD Opteron 23xx (Gen 3 Class Opteron, 2009)
  153. @item @code{Opteron_G2}
  154. AMD Opteron 22xx (Gen 2 Class Opteron, 2006)
  155. @item @code{Opteron_G1}
  156. AMD Opteron 240 (Gen 1 Class Opteron, 2004)
  157. @end table
  158. @node important_cpu_features_amd_x86
  159. @subsubsection Important CPU features for AMD x86 hosts
  160. The following are important CPU features that should be used on AMD x86
  161. hosts, when available in the host CPU. Some of them require explicit
  162. configuration to enable, as they are not included by default in some, or all,
  163. of the named CPU models listed above. In general all of these features are
  164. included if using "Host passthrough" or "Host model".
  165. @table @option
  166. @item @code{ibpb}
  167. Required to enable the Spectre v2 (CVE-2017-5715) fix.
  168. Included by default in AMD CPU models with -IBPB suffix.
  169. Must be explicitly turned on for AMD CPU models without -IBPB suffix.
  170. Requires the host CPU microcode to support this feature before it
  171. can be used for guest CPUs.
  172. @item @code{stibp}
  173. Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some
  174. operating systems.
  175. Must be explicitly turned on for all AMD CPU models.
  176. Requires the host CPU microcode to support this feature before it
  177. can be used for guest CPUs.
  178. @item @code{virt-ssbd}
  179. Required to enable the CVE-2018-3639 fix
  180. Not included by default in any AMD CPU model.
  181. Must be explicitly turned on for all AMD CPU models.
  182. This should be provided to guests, even if amd-ssbd is also
  183. provided, for maximum guest compatibility.
  184. Note for some QEMU / libvirt versions, this must be force enabled
  185. when when using "Host model", because this is a virtual feature
  186. that doesn't exist in the physical host CPUs.
  187. @item @code{amd-ssbd}
  188. Required to enable the CVE-2018-3639 fix
  189. Not included by default in any AMD CPU model.
  190. Must be explicitly turned on for all AMD CPU models.
  191. This provides higher performance than virt-ssbd so should be
  192. exposed to guests whenever available in the host. virt-ssbd
  193. should none the less also be exposed for maximum guest
  194. compatibility as some kernels only know about virt-ssbd.
  195. @item @code{amd-no-ssb}
  196. Recommended to indicate the host is not vulnerable CVE-2018-3639
  197. Not included by default in any AMD CPU model.
  198. Future hardware generations of CPU will not be vulnerable to
  199. CVE-2018-3639, and thus the guest should be told not to enable
  200. its mitigations, by exposing amd-no-ssb. This is mutually
  201. exclusive with virt-ssbd and amd-ssbd.
  202. @item @code{pdpe1gb}
  203. Recommended to allow guest OS to use 1GB size pages
  204. Not included by default in any AMD CPU model.
  205. Should be explicitly turned on for all AMD CPU models.
  206. Note that not all CPU hardware will support this feature.
  207. @end table
  208. @node default_cpu_models_x86
  209. @subsubsection Default x86 CPU models
  210. The default QEMU CPU models are designed such that they can run on all hosts.
  211. If an application does not wish to do perform any host compatibility checks
  212. before launching guests, the default is guaranteed to work.
  213. The default CPU models will, however, leave the guest OS vulnerable to various
  214. CPU hardware flaws, so their use is strongly discouraged. Applications should
  215. follow the earlier guidance to setup a better CPU configuration, with host
  216. passthrough recommended if live migration is not needed.
  217. @table @option
  218. @item @code{qemu32}
  219. @item @code{qemu64}
  220. QEMU Virtual CPU version 2.5+ (32 & 64 bit variants)
  221. qemu64 is used for x86_64 guests and qemu32 is used for i686 guests, when no
  222. -cpu argument is given to QEMU, or no <cpu> is provided in libvirt XML.
  223. @end table
  224. @node other_non_recommended_cpu_models_x86
  225. @subsubsection Other non-recommended x86 CPUs
  226. The following CPUs models are compatible with most AMD and Intel x86 hosts, but
  227. their usage is discouraged, as they expose a very limited featureset, which
  228. prevents guests having optimal performance.
  229. @table @option
  230. @item @code{kvm32}
  231. @item @code{kvm64}
  232. Common KVM processor (32 & 64 bit variants)
  233. Legacy models just for historical compatibility with ancient QEMU versions.
  234. @item @code{486}
  235. @item @code{athlon}
  236. @item @code{phenom}
  237. @item @code{coreduo}
  238. @item @code{core2duo}
  239. @item @code{n270}
  240. @item @code{pentium}
  241. @item @code{pentium2}
  242. @item @code{pentium3}
  243. Various very old x86 CPU models, mostly predating the introduction of
  244. hardware assisted virtualization, that should thus not be required for
  245. running virtual machines.
  246. @end table
  247. @node recommendations_cpu_models_MIPS
  248. @subsection Supported CPU model configurations on MIPS hosts
  249. QEMU supports variety of MIPS CPU models:
  250. @menu
  251. * cpu_models_MIPS32:: Supported CPU models for MIPS32 hosts
  252. * cpu_models_MIPS64:: Supported CPU models for MIPS64 hosts
  253. * cpu_models_nanoMIPS:: Supported CPU models for nanoMIPS hosts
  254. * preferred_cpu_models_MIPS:: Preferred CPU models for MIPS hosts
  255. @end menu
  256. @node cpu_models_MIPS32
  257. @subsubsection Supported CPU models for MIPS32 hosts
  258. The following CPU models are supported for use on MIPS32 hosts. Administrators /
  259. applications are recommended to use the CPU model that matches the generation
  260. of the host CPUs in use. In a deployment with a mixture of host CPU models
  261. between machines, if live migration compatibility is required, use the newest
  262. CPU model that is compatible across all desired hosts.
  263. @table @option
  264. @item @code{mips32r6-generic}
  265. MIPS32 Processor (Release 6, 2015)
  266. @item @code{P5600}
  267. MIPS32 Processor (P5600, 2014)
  268. @item @code{M14K}
  269. @item @code{M14Kc}
  270. MIPS32 Processor (M14K, 2009)
  271. @item @code{74Kf}
  272. MIPS32 Processor (74K, 2007)
  273. @item @code{34Kf}
  274. MIPS32 Processor (34K, 2006)
  275. @item @code{24Kc}
  276. @item @code{24KEc}
  277. @item @code{24Kf}
  278. MIPS32 Processor (24K, 2003)
  279. @item @code{4Kc}
  280. @item @code{4Km}
  281. @item @code{4KEcR1}
  282. @item @code{4KEmR1}
  283. @item @code{4KEc}
  284. @item @code{4KEm}
  285. MIPS32 Processor (4K, 1999)
  286. @end table
  287. @node cpu_models_MIPS64
  288. @subsubsection Supported CPU models for MIPS64 hosts
  289. The following CPU models are supported for use on MIPS64 hosts. Administrators /
  290. applications are recommended to use the CPU model that matches the generation
  291. of the host CPUs in use. In a deployment with a mixture of host CPU models
  292. between machines, if live migration compatibility is required, use the newest
  293. CPU model that is compatible across all desired hosts.
  294. @table @option
  295. @item @code{I6400}
  296. MIPS64 Processor (Release 6, 2014)
  297. @item @code{Loongson-2F}
  298. MIPS64 Processor (Loongson 2, 2008)
  299. @item @code{Loongson-2E}
  300. MIPS64 Processor (Loongson 2, 2006)
  301. @item @code{mips64dspr2}
  302. MIPS64 Processor (Release 2, 2006)
  303. @item @code{MIPS64R2-generic}
  304. @item @code{5KEc}
  305. @item @code{5KEf}
  306. MIPS64 Processor (Release 2, 2002)
  307. @item @code{20Kc}
  308. MIPS64 Processor (20K, 2000)
  309. @item @code{5Kc}
  310. @item @code{5Kf}
  311. MIPS64 Processor (5K, 1999)
  312. @item @code{VR5432}
  313. MIPS64 Processor (VR, 1998)
  314. @item @code{R4000}
  315. MIPS64 Processor (MIPS III, 1991)
  316. @end table
  317. @node cpu_models_nanoMIPS
  318. @subsubsection Supported CPU models for nanoMIPS hosts
  319. The following CPU models are supported for use on nanoMIPS hosts. Administrators /
  320. applications are recommended to use the CPU model that matches the generation
  321. of the host CPUs in use. In a deployment with a mixture of host CPU models
  322. between machines, if live migration compatibility is required, use the newest
  323. CPU model that is compatible across all desired hosts.
  324. @table @option
  325. @item @code{I7200}
  326. MIPS I7200 (nanoMIPS, 2018)
  327. @end table
  328. @node preferred_cpu_models_MIPS
  329. @subsubsection Preferred CPU models for MIPS hosts
  330. The following CPU models are preferred for use on different MIPS hosts:
  331. @table @option
  332. @item @code{MIPS III}
  333. R4000
  334. @item @code{MIPS32R2}
  335. 34Kf
  336. @item @code{MIPS64R6}
  337. I6400
  338. @item @code{nanoMIPS}
  339. I7200
  340. @end table
  341. @node cpu_model_syntax_apps
  342. @subsection Syntax for configuring CPU models
  343. The example below illustrate the approach to configuring the various
  344. CPU models / features in QEMU and libvirt
  345. @menu
  346. * cpu_model_syntax_qemu:: QEMU command line
  347. * cpu_model_syntax_libvirt:: Libvirt guest XML
  348. @end menu
  349. @node cpu_model_syntax_qemu
  350. @subsubsection QEMU command line
  351. @table @option
  352. @item Host passthrough
  353. @example
  354. $ @value{qemu_system_x86} -cpu host
  355. @end example
  356. With feature customization:
  357. @example
  358. $ @value{qemu_system_x86} -cpu host,-vmx,...
  359. @end example
  360. @item Named CPU models
  361. @example
  362. $ @value{qemu_system_x86} -cpu Westmere
  363. @end example
  364. With feature customization:
  365. @example
  366. $ @value{qemu_system_x86} -cpu Westmere,+pcid,...
  367. @end example
  368. @end table
  369. @node cpu_model_syntax_libvirt
  370. @subsubsection Libvirt guest XML
  371. @table @option
  372. @item Host passthrough
  373. @example
  374. <cpu mode='host-passthrough'/>
  375. @end example
  376. With feature customization:
  377. @example
  378. <cpu mode='host-passthrough'>
  379. <feature name="vmx" policy="disable"/>
  380. ...
  381. </cpu>
  382. @end example
  383. @item Host model
  384. @example
  385. <cpu mode='host-model'/>
  386. @end example
  387. With feature customization:
  388. @example
  389. <cpu mode='host-model'>
  390. <feature name="vmx" policy="disable"/>
  391. ...
  392. </cpu>
  393. @end example
  394. @item Named model
  395. @example
  396. <cpu mode='custom'>
  397. <model name="Westmere"/>
  398. </cpu>
  399. @end example
  400. With feature customization:
  401. @example
  402. <cpu mode='custom'>
  403. <model name="Westmere"/>
  404. <feature name="pcid" policy="require"/>
  405. ...
  406. </cpu>
  407. @end example
  408. @end table
  409. @c man end
  410. @ignore
  411. @setfilename qemu-cpu-models
  412. @settitle QEMU / KVM CPU model configuration
  413. @c man begin SEEALSO
  414. The HTML documentation of QEMU for more precise information and Linux
  415. user mode emulator invocation.
  416. @c man end
  417. @c man begin AUTHOR
  418. Daniel P. Berrange
  419. @c man end
  420. @end ignore