cpu_loop.c 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133
  1. /*
  2. * qemu user cpu loop
  3. *
  4. * Copyright (c) 2003-2008 Fabrice Bellard
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "qemu/osdep.h"
  20. #include "qemu-common.h"
  21. #include "qemu/error-report.h"
  22. #include "qemu.h"
  23. #include "cpu_loop-common.h"
  24. #include "elf.h"
  25. void cpu_loop(CPURISCVState *env)
  26. {
  27. CPUState *cs = env_cpu(env);
  28. int trapnr, signum, sigcode;
  29. target_ulong sigaddr;
  30. target_ulong ret;
  31. for (;;) {
  32. cpu_exec_start(cs);
  33. trapnr = cpu_exec(cs);
  34. cpu_exec_end(cs);
  35. process_queued_cpu_work(cs);
  36. signum = 0;
  37. sigcode = 0;
  38. sigaddr = 0;
  39. switch (trapnr) {
  40. case EXCP_INTERRUPT:
  41. /* just indicate that signals should be handled asap */
  42. break;
  43. case EXCP_ATOMIC:
  44. cpu_exec_step_atomic(cs);
  45. break;
  46. case RISCV_EXCP_U_ECALL:
  47. env->pc += 4;
  48. if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) {
  49. /* riscv_flush_icache_syscall is a no-op in QEMU as
  50. self-modifying code is automatically detected */
  51. ret = 0;
  52. } else {
  53. ret = do_syscall(env,
  54. env->gpr[(env->elf_flags & EF_RISCV_RVE)
  55. ? xT0 : xA7],
  56. env->gpr[xA0],
  57. env->gpr[xA1],
  58. env->gpr[xA2],
  59. env->gpr[xA3],
  60. env->gpr[xA4],
  61. env->gpr[xA5],
  62. 0, 0);
  63. }
  64. if (ret == -TARGET_ERESTARTSYS) {
  65. env->pc -= 4;
  66. } else if (ret != -TARGET_QEMU_ESIGRETURN) {
  67. env->gpr[xA0] = ret;
  68. }
  69. if (cs->singlestep_enabled) {
  70. goto gdbstep;
  71. }
  72. break;
  73. case RISCV_EXCP_ILLEGAL_INST:
  74. signum = TARGET_SIGILL;
  75. sigcode = TARGET_ILL_ILLOPC;
  76. break;
  77. case RISCV_EXCP_BREAKPOINT:
  78. signum = TARGET_SIGTRAP;
  79. sigcode = TARGET_TRAP_BRKPT;
  80. sigaddr = env->pc;
  81. break;
  82. case RISCV_EXCP_INST_PAGE_FAULT:
  83. case RISCV_EXCP_LOAD_PAGE_FAULT:
  84. case RISCV_EXCP_STORE_PAGE_FAULT:
  85. signum = TARGET_SIGSEGV;
  86. sigcode = TARGET_SEGV_MAPERR;
  87. sigaddr = env->badaddr;
  88. break;
  89. case EXCP_DEBUG:
  90. gdbstep:
  91. signum = TARGET_SIGTRAP;
  92. sigcode = TARGET_TRAP_BRKPT;
  93. break;
  94. default:
  95. EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
  96. trapnr);
  97. exit(EXIT_FAILURE);
  98. }
  99. if (signum) {
  100. target_siginfo_t info = {
  101. .si_signo = signum,
  102. .si_errno = 0,
  103. .si_code = sigcode,
  104. ._sifields._sigfault._addr = sigaddr
  105. };
  106. queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
  107. }
  108. process_pending_signals(env);
  109. }
  110. }
  111. void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
  112. {
  113. CPUState *cpu = env_cpu(env);
  114. TaskState *ts = cpu->opaque;
  115. struct image_info *info = ts->info;
  116. env->pc = regs->sepc;
  117. env->gpr[xSP] = regs->sp;
  118. env->elf_flags = info->elf_flags;
  119. if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
  120. error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
  121. exit(EXIT_FAILURE);
  122. }
  123. }