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hcd-uhci.c 39 KB

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  1. /*
  2. * USB UHCI controller emulation
  3. *
  4. * Copyright (c) 2005 Fabrice Bellard
  5. *
  6. * Copyright (c) 2008 Max Krasnyansky
  7. * Magor rewrite of the UHCI data structures parser and frame processor
  8. * Support for fully async operation and multiple outstanding transactions
  9. *
  10. * Permission is hereby granted, free of charge, to any person obtaining a copy
  11. * of this software and associated documentation files (the "Software"), to deal
  12. * in the Software without restriction, including without limitation the rights
  13. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14. * copies of the Software, and to permit persons to whom the Software is
  15. * furnished to do so, subject to the following conditions:
  16. *
  17. * The above copyright notice and this permission notice shall be included in
  18. * all copies or substantial portions of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26. * THE SOFTWARE.
  27. */
  28. #include "qemu/osdep.h"
  29. #include "hw/usb.h"
  30. #include "hw/usb/uhci-regs.h"
  31. #include "migration/vmstate.h"
  32. #include "hw/pci/pci.h"
  33. #include "hw/qdev-properties.h"
  34. #include "qapi/error.h"
  35. #include "qemu/timer.h"
  36. #include "qemu/iov.h"
  37. #include "sysemu/dma.h"
  38. #include "trace.h"
  39. #include "qemu/main-loop.h"
  40. #include "qemu/module.h"
  41. #include "qom/object.h"
  42. #define FRAME_TIMER_FREQ 1000
  43. #define FRAME_MAX_LOOPS 256
  44. /* Must be large enough to handle 10 frame delay for initial isoc requests */
  45. #define QH_VALID 32
  46. #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
  47. #define NB_PORTS 2
  48. enum {
  49. TD_RESULT_STOP_FRAME = 10,
  50. TD_RESULT_COMPLETE,
  51. TD_RESULT_NEXT_QH,
  52. TD_RESULT_ASYNC_START,
  53. TD_RESULT_ASYNC_CONT,
  54. };
  55. typedef struct UHCIState UHCIState;
  56. typedef struct UHCIAsync UHCIAsync;
  57. typedef struct UHCIQueue UHCIQueue;
  58. typedef struct UHCIInfo UHCIInfo;
  59. typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass;
  60. struct UHCIInfo {
  61. const char *name;
  62. uint16_t vendor_id;
  63. uint16_t device_id;
  64. uint8_t revision;
  65. uint8_t irq_pin;
  66. void (*realize)(PCIDevice *dev, Error **errp);
  67. bool unplug;
  68. };
  69. struct UHCIPCIDeviceClass {
  70. PCIDeviceClass parent_class;
  71. UHCIInfo info;
  72. };
  73. /*
  74. * Pending async transaction.
  75. * 'packet' must be the first field because completion
  76. * handler does "(UHCIAsync *) pkt" cast.
  77. */
  78. struct UHCIAsync {
  79. USBPacket packet;
  80. uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */
  81. uint8_t *buf;
  82. UHCIQueue *queue;
  83. QTAILQ_ENTRY(UHCIAsync) next;
  84. uint32_t td_addr;
  85. uint8_t done;
  86. };
  87. struct UHCIQueue {
  88. uint32_t qh_addr;
  89. uint32_t token;
  90. UHCIState *uhci;
  91. USBEndpoint *ep;
  92. QTAILQ_ENTRY(UHCIQueue) next;
  93. QTAILQ_HEAD(, UHCIAsync) asyncs;
  94. int8_t valid;
  95. };
  96. typedef struct UHCIPort {
  97. USBPort port;
  98. uint16_t ctrl;
  99. } UHCIPort;
  100. struct UHCIState {
  101. PCIDevice dev;
  102. MemoryRegion io_bar;
  103. USBBus bus; /* Note unused when we're a companion controller */
  104. uint16_t cmd; /* cmd register */
  105. uint16_t status;
  106. uint16_t intr; /* interrupt enable register */
  107. uint16_t frnum; /* frame number */
  108. uint32_t fl_base_addr; /* frame list base address */
  109. uint8_t sof_timing;
  110. uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
  111. int64_t expire_time;
  112. QEMUTimer *frame_timer;
  113. QEMUBH *bh;
  114. uint32_t frame_bytes;
  115. uint32_t frame_bandwidth;
  116. bool completions_only;
  117. UHCIPort ports[NB_PORTS];
  118. /* Interrupts that should be raised at the end of the current frame. */
  119. uint32_t pending_int_mask;
  120. /* Active packets */
  121. QTAILQ_HEAD(, UHCIQueue) queues;
  122. uint8_t num_ports_vmstate;
  123. /* Properties */
  124. char *masterbus;
  125. uint32_t firstport;
  126. uint32_t maxframes;
  127. };
  128. typedef struct UHCI_TD {
  129. uint32_t link;
  130. uint32_t ctrl; /* see TD_CTRL_xxx */
  131. uint32_t token;
  132. uint32_t buffer;
  133. } UHCI_TD;
  134. typedef struct UHCI_QH {
  135. uint32_t link;
  136. uint32_t el_link;
  137. } UHCI_QH;
  138. static void uhci_async_cancel(UHCIAsync *async);
  139. static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td);
  140. static void uhci_resume(void *opaque);
  141. #define TYPE_UHCI "pci-uhci-usb"
  142. DECLARE_INSTANCE_CHECKER(UHCIState, UHCI,
  143. TYPE_UHCI)
  144. static inline int32_t uhci_queue_token(UHCI_TD *td)
  145. {
  146. if ((td->token & (0xf << 15)) == 0) {
  147. /* ctrl ep, cover ep and dev, not pid! */
  148. return td->token & 0x7ff00;
  149. } else {
  150. /* covers ep, dev, pid -> identifies the endpoint */
  151. return td->token & 0x7ffff;
  152. }
  153. }
  154. static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td,
  155. USBEndpoint *ep)
  156. {
  157. UHCIQueue *queue;
  158. queue = g_new0(UHCIQueue, 1);
  159. queue->uhci = s;
  160. queue->qh_addr = qh_addr;
  161. queue->token = uhci_queue_token(td);
  162. queue->ep = ep;
  163. QTAILQ_INIT(&queue->asyncs);
  164. QTAILQ_INSERT_HEAD(&s->queues, queue, next);
  165. queue->valid = QH_VALID;
  166. trace_usb_uhci_queue_add(queue->token);
  167. return queue;
  168. }
  169. static void uhci_queue_free(UHCIQueue *queue, const char *reason)
  170. {
  171. UHCIState *s = queue->uhci;
  172. UHCIAsync *async;
  173. while (!QTAILQ_EMPTY(&queue->asyncs)) {
  174. async = QTAILQ_FIRST(&queue->asyncs);
  175. uhci_async_cancel(async);
  176. }
  177. usb_device_ep_stopped(queue->ep->dev, queue->ep);
  178. trace_usb_uhci_queue_del(queue->token, reason);
  179. QTAILQ_REMOVE(&s->queues, queue, next);
  180. g_free(queue);
  181. }
  182. static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td)
  183. {
  184. uint32_t token = uhci_queue_token(td);
  185. UHCIQueue *queue;
  186. QTAILQ_FOREACH(queue, &s->queues, next) {
  187. if (queue->token == token) {
  188. return queue;
  189. }
  190. }
  191. return NULL;
  192. }
  193. static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td,
  194. uint32_t td_addr, bool queuing)
  195. {
  196. UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs);
  197. uint32_t queue_token_addr = (queue->token >> 8) & 0x7f;
  198. return queue->qh_addr == qh_addr &&
  199. queue->token == uhci_queue_token(td) &&
  200. queue_token_addr == queue->ep->dev->addr &&
  201. (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL ||
  202. first->td_addr == td_addr);
  203. }
  204. static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr)
  205. {
  206. UHCIAsync *async = g_new0(UHCIAsync, 1);
  207. async->queue = queue;
  208. async->td_addr = td_addr;
  209. usb_packet_init(&async->packet);
  210. trace_usb_uhci_packet_add(async->queue->token, async->td_addr);
  211. return async;
  212. }
  213. static void uhci_async_free(UHCIAsync *async)
  214. {
  215. trace_usb_uhci_packet_del(async->queue->token, async->td_addr);
  216. usb_packet_cleanup(&async->packet);
  217. if (async->buf != async->static_buf) {
  218. g_free(async->buf);
  219. }
  220. g_free(async);
  221. }
  222. static void uhci_async_link(UHCIAsync *async)
  223. {
  224. UHCIQueue *queue = async->queue;
  225. QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
  226. trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr);
  227. }
  228. static void uhci_async_unlink(UHCIAsync *async)
  229. {
  230. UHCIQueue *queue = async->queue;
  231. QTAILQ_REMOVE(&queue->asyncs, async, next);
  232. trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr);
  233. }
  234. static void uhci_async_cancel(UHCIAsync *async)
  235. {
  236. uhci_async_unlink(async);
  237. trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr,
  238. async->done);
  239. if (!async->done)
  240. usb_cancel_packet(&async->packet);
  241. uhci_async_free(async);
  242. }
  243. /*
  244. * Mark all outstanding async packets as invalid.
  245. * This is used for canceling them when TDs are removed by the HCD.
  246. */
  247. static void uhci_async_validate_begin(UHCIState *s)
  248. {
  249. UHCIQueue *queue;
  250. QTAILQ_FOREACH(queue, &s->queues, next) {
  251. queue->valid--;
  252. }
  253. }
  254. /*
  255. * Cancel async packets that are no longer valid
  256. */
  257. static void uhci_async_validate_end(UHCIState *s)
  258. {
  259. UHCIQueue *queue, *n;
  260. QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
  261. if (!queue->valid) {
  262. uhci_queue_free(queue, "validate-end");
  263. }
  264. }
  265. }
  266. static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
  267. {
  268. UHCIQueue *queue, *n;
  269. QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
  270. if (queue->ep->dev == dev) {
  271. uhci_queue_free(queue, "cancel-device");
  272. }
  273. }
  274. }
  275. static void uhci_async_cancel_all(UHCIState *s)
  276. {
  277. UHCIQueue *queue, *nq;
  278. QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) {
  279. uhci_queue_free(queue, "cancel-all");
  280. }
  281. }
  282. static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
  283. {
  284. UHCIQueue *queue;
  285. UHCIAsync *async;
  286. QTAILQ_FOREACH(queue, &s->queues, next) {
  287. QTAILQ_FOREACH(async, &queue->asyncs, next) {
  288. if (async->td_addr == td_addr) {
  289. return async;
  290. }
  291. }
  292. }
  293. return NULL;
  294. }
  295. static void uhci_update_irq(UHCIState *s)
  296. {
  297. int level;
  298. if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
  299. ((s->status2 & 2) && (s->intr & (1 << 3))) ||
  300. ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
  301. ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
  302. (s->status & UHCI_STS_HSERR) ||
  303. (s->status & UHCI_STS_HCPERR)) {
  304. level = 1;
  305. } else {
  306. level = 0;
  307. }
  308. pci_set_irq(&s->dev, level);
  309. }
  310. static void uhci_reset(DeviceState *dev)
  311. {
  312. PCIDevice *d = PCI_DEVICE(dev);
  313. UHCIState *s = UHCI(d);
  314. uint8_t *pci_conf;
  315. int i;
  316. UHCIPort *port;
  317. trace_usb_uhci_reset();
  318. pci_conf = s->dev.config;
  319. pci_conf[0x6a] = 0x01; /* usb clock */
  320. pci_conf[0x6b] = 0x00;
  321. s->cmd = 0;
  322. s->status = UHCI_STS_HCHALTED;
  323. s->status2 = 0;
  324. s->intr = 0;
  325. s->fl_base_addr = 0;
  326. s->sof_timing = 64;
  327. for(i = 0; i < NB_PORTS; i++) {
  328. port = &s->ports[i];
  329. port->ctrl = 0x0080;
  330. if (port->port.dev && port->port.dev->attached) {
  331. usb_port_reset(&port->port);
  332. }
  333. }
  334. uhci_async_cancel_all(s);
  335. qemu_bh_cancel(s->bh);
  336. uhci_update_irq(s);
  337. }
  338. static const VMStateDescription vmstate_uhci_port = {
  339. .name = "uhci port",
  340. .version_id = 1,
  341. .minimum_version_id = 1,
  342. .fields = (VMStateField[]) {
  343. VMSTATE_UINT16(ctrl, UHCIPort),
  344. VMSTATE_END_OF_LIST()
  345. }
  346. };
  347. static int uhci_post_load(void *opaque, int version_id)
  348. {
  349. UHCIState *s = opaque;
  350. if (version_id < 2) {
  351. s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
  352. (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ);
  353. }
  354. return 0;
  355. }
  356. static const VMStateDescription vmstate_uhci = {
  357. .name = "uhci",
  358. .version_id = 3,
  359. .minimum_version_id = 1,
  360. .post_load = uhci_post_load,
  361. .fields = (VMStateField[]) {
  362. VMSTATE_PCI_DEVICE(dev, UHCIState),
  363. VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL),
  364. VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
  365. vmstate_uhci_port, UHCIPort),
  366. VMSTATE_UINT16(cmd, UHCIState),
  367. VMSTATE_UINT16(status, UHCIState),
  368. VMSTATE_UINT16(intr, UHCIState),
  369. VMSTATE_UINT16(frnum, UHCIState),
  370. VMSTATE_UINT32(fl_base_addr, UHCIState),
  371. VMSTATE_UINT8(sof_timing, UHCIState),
  372. VMSTATE_UINT8(status2, UHCIState),
  373. VMSTATE_TIMER_PTR(frame_timer, UHCIState),
  374. VMSTATE_INT64_V(expire_time, UHCIState, 2),
  375. VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3),
  376. VMSTATE_END_OF_LIST()
  377. }
  378. };
  379. static void uhci_port_write(void *opaque, hwaddr addr,
  380. uint64_t val, unsigned size)
  381. {
  382. UHCIState *s = opaque;
  383. trace_usb_uhci_mmio_writew(addr, val);
  384. switch(addr) {
  385. case 0x00:
  386. if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
  387. /* start frame processing */
  388. trace_usb_uhci_schedule_start();
  389. s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
  390. (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ);
  391. timer_mod(s->frame_timer, s->expire_time);
  392. s->status &= ~UHCI_STS_HCHALTED;
  393. } else if (!(val & UHCI_CMD_RS)) {
  394. s->status |= UHCI_STS_HCHALTED;
  395. }
  396. if (val & UHCI_CMD_GRESET) {
  397. UHCIPort *port;
  398. int i;
  399. /* send reset on the USB bus */
  400. for(i = 0; i < NB_PORTS; i++) {
  401. port = &s->ports[i];
  402. usb_device_reset(port->port.dev);
  403. }
  404. uhci_reset(DEVICE(s));
  405. return;
  406. }
  407. if (val & UHCI_CMD_HCRESET) {
  408. uhci_reset(DEVICE(s));
  409. return;
  410. }
  411. s->cmd = val;
  412. if (val & UHCI_CMD_EGSM) {
  413. if ((s->ports[0].ctrl & UHCI_PORT_RD) ||
  414. (s->ports[1].ctrl & UHCI_PORT_RD)) {
  415. uhci_resume(s);
  416. }
  417. }
  418. break;
  419. case 0x02:
  420. s->status &= ~val;
  421. /* XXX: the chip spec is not coherent, so we add a hidden
  422. register to distinguish between IOC and SPD */
  423. if (val & UHCI_STS_USBINT)
  424. s->status2 = 0;
  425. uhci_update_irq(s);
  426. break;
  427. case 0x04:
  428. s->intr = val;
  429. uhci_update_irq(s);
  430. break;
  431. case 0x06:
  432. if (s->status & UHCI_STS_HCHALTED)
  433. s->frnum = val & 0x7ff;
  434. break;
  435. case 0x08:
  436. s->fl_base_addr &= 0xffff0000;
  437. s->fl_base_addr |= val & ~0xfff;
  438. break;
  439. case 0x0a:
  440. s->fl_base_addr &= 0x0000ffff;
  441. s->fl_base_addr |= (val << 16);
  442. break;
  443. case 0x0c:
  444. s->sof_timing = val & 0xff;
  445. break;
  446. case 0x10 ... 0x1f:
  447. {
  448. UHCIPort *port;
  449. USBDevice *dev;
  450. int n;
  451. n = (addr >> 1) & 7;
  452. if (n >= NB_PORTS)
  453. return;
  454. port = &s->ports[n];
  455. dev = port->port.dev;
  456. if (dev && dev->attached) {
  457. /* port reset */
  458. if ( (val & UHCI_PORT_RESET) &&
  459. !(port->ctrl & UHCI_PORT_RESET) ) {
  460. usb_device_reset(dev);
  461. }
  462. }
  463. port->ctrl &= UHCI_PORT_READ_ONLY;
  464. /* enabled may only be set if a device is connected */
  465. if (!(port->ctrl & UHCI_PORT_CCS)) {
  466. val &= ~UHCI_PORT_EN;
  467. }
  468. port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
  469. /* some bits are reset when a '1' is written to them */
  470. port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
  471. }
  472. break;
  473. }
  474. }
  475. static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
  476. {
  477. UHCIState *s = opaque;
  478. uint32_t val;
  479. switch(addr) {
  480. case 0x00:
  481. val = s->cmd;
  482. break;
  483. case 0x02:
  484. val = s->status;
  485. break;
  486. case 0x04:
  487. val = s->intr;
  488. break;
  489. case 0x06:
  490. val = s->frnum;
  491. break;
  492. case 0x08:
  493. val = s->fl_base_addr & 0xffff;
  494. break;
  495. case 0x0a:
  496. val = (s->fl_base_addr >> 16) & 0xffff;
  497. break;
  498. case 0x0c:
  499. val = s->sof_timing;
  500. break;
  501. case 0x10 ... 0x1f:
  502. {
  503. UHCIPort *port;
  504. int n;
  505. n = (addr >> 1) & 7;
  506. if (n >= NB_PORTS)
  507. goto read_default;
  508. port = &s->ports[n];
  509. val = port->ctrl;
  510. }
  511. break;
  512. default:
  513. read_default:
  514. val = 0xff7f; /* disabled port */
  515. break;
  516. }
  517. trace_usb_uhci_mmio_readw(addr, val);
  518. return val;
  519. }
  520. /* signal resume if controller suspended */
  521. static void uhci_resume (void *opaque)
  522. {
  523. UHCIState *s = (UHCIState *)opaque;
  524. if (!s)
  525. return;
  526. if (s->cmd & UHCI_CMD_EGSM) {
  527. s->cmd |= UHCI_CMD_FGR;
  528. s->status |= UHCI_STS_RD;
  529. uhci_update_irq(s);
  530. }
  531. }
  532. static void uhci_attach(USBPort *port1)
  533. {
  534. UHCIState *s = port1->opaque;
  535. UHCIPort *port = &s->ports[port1->index];
  536. /* set connect status */
  537. port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
  538. /* update speed */
  539. if (port->port.dev->speed == USB_SPEED_LOW) {
  540. port->ctrl |= UHCI_PORT_LSDA;
  541. } else {
  542. port->ctrl &= ~UHCI_PORT_LSDA;
  543. }
  544. uhci_resume(s);
  545. }
  546. static void uhci_detach(USBPort *port1)
  547. {
  548. UHCIState *s = port1->opaque;
  549. UHCIPort *port = &s->ports[port1->index];
  550. uhci_async_cancel_device(s, port1->dev);
  551. /* set connect status */
  552. if (port->ctrl & UHCI_PORT_CCS) {
  553. port->ctrl &= ~UHCI_PORT_CCS;
  554. port->ctrl |= UHCI_PORT_CSC;
  555. }
  556. /* disable port */
  557. if (port->ctrl & UHCI_PORT_EN) {
  558. port->ctrl &= ~UHCI_PORT_EN;
  559. port->ctrl |= UHCI_PORT_ENC;
  560. }
  561. uhci_resume(s);
  562. }
  563. static void uhci_child_detach(USBPort *port1, USBDevice *child)
  564. {
  565. UHCIState *s = port1->opaque;
  566. uhci_async_cancel_device(s, child);
  567. }
  568. static void uhci_wakeup(USBPort *port1)
  569. {
  570. UHCIState *s = port1->opaque;
  571. UHCIPort *port = &s->ports[port1->index];
  572. if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
  573. port->ctrl |= UHCI_PORT_RD;
  574. uhci_resume(s);
  575. }
  576. }
  577. static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
  578. {
  579. USBDevice *dev;
  580. int i;
  581. for (i = 0; i < NB_PORTS; i++) {
  582. UHCIPort *port = &s->ports[i];
  583. if (!(port->ctrl & UHCI_PORT_EN)) {
  584. continue;
  585. }
  586. dev = usb_find_device(&port->port, addr);
  587. if (dev != NULL) {
  588. return dev;
  589. }
  590. }
  591. return NULL;
  592. }
  593. static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link)
  594. {
  595. pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td));
  596. le32_to_cpus(&td->link);
  597. le32_to_cpus(&td->ctrl);
  598. le32_to_cpus(&td->token);
  599. le32_to_cpus(&td->buffer);
  600. }
  601. static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr,
  602. int status, uint32_t *int_mask)
  603. {
  604. uint32_t queue_token = uhci_queue_token(td);
  605. int ret;
  606. switch (status) {
  607. case USB_RET_NAK:
  608. td->ctrl |= TD_CTRL_NAK;
  609. return TD_RESULT_NEXT_QH;
  610. case USB_RET_STALL:
  611. td->ctrl |= TD_CTRL_STALL;
  612. trace_usb_uhci_packet_complete_stall(queue_token, td_addr);
  613. ret = TD_RESULT_NEXT_QH;
  614. break;
  615. case USB_RET_BABBLE:
  616. td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
  617. /* frame interrupted */
  618. trace_usb_uhci_packet_complete_babble(queue_token, td_addr);
  619. ret = TD_RESULT_STOP_FRAME;
  620. break;
  621. case USB_RET_IOERROR:
  622. case USB_RET_NODEV:
  623. default:
  624. td->ctrl |= TD_CTRL_TIMEOUT;
  625. td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT);
  626. trace_usb_uhci_packet_complete_error(queue_token, td_addr);
  627. ret = TD_RESULT_NEXT_QH;
  628. break;
  629. }
  630. td->ctrl &= ~TD_CTRL_ACTIVE;
  631. s->status |= UHCI_STS_USBERR;
  632. if (td->ctrl & TD_CTRL_IOC) {
  633. *int_mask |= 0x01;
  634. }
  635. uhci_update_irq(s);
  636. return ret;
  637. }
  638. static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
  639. {
  640. int len = 0, max_len;
  641. uint8_t pid;
  642. max_len = ((td->token >> 21) + 1) & 0x7ff;
  643. pid = td->token & 0xff;
  644. if (td->ctrl & TD_CTRL_IOS)
  645. td->ctrl &= ~TD_CTRL_ACTIVE;
  646. if (async->packet.status != USB_RET_SUCCESS) {
  647. return uhci_handle_td_error(s, td, async->td_addr,
  648. async->packet.status, int_mask);
  649. }
  650. len = async->packet.actual_length;
  651. td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
  652. /* The NAK bit may have been set by a previous frame, so clear it
  653. here. The docs are somewhat unclear, but win2k relies on this
  654. behavior. */
  655. td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
  656. if (td->ctrl & TD_CTRL_IOC)
  657. *int_mask |= 0x01;
  658. if (pid == USB_TOKEN_IN) {
  659. pci_dma_write(&s->dev, td->buffer, async->buf, len);
  660. if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
  661. *int_mask |= 0x02;
  662. /* short packet: do not update QH */
  663. trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
  664. async->td_addr);
  665. return TD_RESULT_NEXT_QH;
  666. }
  667. }
  668. /* success */
  669. trace_usb_uhci_packet_complete_success(async->queue->token,
  670. async->td_addr);
  671. return TD_RESULT_COMPLETE;
  672. }
  673. static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
  674. UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask)
  675. {
  676. int ret, max_len;
  677. bool spd;
  678. bool queuing = (q != NULL);
  679. uint8_t pid = td->token & 0xff;
  680. UHCIAsync *async;
  681. async = uhci_async_find_td(s, td_addr);
  682. if (async) {
  683. if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) {
  684. assert(q == NULL || q == async->queue);
  685. q = async->queue;
  686. } else {
  687. uhci_queue_free(async->queue, "guest re-used pending td");
  688. async = NULL;
  689. }
  690. }
  691. if (q == NULL) {
  692. q = uhci_queue_find(s, td);
  693. if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) {
  694. uhci_queue_free(q, "guest re-used qh");
  695. q = NULL;
  696. }
  697. }
  698. if (q) {
  699. q->valid = QH_VALID;
  700. }
  701. /* Is active ? */
  702. if (!(td->ctrl & TD_CTRL_ACTIVE)) {
  703. if (async) {
  704. /* Guest marked a pending td non-active, cancel the queue */
  705. uhci_queue_free(async->queue, "pending td non-active");
  706. }
  707. /*
  708. * ehci11d spec page 22: "Even if the Active bit in the TD is already
  709. * cleared when the TD is fetched ... an IOC interrupt is generated"
  710. */
  711. if (td->ctrl & TD_CTRL_IOC) {
  712. *int_mask |= 0x01;
  713. }
  714. return TD_RESULT_NEXT_QH;
  715. }
  716. switch (pid) {
  717. case USB_TOKEN_OUT:
  718. case USB_TOKEN_SETUP:
  719. case USB_TOKEN_IN:
  720. break;
  721. default:
  722. /* invalid pid : frame interrupted */
  723. s->status |= UHCI_STS_HCPERR;
  724. s->cmd &= ~UHCI_CMD_RS;
  725. uhci_update_irq(s);
  726. return TD_RESULT_STOP_FRAME;
  727. }
  728. if (async) {
  729. if (queuing) {
  730. /* we are busy filling the queue, we are not prepared
  731. to consume completed packages then, just leave them
  732. in async state */
  733. return TD_RESULT_ASYNC_CONT;
  734. }
  735. if (!async->done) {
  736. UHCI_TD last_td;
  737. UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs);
  738. /*
  739. * While we are waiting for the current td to complete, the guest
  740. * may have added more tds to the queue. Note we re-read the td
  741. * rather then caching it, as we want to see guest made changes!
  742. */
  743. uhci_read_td(s, &last_td, last->td_addr);
  744. uhci_queue_fill(async->queue, &last_td);
  745. return TD_RESULT_ASYNC_CONT;
  746. }
  747. uhci_async_unlink(async);
  748. goto done;
  749. }
  750. if (s->completions_only) {
  751. return TD_RESULT_ASYNC_CONT;
  752. }
  753. /* Allocate new packet */
  754. if (q == NULL) {
  755. USBDevice *dev;
  756. USBEndpoint *ep;
  757. dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
  758. if (dev == NULL) {
  759. return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV,
  760. int_mask);
  761. }
  762. ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
  763. q = uhci_queue_new(s, qh_addr, td, ep);
  764. }
  765. async = uhci_async_alloc(q, td_addr);
  766. max_len = ((td->token >> 21) + 1) & 0x7ff;
  767. spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0);
  768. usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd,
  769. (td->ctrl & TD_CTRL_IOC) != 0);
  770. if (max_len <= sizeof(async->static_buf)) {
  771. async->buf = async->static_buf;
  772. } else {
  773. async->buf = g_malloc(max_len);
  774. }
  775. usb_packet_addbuf(&async->packet, async->buf, max_len);
  776. switch(pid) {
  777. case USB_TOKEN_OUT:
  778. case USB_TOKEN_SETUP:
  779. pci_dma_read(&s->dev, td->buffer, async->buf, max_len);
  780. usb_handle_packet(q->ep->dev, &async->packet);
  781. if (async->packet.status == USB_RET_SUCCESS) {
  782. async->packet.actual_length = max_len;
  783. }
  784. break;
  785. case USB_TOKEN_IN:
  786. usb_handle_packet(q->ep->dev, &async->packet);
  787. break;
  788. default:
  789. abort(); /* Never to execute */
  790. }
  791. if (async->packet.status == USB_RET_ASYNC) {
  792. uhci_async_link(async);
  793. if (!queuing) {
  794. uhci_queue_fill(q, td);
  795. }
  796. return TD_RESULT_ASYNC_START;
  797. }
  798. done:
  799. ret = uhci_complete_td(s, td, async, int_mask);
  800. uhci_async_free(async);
  801. return ret;
  802. }
  803. static void uhci_async_complete(USBPort *port, USBPacket *packet)
  804. {
  805. UHCIAsync *async = container_of(packet, UHCIAsync, packet);
  806. UHCIState *s = async->queue->uhci;
  807. if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
  808. uhci_async_cancel(async);
  809. return;
  810. }
  811. async->done = 1;
  812. /* Force processing of this packet *now*, needed for migration */
  813. s->completions_only = true;
  814. qemu_bh_schedule(s->bh);
  815. }
  816. static int is_valid(uint32_t link)
  817. {
  818. return (link & 1) == 0;
  819. }
  820. static int is_qh(uint32_t link)
  821. {
  822. return (link & 2) != 0;
  823. }
  824. static int depth_first(uint32_t link)
  825. {
  826. return (link & 4) != 0;
  827. }
  828. /* QH DB used for detecting QH loops */
  829. #define UHCI_MAX_QUEUES 128
  830. typedef struct {
  831. uint32_t addr[UHCI_MAX_QUEUES];
  832. int count;
  833. } QhDb;
  834. static void qhdb_reset(QhDb *db)
  835. {
  836. db->count = 0;
  837. }
  838. /* Add QH to DB. Returns 1 if already present or DB is full. */
  839. static int qhdb_insert(QhDb *db, uint32_t addr)
  840. {
  841. int i;
  842. for (i = 0; i < db->count; i++)
  843. if (db->addr[i] == addr)
  844. return 1;
  845. if (db->count >= UHCI_MAX_QUEUES)
  846. return 1;
  847. db->addr[db->count++] = addr;
  848. return 0;
  849. }
  850. static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td)
  851. {
  852. uint32_t int_mask = 0;
  853. uint32_t plink = td->link;
  854. UHCI_TD ptd;
  855. int ret;
  856. while (is_valid(plink)) {
  857. uhci_read_td(q->uhci, &ptd, plink);
  858. if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
  859. break;
  860. }
  861. if (uhci_queue_token(&ptd) != q->token) {
  862. break;
  863. }
  864. trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
  865. ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask);
  866. if (ret == TD_RESULT_ASYNC_CONT) {
  867. break;
  868. }
  869. assert(ret == TD_RESULT_ASYNC_START);
  870. assert(int_mask == 0);
  871. plink = ptd.link;
  872. }
  873. usb_device_flush_ep_queue(q->ep->dev, q->ep);
  874. }
  875. static void uhci_process_frame(UHCIState *s)
  876. {
  877. uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
  878. uint32_t curr_qh, td_count = 0;
  879. int cnt, ret;
  880. UHCI_TD td;
  881. UHCI_QH qh;
  882. QhDb qhdb;
  883. frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
  884. pci_dma_read(&s->dev, frame_addr, &link, 4);
  885. le32_to_cpus(&link);
  886. int_mask = 0;
  887. curr_qh = 0;
  888. qhdb_reset(&qhdb);
  889. for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
  890. if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) {
  891. /* We've reached the usb 1.1 bandwidth, which is
  892. 1280 bytes/frame, stop processing */
  893. trace_usb_uhci_frame_stop_bandwidth();
  894. break;
  895. }
  896. if (is_qh(link)) {
  897. /* QH */
  898. trace_usb_uhci_qh_load(link & ~0xf);
  899. if (qhdb_insert(&qhdb, link)) {
  900. /*
  901. * We're going in circles. Which is not a bug because
  902. * HCD is allowed to do that as part of the BW management.
  903. *
  904. * Stop processing here if no transaction has been done
  905. * since we've been here last time.
  906. */
  907. if (td_count == 0) {
  908. trace_usb_uhci_frame_loop_stop_idle();
  909. break;
  910. } else {
  911. trace_usb_uhci_frame_loop_continue();
  912. td_count = 0;
  913. qhdb_reset(&qhdb);
  914. qhdb_insert(&qhdb, link);
  915. }
  916. }
  917. pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
  918. le32_to_cpus(&qh.link);
  919. le32_to_cpus(&qh.el_link);
  920. if (!is_valid(qh.el_link)) {
  921. /* QH w/o elements */
  922. curr_qh = 0;
  923. link = qh.link;
  924. } else {
  925. /* QH with elements */
  926. curr_qh = link;
  927. link = qh.el_link;
  928. }
  929. continue;
  930. }
  931. /* TD */
  932. uhci_read_td(s, &td, link);
  933. trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
  934. old_td_ctrl = td.ctrl;
  935. ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask);
  936. if (old_td_ctrl != td.ctrl) {
  937. /* update the status bits of the TD */
  938. val = cpu_to_le32(td.ctrl);
  939. pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
  940. }
  941. switch (ret) {
  942. case TD_RESULT_STOP_FRAME: /* interrupted frame */
  943. goto out;
  944. case TD_RESULT_NEXT_QH:
  945. case TD_RESULT_ASYNC_CONT:
  946. trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
  947. link = curr_qh ? qh.link : td.link;
  948. continue;
  949. case TD_RESULT_ASYNC_START:
  950. trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
  951. link = curr_qh ? qh.link : td.link;
  952. continue;
  953. case TD_RESULT_COMPLETE:
  954. trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
  955. link = td.link;
  956. td_count++;
  957. s->frame_bytes += (td.ctrl & 0x7ff) + 1;
  958. if (curr_qh) {
  959. /* update QH element link */
  960. qh.el_link = link;
  961. val = cpu_to_le32(qh.el_link);
  962. pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
  963. if (!depth_first(link)) {
  964. /* done with this QH */
  965. curr_qh = 0;
  966. link = qh.link;
  967. }
  968. }
  969. break;
  970. default:
  971. assert(!"unknown return code");
  972. }
  973. /* go to the next entry */
  974. }
  975. out:
  976. s->pending_int_mask |= int_mask;
  977. }
  978. static void uhci_bh(void *opaque)
  979. {
  980. UHCIState *s = opaque;
  981. uhci_process_frame(s);
  982. }
  983. static void uhci_frame_timer(void *opaque)
  984. {
  985. UHCIState *s = opaque;
  986. uint64_t t_now, t_last_run;
  987. int i, frames;
  988. const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ;
  989. s->completions_only = false;
  990. qemu_bh_cancel(s->bh);
  991. if (!(s->cmd & UHCI_CMD_RS)) {
  992. /* Full stop */
  993. trace_usb_uhci_schedule_stop();
  994. timer_del(s->frame_timer);
  995. uhci_async_cancel_all(s);
  996. /* set hchalted bit in status - UHCI11D 2.1.2 */
  997. s->status |= UHCI_STS_HCHALTED;
  998. return;
  999. }
  1000. /* We still store expire_time in our state, for migration */
  1001. t_last_run = s->expire_time - frame_t;
  1002. t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  1003. /* Process up to MAX_FRAMES_PER_TICK frames */
  1004. frames = (t_now - t_last_run) / frame_t;
  1005. if (frames > s->maxframes) {
  1006. int skipped = frames - s->maxframes;
  1007. s->expire_time += skipped * frame_t;
  1008. s->frnum = (s->frnum + skipped) & 0x7ff;
  1009. frames -= skipped;
  1010. }
  1011. if (frames > MAX_FRAMES_PER_TICK) {
  1012. frames = MAX_FRAMES_PER_TICK;
  1013. }
  1014. for (i = 0; i < frames; i++) {
  1015. s->frame_bytes = 0;
  1016. trace_usb_uhci_frame_start(s->frnum);
  1017. uhci_async_validate_begin(s);
  1018. uhci_process_frame(s);
  1019. uhci_async_validate_end(s);
  1020. /* The spec says frnum is the frame currently being processed, and
  1021. * the guest must look at frnum - 1 on interrupt, so inc frnum now */
  1022. s->frnum = (s->frnum + 1) & 0x7ff;
  1023. s->expire_time += frame_t;
  1024. }
  1025. /* Complete the previous frame(s) */
  1026. if (s->pending_int_mask) {
  1027. s->status2 |= s->pending_int_mask;
  1028. s->status |= UHCI_STS_USBINT;
  1029. uhci_update_irq(s);
  1030. }
  1031. s->pending_int_mask = 0;
  1032. timer_mod(s->frame_timer, t_now + frame_t);
  1033. }
  1034. static const MemoryRegionOps uhci_ioport_ops = {
  1035. .read = uhci_port_read,
  1036. .write = uhci_port_write,
  1037. .valid.min_access_size = 1,
  1038. .valid.max_access_size = 4,
  1039. .impl.min_access_size = 2,
  1040. .impl.max_access_size = 2,
  1041. .endianness = DEVICE_LITTLE_ENDIAN,
  1042. };
  1043. static USBPortOps uhci_port_ops = {
  1044. .attach = uhci_attach,
  1045. .detach = uhci_detach,
  1046. .child_detach = uhci_child_detach,
  1047. .wakeup = uhci_wakeup,
  1048. .complete = uhci_async_complete,
  1049. };
  1050. static USBBusOps uhci_bus_ops = {
  1051. };
  1052. static void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
  1053. {
  1054. Error *err = NULL;
  1055. PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
  1056. UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class);
  1057. UHCIState *s = UHCI(dev);
  1058. uint8_t *pci_conf = s->dev.config;
  1059. int i;
  1060. pci_conf[PCI_CLASS_PROG] = 0x00;
  1061. /* TODO: reset value should be 0. */
  1062. pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
  1063. pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
  1064. if (s->masterbus) {
  1065. USBPort *ports[NB_PORTS];
  1066. for(i = 0; i < NB_PORTS; i++) {
  1067. ports[i] = &s->ports[i].port;
  1068. }
  1069. usb_register_companion(s->masterbus, ports, NB_PORTS,
  1070. s->firstport, s, &uhci_port_ops,
  1071. USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
  1072. &err);
  1073. if (err) {
  1074. error_propagate(errp, err);
  1075. return;
  1076. }
  1077. } else {
  1078. usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev));
  1079. for (i = 0; i < NB_PORTS; i++) {
  1080. usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
  1081. USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
  1082. }
  1083. }
  1084. s->bh = qemu_bh_new(uhci_bh, s);
  1085. s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s);
  1086. s->num_ports_vmstate = NB_PORTS;
  1087. QTAILQ_INIT(&s->queues);
  1088. memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s,
  1089. "uhci", 0x20);
  1090. /* Use region 4 for consistency with real hardware. BSD guests seem
  1091. to rely on this. */
  1092. pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
  1093. }
  1094. static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
  1095. {
  1096. UHCIState *s = UHCI(dev);
  1097. uint8_t *pci_conf = s->dev.config;
  1098. /* USB misc control 1/2 */
  1099. pci_set_long(pci_conf + 0x40,0x00001000);
  1100. /* PM capability */
  1101. pci_set_long(pci_conf + 0x80,0x00020001);
  1102. /* USB legacy support */
  1103. pci_set_long(pci_conf + 0xc0,0x00002000);
  1104. usb_uhci_common_realize(dev, errp);
  1105. }
  1106. static void usb_uhci_exit(PCIDevice *dev)
  1107. {
  1108. UHCIState *s = UHCI(dev);
  1109. trace_usb_uhci_exit();
  1110. if (s->frame_timer) {
  1111. timer_del(s->frame_timer);
  1112. timer_free(s->frame_timer);
  1113. s->frame_timer = NULL;
  1114. }
  1115. if (s->bh) {
  1116. qemu_bh_delete(s->bh);
  1117. }
  1118. uhci_async_cancel_all(s);
  1119. if (!s->masterbus) {
  1120. usb_bus_release(&s->bus);
  1121. }
  1122. }
  1123. static Property uhci_properties_companion[] = {
  1124. DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
  1125. DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
  1126. DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
  1127. DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
  1128. DEFINE_PROP_END_OF_LIST(),
  1129. };
  1130. static Property uhci_properties_standalone[] = {
  1131. DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
  1132. DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
  1133. DEFINE_PROP_END_OF_LIST(),
  1134. };
  1135. static void uhci_class_init(ObjectClass *klass, void *data)
  1136. {
  1137. DeviceClass *dc = DEVICE_CLASS(klass);
  1138. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  1139. k->class_id = PCI_CLASS_SERIAL_USB;
  1140. dc->vmsd = &vmstate_uhci;
  1141. dc->reset = uhci_reset;
  1142. set_bit(DEVICE_CATEGORY_USB, dc->categories);
  1143. }
  1144. static const TypeInfo uhci_pci_type_info = {
  1145. .name = TYPE_UHCI,
  1146. .parent = TYPE_PCI_DEVICE,
  1147. .instance_size = sizeof(UHCIState),
  1148. .class_size = sizeof(UHCIPCIDeviceClass),
  1149. .abstract = true,
  1150. .class_init = uhci_class_init,
  1151. .interfaces = (InterfaceInfo[]) {
  1152. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  1153. { },
  1154. },
  1155. };
  1156. static void uhci_data_class_init(ObjectClass *klass, void *data)
  1157. {
  1158. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  1159. DeviceClass *dc = DEVICE_CLASS(klass);
  1160. UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class);
  1161. UHCIInfo *info = data;
  1162. k->realize = info->realize ? info->realize : usb_uhci_common_realize;
  1163. k->exit = info->unplug ? usb_uhci_exit : NULL;
  1164. k->vendor_id = info->vendor_id;
  1165. k->device_id = info->device_id;
  1166. k->revision = info->revision;
  1167. if (!info->unplug) {
  1168. /* uhci controllers in companion setups can't be hotplugged */
  1169. dc->hotpluggable = false;
  1170. device_class_set_props(dc, uhci_properties_companion);
  1171. } else {
  1172. device_class_set_props(dc, uhci_properties_standalone);
  1173. }
  1174. u->info = *info;
  1175. }
  1176. static UHCIInfo uhci_info[] = {
  1177. {
  1178. .name = "piix3-usb-uhci",
  1179. .vendor_id = PCI_VENDOR_ID_INTEL,
  1180. .device_id = PCI_DEVICE_ID_INTEL_82371SB_2,
  1181. .revision = 0x01,
  1182. .irq_pin = 3,
  1183. .unplug = true,
  1184. },{
  1185. .name = "piix4-usb-uhci",
  1186. .vendor_id = PCI_VENDOR_ID_INTEL,
  1187. .device_id = PCI_DEVICE_ID_INTEL_82371AB_2,
  1188. .revision = 0x01,
  1189. .irq_pin = 3,
  1190. .unplug = true,
  1191. },{
  1192. .name = "vt82c686b-usb-uhci",
  1193. .vendor_id = PCI_VENDOR_ID_VIA,
  1194. .device_id = PCI_DEVICE_ID_VIA_UHCI,
  1195. .revision = 0x01,
  1196. .irq_pin = 3,
  1197. .realize = usb_uhci_vt82c686b_realize,
  1198. .unplug = true,
  1199. },{
  1200. .name = "ich9-usb-uhci1", /* 00:1d.0 */
  1201. .vendor_id = PCI_VENDOR_ID_INTEL,
  1202. .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1,
  1203. .revision = 0x03,
  1204. .irq_pin = 0,
  1205. .unplug = false,
  1206. },{
  1207. .name = "ich9-usb-uhci2", /* 00:1d.1 */
  1208. .vendor_id = PCI_VENDOR_ID_INTEL,
  1209. .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2,
  1210. .revision = 0x03,
  1211. .irq_pin = 1,
  1212. .unplug = false,
  1213. },{
  1214. .name = "ich9-usb-uhci3", /* 00:1d.2 */
  1215. .vendor_id = PCI_VENDOR_ID_INTEL,
  1216. .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3,
  1217. .revision = 0x03,
  1218. .irq_pin = 2,
  1219. .unplug = false,
  1220. },{
  1221. .name = "ich9-usb-uhci4", /* 00:1a.0 */
  1222. .vendor_id = PCI_VENDOR_ID_INTEL,
  1223. .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4,
  1224. .revision = 0x03,
  1225. .irq_pin = 0,
  1226. .unplug = false,
  1227. },{
  1228. .name = "ich9-usb-uhci5", /* 00:1a.1 */
  1229. .vendor_id = PCI_VENDOR_ID_INTEL,
  1230. .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5,
  1231. .revision = 0x03,
  1232. .irq_pin = 1,
  1233. .unplug = false,
  1234. },{
  1235. .name = "ich9-usb-uhci6", /* 00:1a.2 */
  1236. .vendor_id = PCI_VENDOR_ID_INTEL,
  1237. .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6,
  1238. .revision = 0x03,
  1239. .irq_pin = 2,
  1240. .unplug = false,
  1241. }
  1242. };
  1243. static void uhci_register_types(void)
  1244. {
  1245. TypeInfo uhci_type_info = {
  1246. .parent = TYPE_UHCI,
  1247. .class_init = uhci_data_class_init,
  1248. };
  1249. int i;
  1250. type_register_static(&uhci_pci_type_info);
  1251. for (i = 0; i < ARRAY_SIZE(uhci_info); i++) {
  1252. uhci_type_info.name = uhci_info[i].name;
  1253. uhci_type_info.class_data = uhci_info + i;
  1254. type_register(&uhci_type_info);
  1255. }
  1256. }
  1257. type_init(uhci_register_types)