mc146818rtc.c 32 KB

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  1. /*
  2. * QEMU MC146818 RTC emulation
  3. *
  4. * Copyright (c) 2003-2004 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "qemu/osdep.h"
  25. #include "qemu-common.h"
  26. #include "qemu/cutils.h"
  27. #include "qemu/module.h"
  28. #include "qemu/bcd.h"
  29. #include "hw/acpi/aml-build.h"
  30. #include "hw/irq.h"
  31. #include "hw/qdev-properties.h"
  32. #include "qemu/timer.h"
  33. #include "sysemu/sysemu.h"
  34. #include "sysemu/replay.h"
  35. #include "sysemu/reset.h"
  36. #include "sysemu/runstate.h"
  37. #include "hw/rtc/mc146818rtc.h"
  38. #include "hw/rtc/mc146818rtc_regs.h"
  39. #include "migration/vmstate.h"
  40. #include "qapi/error.h"
  41. #include "qapi/qapi-events-misc-target.h"
  42. #include "qapi/visitor.h"
  43. #include "exec/address-spaces.h"
  44. #include "hw/rtc/mc146818rtc_regs.h"
  45. #ifdef TARGET_I386
  46. #include "qapi/qapi-commands-misc-target.h"
  47. #include "hw/i386/apic.h"
  48. #endif
  49. //#define DEBUG_CMOS
  50. //#define DEBUG_COALESCED
  51. #ifdef DEBUG_CMOS
  52. # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
  53. #else
  54. # define CMOS_DPRINTF(format, ...) do { } while (0)
  55. #endif
  56. #ifdef DEBUG_COALESCED
  57. # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__)
  58. #else
  59. # define DPRINTF_C(format, ...) do { } while (0)
  60. #endif
  61. #define SEC_PER_MIN 60
  62. #define MIN_PER_HOUR 60
  63. #define SEC_PER_HOUR 3600
  64. #define HOUR_PER_DAY 24
  65. #define SEC_PER_DAY 86400
  66. #define RTC_REINJECT_ON_ACK_COUNT 20
  67. #define RTC_CLOCK_RATE 32768
  68. #define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768)
  69. static void rtc_set_time(RTCState *s);
  70. static void rtc_update_time(RTCState *s);
  71. static void rtc_set_cmos(RTCState *s, const struct tm *tm);
  72. static inline int rtc_from_bcd(RTCState *s, int a);
  73. static uint64_t get_next_alarm(RTCState *s);
  74. static inline bool rtc_running(RTCState *s)
  75. {
  76. return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
  77. (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
  78. }
  79. static uint64_t get_guest_rtc_ns(RTCState *s)
  80. {
  81. uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
  82. return s->base_rtc * NANOSECONDS_PER_SECOND +
  83. guest_clock - s->last_update + s->offset;
  84. }
  85. static void rtc_coalesced_timer_update(RTCState *s)
  86. {
  87. if (s->irq_coalesced == 0) {
  88. timer_del(s->coalesced_timer);
  89. } else {
  90. /* divide each RTC interval to 2 - 8 smaller intervals */
  91. int c = MIN(s->irq_coalesced, 7) + 1;
  92. int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
  93. periodic_clock_to_ns(s->period / c);
  94. timer_mod(s->coalesced_timer, next_clock);
  95. }
  96. }
  97. static QLIST_HEAD(, RTCState) rtc_devices =
  98. QLIST_HEAD_INITIALIZER(rtc_devices);
  99. #ifdef TARGET_I386
  100. void qmp_rtc_reset_reinjection(Error **errp)
  101. {
  102. RTCState *s;
  103. QLIST_FOREACH(s, &rtc_devices, link) {
  104. s->irq_coalesced = 0;
  105. }
  106. }
  107. static bool rtc_policy_slew_deliver_irq(RTCState *s)
  108. {
  109. apic_reset_irq_delivered();
  110. qemu_irq_raise(s->irq);
  111. return apic_get_irq_delivered();
  112. }
  113. static void rtc_coalesced_timer(void *opaque)
  114. {
  115. RTCState *s = opaque;
  116. if (s->irq_coalesced != 0) {
  117. s->cmos_data[RTC_REG_C] |= 0xc0;
  118. DPRINTF_C("cmos: injecting from timer\n");
  119. if (rtc_policy_slew_deliver_irq(s)) {
  120. s->irq_coalesced--;
  121. DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
  122. s->irq_coalesced);
  123. }
  124. }
  125. rtc_coalesced_timer_update(s);
  126. }
  127. #else
  128. static bool rtc_policy_slew_deliver_irq(RTCState *s)
  129. {
  130. assert(0);
  131. return false;
  132. }
  133. #endif
  134. static uint32_t rtc_periodic_clock_ticks(RTCState *s)
  135. {
  136. int period_code;
  137. if (!(s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
  138. return 0;
  139. }
  140. period_code = s->cmos_data[RTC_REG_A] & 0x0f;
  141. return periodic_period_to_clock(period_code);
  142. }
  143. /*
  144. * handle periodic timer. @old_period indicates the periodic timer update
  145. * is just due to period adjustment.
  146. */
  147. static void
  148. periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_period, bool period_change)
  149. {
  150. uint32_t period;
  151. int64_t cur_clock, next_irq_clock, lost_clock = 0;
  152. period = rtc_periodic_clock_ticks(s);
  153. s->period = period;
  154. if (!period) {
  155. s->irq_coalesced = 0;
  156. timer_del(s->periodic_timer);
  157. return;
  158. }
  159. /* compute 32 khz clock */
  160. cur_clock =
  161. muldiv64(current_time, RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND);
  162. /*
  163. * if the periodic timer's update is due to period re-configuration,
  164. * we should count the clock since last interrupt.
  165. */
  166. if (old_period && period_change) {
  167. int64_t last_periodic_clock, next_periodic_clock;
  168. next_periodic_clock = muldiv64(s->next_periodic_time,
  169. RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND);
  170. last_periodic_clock = next_periodic_clock - old_period;
  171. lost_clock = cur_clock - last_periodic_clock;
  172. assert(lost_clock >= 0);
  173. }
  174. /*
  175. * s->irq_coalesced can change for two reasons:
  176. *
  177. * a) if one or more periodic timer interrupts have been lost,
  178. * lost_clock will be more that a period.
  179. *
  180. * b) when the period may be reconfigured, we expect the OS to
  181. * treat delayed tick as the new period. So, when switching
  182. * from a shorter to a longer period, scale down the missing,
  183. * because the OS will treat past delayed ticks as longer
  184. * (leftovers are put back into lost_clock). When switching
  185. * to a shorter period, scale up the missing ticks since the
  186. * OS handler will treat past delayed ticks as shorter.
  187. */
  188. if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
  189. uint32_t old_irq_coalesced = s->irq_coalesced;
  190. lost_clock += old_irq_coalesced * old_period;
  191. s->irq_coalesced = lost_clock / s->period;
  192. lost_clock %= s->period;
  193. if (old_irq_coalesced != s->irq_coalesced ||
  194. old_period != s->period) {
  195. DPRINTF_C("cmos: coalesced irqs scaled from %d to %d, "
  196. "period scaled from %d to %d\n", old_irq_coalesced,
  197. s->irq_coalesced, old_period, s->period);
  198. rtc_coalesced_timer_update(s);
  199. }
  200. } else {
  201. /*
  202. * no way to compensate the interrupt if LOST_TICK_POLICY_SLEW
  203. * is not used, we should make the time progress anyway.
  204. */
  205. lost_clock = MIN(lost_clock, period);
  206. }
  207. assert(lost_clock >= 0 && lost_clock <= period);
  208. next_irq_clock = cur_clock + period - lost_clock;
  209. s->next_periodic_time = periodic_clock_to_ns(next_irq_clock) + 1;
  210. timer_mod(s->periodic_timer, s->next_periodic_time);
  211. }
  212. static void rtc_periodic_timer(void *opaque)
  213. {
  214. RTCState *s = opaque;
  215. periodic_timer_update(s, s->next_periodic_time, s->period, false);
  216. s->cmos_data[RTC_REG_C] |= REG_C_PF;
  217. if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
  218. s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
  219. if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
  220. if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
  221. s->irq_reinject_on_ack_count = 0;
  222. if (!rtc_policy_slew_deliver_irq(s)) {
  223. s->irq_coalesced++;
  224. rtc_coalesced_timer_update(s);
  225. DPRINTF_C("cmos: coalesced irqs increased to %d\n",
  226. s->irq_coalesced);
  227. }
  228. } else
  229. qemu_irq_raise(s->irq);
  230. }
  231. }
  232. /* handle update-ended timer */
  233. static void check_update_timer(RTCState *s)
  234. {
  235. uint64_t next_update_time;
  236. uint64_t guest_nsec;
  237. int next_alarm_sec;
  238. /* From the data sheet: "Holding the dividers in reset prevents
  239. * interrupts from operating, while setting the SET bit allows"
  240. * them to occur.
  241. */
  242. if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
  243. assert((s->cmos_data[RTC_REG_A] & REG_A_UIP) == 0);
  244. timer_del(s->update_timer);
  245. return;
  246. }
  247. guest_nsec = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
  248. next_update_time = qemu_clock_get_ns(rtc_clock)
  249. + NANOSECONDS_PER_SECOND - guest_nsec;
  250. /* Compute time of next alarm. One second is already accounted
  251. * for in next_update_time.
  252. */
  253. next_alarm_sec = get_next_alarm(s);
  254. s->next_alarm_time = next_update_time +
  255. (next_alarm_sec - 1) * NANOSECONDS_PER_SECOND;
  256. /* If update_in_progress latched the UIP bit, we must keep the timer
  257. * programmed to the next second, so that UIP is cleared. Otherwise,
  258. * if UF is already set, we might be able to optimize.
  259. */
  260. if (!(s->cmos_data[RTC_REG_A] & REG_A_UIP) &&
  261. (s->cmos_data[RTC_REG_C] & REG_C_UF)) {
  262. /* If AF cannot change (i.e. either it is set already, or
  263. * SET=1 and then the time is not updated), nothing to do.
  264. */
  265. if ((s->cmos_data[RTC_REG_B] & REG_B_SET) ||
  266. (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
  267. timer_del(s->update_timer);
  268. return;
  269. }
  270. /* UF is set, but AF is clear. Program the timer to target
  271. * the alarm time. */
  272. next_update_time = s->next_alarm_time;
  273. }
  274. if (next_update_time != timer_expire_time_ns(s->update_timer)) {
  275. timer_mod(s->update_timer, next_update_time);
  276. }
  277. }
  278. static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
  279. {
  280. if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
  281. hour %= 12;
  282. if (s->cmos_data[RTC_HOURS] & 0x80) {
  283. hour += 12;
  284. }
  285. }
  286. return hour;
  287. }
  288. static uint64_t get_next_alarm(RTCState *s)
  289. {
  290. int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
  291. int32_t hour, min, sec;
  292. rtc_update_time(s);
  293. alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
  294. alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
  295. alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
  296. alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
  297. cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
  298. cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
  299. cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
  300. cur_hour = convert_hour(s, cur_hour);
  301. if (alarm_hour == -1) {
  302. alarm_hour = cur_hour;
  303. if (alarm_min == -1) {
  304. alarm_min = cur_min;
  305. if (alarm_sec == -1) {
  306. alarm_sec = cur_sec + 1;
  307. } else if (cur_sec > alarm_sec) {
  308. alarm_min++;
  309. }
  310. } else if (cur_min == alarm_min) {
  311. if (alarm_sec == -1) {
  312. alarm_sec = cur_sec + 1;
  313. } else {
  314. if (cur_sec > alarm_sec) {
  315. alarm_hour++;
  316. }
  317. }
  318. if (alarm_sec == SEC_PER_MIN) {
  319. /* wrap to next hour, minutes is not in don't care mode */
  320. alarm_sec = 0;
  321. alarm_hour++;
  322. }
  323. } else if (cur_min > alarm_min) {
  324. alarm_hour++;
  325. }
  326. } else if (cur_hour == alarm_hour) {
  327. if (alarm_min == -1) {
  328. alarm_min = cur_min;
  329. if (alarm_sec == -1) {
  330. alarm_sec = cur_sec + 1;
  331. } else if (cur_sec > alarm_sec) {
  332. alarm_min++;
  333. }
  334. if (alarm_sec == SEC_PER_MIN) {
  335. alarm_sec = 0;
  336. alarm_min++;
  337. }
  338. /* wrap to next day, hour is not in don't care mode */
  339. alarm_min %= MIN_PER_HOUR;
  340. } else if (cur_min == alarm_min) {
  341. if (alarm_sec == -1) {
  342. alarm_sec = cur_sec + 1;
  343. }
  344. /* wrap to next day, hours+minutes not in don't care mode */
  345. alarm_sec %= SEC_PER_MIN;
  346. }
  347. }
  348. /* values that are still don't care fire at the next min/sec */
  349. if (alarm_min == -1) {
  350. alarm_min = 0;
  351. }
  352. if (alarm_sec == -1) {
  353. alarm_sec = 0;
  354. }
  355. /* keep values in range */
  356. if (alarm_sec == SEC_PER_MIN) {
  357. alarm_sec = 0;
  358. alarm_min++;
  359. }
  360. if (alarm_min == MIN_PER_HOUR) {
  361. alarm_min = 0;
  362. alarm_hour++;
  363. }
  364. alarm_hour %= HOUR_PER_DAY;
  365. hour = alarm_hour - cur_hour;
  366. min = hour * MIN_PER_HOUR + alarm_min - cur_min;
  367. sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
  368. return sec <= 0 ? sec + SEC_PER_DAY : sec;
  369. }
  370. static void rtc_update_timer(void *opaque)
  371. {
  372. RTCState *s = opaque;
  373. int32_t irqs = REG_C_UF;
  374. int32_t new_irqs;
  375. assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
  376. /* UIP might have been latched, update time and clear it. */
  377. rtc_update_time(s);
  378. s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
  379. if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {
  380. irqs |= REG_C_AF;
  381. if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
  382. qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC, NULL);
  383. }
  384. }
  385. new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
  386. s->cmos_data[RTC_REG_C] |= irqs;
  387. if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
  388. s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
  389. qemu_irq_raise(s->irq);
  390. }
  391. check_update_timer(s);
  392. }
  393. static void cmos_ioport_write(void *opaque, hwaddr addr,
  394. uint64_t data, unsigned size)
  395. {
  396. RTCState *s = opaque;
  397. uint32_t old_period;
  398. bool update_periodic_timer;
  399. if ((addr & 1) == 0) {
  400. s->cmos_index = data & 0x7f;
  401. } else {
  402. CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
  403. s->cmos_index, data);
  404. switch(s->cmos_index) {
  405. case RTC_SECONDS_ALARM:
  406. case RTC_MINUTES_ALARM:
  407. case RTC_HOURS_ALARM:
  408. s->cmos_data[s->cmos_index] = data;
  409. check_update_timer(s);
  410. break;
  411. case RTC_IBM_PS2_CENTURY_BYTE:
  412. s->cmos_index = RTC_CENTURY;
  413. /* fall through */
  414. case RTC_CENTURY:
  415. case RTC_SECONDS:
  416. case RTC_MINUTES:
  417. case RTC_HOURS:
  418. case RTC_DAY_OF_WEEK:
  419. case RTC_DAY_OF_MONTH:
  420. case RTC_MONTH:
  421. case RTC_YEAR:
  422. s->cmos_data[s->cmos_index] = data;
  423. /* if in set mode, do not update the time */
  424. if (rtc_running(s)) {
  425. rtc_set_time(s);
  426. check_update_timer(s);
  427. }
  428. break;
  429. case RTC_REG_A:
  430. update_periodic_timer = (s->cmos_data[RTC_REG_A] ^ data) & 0x0f;
  431. old_period = rtc_periodic_clock_ticks(s);
  432. if ((data & 0x60) == 0x60) {
  433. if (rtc_running(s)) {
  434. rtc_update_time(s);
  435. }
  436. /* What happens to UIP when divider reset is enabled is
  437. * unclear from the datasheet. Shouldn't matter much
  438. * though.
  439. */
  440. s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
  441. } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
  442. (data & 0x70) <= 0x20) {
  443. /* when the divider reset is removed, the first update cycle
  444. * begins one-half second later*/
  445. if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
  446. s->offset = 500000000;
  447. rtc_set_time(s);
  448. }
  449. s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
  450. }
  451. /* UIP bit is read only */
  452. s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
  453. (s->cmos_data[RTC_REG_A] & REG_A_UIP);
  454. if (update_periodic_timer) {
  455. periodic_timer_update(s, qemu_clock_get_ns(rtc_clock),
  456. old_period, true);
  457. }
  458. check_update_timer(s);
  459. break;
  460. case RTC_REG_B:
  461. update_periodic_timer = (s->cmos_data[RTC_REG_B] ^ data)
  462. & REG_B_PIE;
  463. old_period = rtc_periodic_clock_ticks(s);
  464. if (data & REG_B_SET) {
  465. /* update cmos to when the rtc was stopping */
  466. if (rtc_running(s)) {
  467. rtc_update_time(s);
  468. }
  469. /* set mode: reset UIP mode */
  470. s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
  471. data &= ~REG_B_UIE;
  472. } else {
  473. /* if disabling set mode, update the time */
  474. if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
  475. (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
  476. s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
  477. rtc_set_time(s);
  478. }
  479. }
  480. /* if an interrupt flag is already set when the interrupt
  481. * becomes enabled, raise an interrupt immediately. */
  482. if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
  483. s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
  484. qemu_irq_raise(s->irq);
  485. } else {
  486. s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
  487. qemu_irq_lower(s->irq);
  488. }
  489. s->cmos_data[RTC_REG_B] = data;
  490. if (update_periodic_timer) {
  491. periodic_timer_update(s, qemu_clock_get_ns(rtc_clock),
  492. old_period, true);
  493. }
  494. check_update_timer(s);
  495. break;
  496. case RTC_REG_C:
  497. case RTC_REG_D:
  498. /* cannot write to them */
  499. break;
  500. default:
  501. s->cmos_data[s->cmos_index] = data;
  502. break;
  503. }
  504. }
  505. }
  506. static inline int rtc_to_bcd(RTCState *s, int a)
  507. {
  508. if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
  509. return a;
  510. } else {
  511. return ((a / 10) << 4) | (a % 10);
  512. }
  513. }
  514. static inline int rtc_from_bcd(RTCState *s, int a)
  515. {
  516. if ((a & 0xc0) == 0xc0) {
  517. return -1;
  518. }
  519. if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
  520. return a;
  521. } else {
  522. return ((a >> 4) * 10) + (a & 0x0f);
  523. }
  524. }
  525. static void rtc_get_time(RTCState *s, struct tm *tm)
  526. {
  527. tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
  528. tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
  529. tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
  530. if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
  531. tm->tm_hour %= 12;
  532. if (s->cmos_data[RTC_HOURS] & 0x80) {
  533. tm->tm_hour += 12;
  534. }
  535. }
  536. tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
  537. tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
  538. tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
  539. tm->tm_year =
  540. rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
  541. rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
  542. }
  543. static void rtc_set_time(RTCState *s)
  544. {
  545. struct tm tm;
  546. rtc_get_time(s, &tm);
  547. s->base_rtc = mktimegm(&tm);
  548. s->last_update = qemu_clock_get_ns(rtc_clock);
  549. qapi_event_send_rtc_change(qemu_timedate_diff(&tm));
  550. }
  551. static void rtc_set_cmos(RTCState *s, const struct tm *tm)
  552. {
  553. int year;
  554. s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
  555. s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
  556. if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
  557. /* 24 hour format */
  558. s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
  559. } else {
  560. /* 12 hour format */
  561. int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
  562. s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
  563. if (tm->tm_hour >= 12)
  564. s->cmos_data[RTC_HOURS] |= 0x80;
  565. }
  566. s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
  567. s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
  568. s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
  569. year = tm->tm_year + 1900 - s->base_year;
  570. s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
  571. s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
  572. }
  573. static void rtc_update_time(RTCState *s)
  574. {
  575. struct tm ret;
  576. time_t guest_sec;
  577. int64_t guest_nsec;
  578. guest_nsec = get_guest_rtc_ns(s);
  579. guest_sec = guest_nsec / NANOSECONDS_PER_SECOND;
  580. gmtime_r(&guest_sec, &ret);
  581. /* Is SET flag of Register B disabled? */
  582. if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) {
  583. rtc_set_cmos(s, &ret);
  584. }
  585. }
  586. static int update_in_progress(RTCState *s)
  587. {
  588. int64_t guest_nsec;
  589. if (!rtc_running(s)) {
  590. return 0;
  591. }
  592. if (timer_pending(s->update_timer)) {
  593. int64_t next_update_time = timer_expire_time_ns(s->update_timer);
  594. /* Latch UIP until the timer expires. */
  595. if (qemu_clock_get_ns(rtc_clock) >=
  596. (next_update_time - UIP_HOLD_LENGTH)) {
  597. s->cmos_data[RTC_REG_A] |= REG_A_UIP;
  598. return 1;
  599. }
  600. }
  601. guest_nsec = get_guest_rtc_ns(s);
  602. /* UIP bit will be set at last 244us of every second. */
  603. if ((guest_nsec % NANOSECONDS_PER_SECOND) >=
  604. (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)) {
  605. return 1;
  606. }
  607. return 0;
  608. }
  609. static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
  610. unsigned size)
  611. {
  612. RTCState *s = opaque;
  613. int ret;
  614. if ((addr & 1) == 0) {
  615. return 0xff;
  616. } else {
  617. switch(s->cmos_index) {
  618. case RTC_IBM_PS2_CENTURY_BYTE:
  619. s->cmos_index = RTC_CENTURY;
  620. /* fall through */
  621. case RTC_CENTURY:
  622. case RTC_SECONDS:
  623. case RTC_MINUTES:
  624. case RTC_HOURS:
  625. case RTC_DAY_OF_WEEK:
  626. case RTC_DAY_OF_MONTH:
  627. case RTC_MONTH:
  628. case RTC_YEAR:
  629. /* if not in set mode, calibrate cmos before
  630. * reading*/
  631. if (rtc_running(s)) {
  632. rtc_update_time(s);
  633. }
  634. ret = s->cmos_data[s->cmos_index];
  635. break;
  636. case RTC_REG_A:
  637. ret = s->cmos_data[s->cmos_index];
  638. if (update_in_progress(s)) {
  639. ret |= REG_A_UIP;
  640. }
  641. break;
  642. case RTC_REG_C:
  643. ret = s->cmos_data[s->cmos_index];
  644. qemu_irq_lower(s->irq);
  645. s->cmos_data[RTC_REG_C] = 0x00;
  646. if (ret & (REG_C_UF | REG_C_AF)) {
  647. check_update_timer(s);
  648. }
  649. if(s->irq_coalesced &&
  650. (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
  651. s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
  652. s->irq_reinject_on_ack_count++;
  653. s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
  654. DPRINTF_C("cmos: injecting on ack\n");
  655. if (rtc_policy_slew_deliver_irq(s)) {
  656. s->irq_coalesced--;
  657. DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
  658. s->irq_coalesced);
  659. }
  660. }
  661. break;
  662. default:
  663. ret = s->cmos_data[s->cmos_index];
  664. break;
  665. }
  666. CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
  667. s->cmos_index, ret);
  668. return ret;
  669. }
  670. }
  671. void rtc_set_memory(ISADevice *dev, int addr, int val)
  672. {
  673. RTCState *s = MC146818_RTC(dev);
  674. if (addr >= 0 && addr <= 127)
  675. s->cmos_data[addr] = val;
  676. }
  677. int rtc_get_memory(ISADevice *dev, int addr)
  678. {
  679. RTCState *s = MC146818_RTC(dev);
  680. assert(addr >= 0 && addr <= 127);
  681. return s->cmos_data[addr];
  682. }
  683. static void rtc_set_date_from_host(ISADevice *dev)
  684. {
  685. RTCState *s = MC146818_RTC(dev);
  686. struct tm tm;
  687. qemu_get_timedate(&tm, 0);
  688. s->base_rtc = mktimegm(&tm);
  689. s->last_update = qemu_clock_get_ns(rtc_clock);
  690. s->offset = 0;
  691. /* set the CMOS date */
  692. rtc_set_cmos(s, &tm);
  693. }
  694. static int rtc_pre_save(void *opaque)
  695. {
  696. RTCState *s = opaque;
  697. rtc_update_time(s);
  698. return 0;
  699. }
  700. static int rtc_post_load(void *opaque, int version_id)
  701. {
  702. RTCState *s = opaque;
  703. if (version_id <= 2 || rtc_clock == QEMU_CLOCK_REALTIME) {
  704. rtc_set_time(s);
  705. s->offset = 0;
  706. check_update_timer(s);
  707. }
  708. s->period = rtc_periodic_clock_ticks(s);
  709. /* The periodic timer is deterministic in record/replay mode,
  710. * so there is no need to update it after loading the vmstate.
  711. * Reading RTC here would misalign record and replay.
  712. */
  713. if (replay_mode == REPLAY_MODE_NONE) {
  714. uint64_t now = qemu_clock_get_ns(rtc_clock);
  715. if (now < s->next_periodic_time ||
  716. now > (s->next_periodic_time + get_max_clock_jump())) {
  717. periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), s->period, false);
  718. }
  719. }
  720. if (version_id >= 2) {
  721. if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
  722. rtc_coalesced_timer_update(s);
  723. }
  724. }
  725. return 0;
  726. }
  727. static bool rtc_irq_reinject_on_ack_count_needed(void *opaque)
  728. {
  729. RTCState *s = (RTCState *)opaque;
  730. return s->irq_reinject_on_ack_count != 0;
  731. }
  732. static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = {
  733. .name = "mc146818rtc/irq_reinject_on_ack_count",
  734. .version_id = 1,
  735. .minimum_version_id = 1,
  736. .needed = rtc_irq_reinject_on_ack_count_needed,
  737. .fields = (VMStateField[]) {
  738. VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState),
  739. VMSTATE_END_OF_LIST()
  740. }
  741. };
  742. static const VMStateDescription vmstate_rtc = {
  743. .name = "mc146818rtc",
  744. .version_id = 3,
  745. .minimum_version_id = 1,
  746. .pre_save = rtc_pre_save,
  747. .post_load = rtc_post_load,
  748. .fields = (VMStateField[]) {
  749. VMSTATE_BUFFER(cmos_data, RTCState),
  750. VMSTATE_UINT8(cmos_index, RTCState),
  751. VMSTATE_UNUSED(7*4),
  752. VMSTATE_TIMER_PTR(periodic_timer, RTCState),
  753. VMSTATE_INT64(next_periodic_time, RTCState),
  754. VMSTATE_UNUSED(3*8),
  755. VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
  756. VMSTATE_UINT32_V(period, RTCState, 2),
  757. VMSTATE_UINT64_V(base_rtc, RTCState, 3),
  758. VMSTATE_UINT64_V(last_update, RTCState, 3),
  759. VMSTATE_INT64_V(offset, RTCState, 3),
  760. VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3),
  761. VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
  762. VMSTATE_END_OF_LIST()
  763. },
  764. .subsections = (const VMStateDescription*[]) {
  765. &vmstate_rtc_irq_reinject_on_ack_count,
  766. NULL
  767. }
  768. };
  769. /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
  770. BIOS will read it and start S3 resume at POST Entry */
  771. static void rtc_notify_suspend(Notifier *notifier, void *data)
  772. {
  773. RTCState *s = container_of(notifier, RTCState, suspend_notifier);
  774. rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
  775. }
  776. static void rtc_reset(void *opaque)
  777. {
  778. RTCState *s = opaque;
  779. s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
  780. s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
  781. check_update_timer(s);
  782. qemu_irq_lower(s->irq);
  783. if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
  784. s->irq_coalesced = 0;
  785. s->irq_reinject_on_ack_count = 0;
  786. }
  787. }
  788. static const MemoryRegionOps cmos_ops = {
  789. .read = cmos_ioport_read,
  790. .write = cmos_ioport_write,
  791. .impl = {
  792. .min_access_size = 1,
  793. .max_access_size = 1,
  794. },
  795. .endianness = DEVICE_LITTLE_ENDIAN,
  796. };
  797. static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp)
  798. {
  799. RTCState *s = MC146818_RTC(obj);
  800. rtc_update_time(s);
  801. rtc_get_time(s, current_tm);
  802. }
  803. static void rtc_realizefn(DeviceState *dev, Error **errp)
  804. {
  805. ISADevice *isadev = ISA_DEVICE(dev);
  806. RTCState *s = MC146818_RTC(dev);
  807. s->cmos_data[RTC_REG_A] = 0x26;
  808. s->cmos_data[RTC_REG_B] = 0x02;
  809. s->cmos_data[RTC_REG_C] = 0x00;
  810. s->cmos_data[RTC_REG_D] = 0x80;
  811. /* This is for historical reasons. The default base year qdev property
  812. * was set to 2000 for most machine types before the century byte was
  813. * implemented.
  814. *
  815. * This if statement means that the century byte will be always 0
  816. * (at least until 2079...) for base_year = 1980, but will be set
  817. * correctly for base_year = 2000.
  818. */
  819. if (s->base_year == 2000) {
  820. s->base_year = 0;
  821. }
  822. rtc_set_date_from_host(isadev);
  823. switch (s->lost_tick_policy) {
  824. #ifdef TARGET_I386
  825. case LOST_TICK_POLICY_SLEW:
  826. s->coalesced_timer =
  827. timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
  828. break;
  829. #endif
  830. case LOST_TICK_POLICY_DISCARD:
  831. break;
  832. default:
  833. error_setg(errp, "Invalid lost tick policy.");
  834. return;
  835. }
  836. s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
  837. s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
  838. check_update_timer(s);
  839. s->suspend_notifier.notify = rtc_notify_suspend;
  840. qemu_register_suspend_notifier(&s->suspend_notifier);
  841. memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
  842. isa_register_ioport(isadev, &s->io, RTC_ISA_BASE);
  843. /* register rtc 0x70 port for coalesced_pio */
  844. memory_region_set_flush_coalesced(&s->io);
  845. memory_region_init_io(&s->coalesced_io, OBJECT(s), &cmos_ops,
  846. s, "rtc-index", 1);
  847. memory_region_add_subregion(&s->io, 0, &s->coalesced_io);
  848. memory_region_add_coalescing(&s->coalesced_io, 0, 1);
  849. qdev_set_legacy_instance_id(dev, RTC_ISA_BASE, 3);
  850. qemu_register_reset(rtc_reset, s);
  851. object_property_add_tm(OBJECT(s), "date", rtc_get_date);
  852. qdev_init_gpio_out(dev, &s->irq, 1);
  853. QLIST_INSERT_HEAD(&rtc_devices, s, link);
  854. }
  855. ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
  856. {
  857. DeviceState *dev;
  858. ISADevice *isadev;
  859. isadev = isa_new(TYPE_MC146818_RTC);
  860. dev = DEVICE(isadev);
  861. qdev_prop_set_int32(dev, "base_year", base_year);
  862. isa_realize_and_unref(isadev, bus, &error_fatal);
  863. if (intercept_irq) {
  864. qdev_connect_gpio_out(dev, 0, intercept_irq);
  865. } else {
  866. isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ);
  867. }
  868. object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isadev),
  869. "date");
  870. return isadev;
  871. }
  872. static Property mc146818rtc_properties[] = {
  873. DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
  874. DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
  875. lost_tick_policy, LOST_TICK_POLICY_DISCARD),
  876. DEFINE_PROP_END_OF_LIST(),
  877. };
  878. static void rtc_resetdev(DeviceState *d)
  879. {
  880. RTCState *s = MC146818_RTC(d);
  881. /* Reason: VM do suspend self will set 0xfe
  882. * Reset any values other than 0xfe(Guest suspend case) */
  883. if (s->cmos_data[0x0f] != 0xfe) {
  884. s->cmos_data[0x0f] = 0x00;
  885. }
  886. }
  887. static void rtc_build_aml(ISADevice *isadev, Aml *scope)
  888. {
  889. Aml *dev;
  890. Aml *crs;
  891. /*
  892. * Reserving 8 io ports here, following what physical hardware
  893. * does, even though qemu only responds to the first two ports.
  894. */
  895. crs = aml_resource_template();
  896. aml_append(crs, aml_io(AML_DECODE16, RTC_ISA_BASE, RTC_ISA_BASE,
  897. 0x01, 0x08));
  898. aml_append(crs, aml_irq_no_flags(RTC_ISA_IRQ));
  899. dev = aml_device("RTC");
  900. aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
  901. aml_append(dev, aml_name_decl("_CRS", crs));
  902. aml_append(scope, dev);
  903. }
  904. static void rtc_class_initfn(ObjectClass *klass, void *data)
  905. {
  906. DeviceClass *dc = DEVICE_CLASS(klass);
  907. ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
  908. dc->realize = rtc_realizefn;
  909. dc->reset = rtc_resetdev;
  910. dc->vmsd = &vmstate_rtc;
  911. isa->build_aml = rtc_build_aml;
  912. device_class_set_props(dc, mc146818rtc_properties);
  913. }
  914. static const TypeInfo mc146818rtc_info = {
  915. .name = TYPE_MC146818_RTC,
  916. .parent = TYPE_ISA_DEVICE,
  917. .instance_size = sizeof(RTCState),
  918. .class_init = rtc_class_initfn,
  919. };
  920. static void mc146818rtc_register_types(void)
  921. {
  922. type_register_static(&mc146818rtc_info);
  923. }
  924. type_init(mc146818rtc_register_types)