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mps2-fpgaio.c 9.6 KB

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  1. /*
  2. * ARM MPS2 AN505 FPGAIO emulation
  3. *
  4. * Copyright (c) 2018 Linaro Limited
  5. * Written by Peter Maydell
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 or
  9. * (at your option) any later version.
  10. */
  11. /* This is a model of the "FPGA system control and I/O" block found
  12. * in the AN505 FPGA image for the MPS2 devboard.
  13. * It is documented in AN505:
  14. * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
  15. */
  16. #include "qemu/osdep.h"
  17. #include "qemu/log.h"
  18. #include "qemu/module.h"
  19. #include "qapi/error.h"
  20. #include "trace.h"
  21. #include "hw/sysbus.h"
  22. #include "migration/vmstate.h"
  23. #include "hw/registerfields.h"
  24. #include "hw/misc/mps2-fpgaio.h"
  25. #include "hw/qdev-properties.h"
  26. #include "qemu/timer.h"
  27. REG32(LED0, 0)
  28. REG32(BUTTON, 8)
  29. REG32(CLK1HZ, 0x10)
  30. REG32(CLK100HZ, 0x14)
  31. REG32(COUNTER, 0x18)
  32. REG32(PRESCALE, 0x1c)
  33. REG32(PSCNTR, 0x20)
  34. REG32(MISC, 0x4c)
  35. static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq)
  36. {
  37. return muldiv64(now - tick_offset, frq, NANOSECONDS_PER_SECOND);
  38. }
  39. static int64_t tickoff_from_counter(int64_t now, uint32_t count, int frq)
  40. {
  41. return now - muldiv64(count, NANOSECONDS_PER_SECOND, frq);
  42. }
  43. static void resync_counter(MPS2FPGAIO *s)
  44. {
  45. /*
  46. * Update s->counter and s->pscntr to their true current values
  47. * by calculating how many times PSCNTR has ticked since the
  48. * last time we did a resync.
  49. */
  50. int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  51. int64_t elapsed = now - s->pscntr_sync_ticks;
  52. /*
  53. * Round elapsed down to a whole number of PSCNTR ticks, so we don't
  54. * lose time if we do multiple resyncs in a single tick.
  55. */
  56. uint64_t ticks = muldiv64(elapsed, s->prescale_clk, NANOSECONDS_PER_SECOND);
  57. /*
  58. * Work out what PSCNTR and COUNTER have moved to. We assume that
  59. * PSCNTR reloads from PRESCALE one tick-period after it hits zero,
  60. * and that COUNTER increments at the same moment.
  61. */
  62. if (ticks == 0) {
  63. /* We haven't ticked since the last time we were asked */
  64. return;
  65. } else if (ticks < s->pscntr) {
  66. /* We haven't yet reached zero, just reduce the PSCNTR */
  67. s->pscntr -= ticks;
  68. } else {
  69. if (s->prescale == 0) {
  70. /*
  71. * If the reload value is zero then the PSCNTR will stick
  72. * at zero once it reaches it, and so we will increment
  73. * COUNTER every tick after that.
  74. */
  75. s->counter += ticks - s->pscntr;
  76. s->pscntr = 0;
  77. } else {
  78. /*
  79. * This is the complicated bit. This ASCII art diagram gives an
  80. * example with PRESCALE==5 PSCNTR==7:
  81. *
  82. * ticks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
  83. * PSCNTR 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5
  84. * cinc 1 2
  85. * y 0 1 2 3 4 5 6 7 8 9 10 11 12
  86. * x 0 1 2 3 4 5 0 1 2 3 4 5 0
  87. *
  88. * where x = y % (s->prescale + 1)
  89. * and so PSCNTR = s->prescale - x
  90. * and COUNTER is incremented by y / (s->prescale + 1)
  91. *
  92. * The case where PSCNTR < PRESCALE works out the same,
  93. * though we must be careful to calculate y as 64-bit unsigned
  94. * for all parts of the expression.
  95. * y < 0 is not possible because that implies ticks < s->pscntr.
  96. */
  97. uint64_t y = ticks - s->pscntr + s->prescale;
  98. s->pscntr = s->prescale - (y % (s->prescale + 1));
  99. s->counter += y / (s->prescale + 1);
  100. }
  101. }
  102. /*
  103. * Only advance the sync time to the timestamp of the last PSCNTR tick,
  104. * not all the way to 'now', so we don't lose time if we do multiple
  105. * resyncs in a single tick.
  106. */
  107. s->pscntr_sync_ticks += muldiv64(ticks, NANOSECONDS_PER_SECOND,
  108. s->prescale_clk);
  109. }
  110. static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size)
  111. {
  112. MPS2FPGAIO *s = MPS2_FPGAIO(opaque);
  113. uint64_t r;
  114. int64_t now;
  115. switch (offset) {
  116. case A_LED0:
  117. r = s->led0;
  118. break;
  119. case A_BUTTON:
  120. /* User-pressable board buttons. We don't model that, so just return
  121. * zeroes.
  122. */
  123. r = 0;
  124. break;
  125. case A_PRESCALE:
  126. r = s->prescale;
  127. break;
  128. case A_MISC:
  129. r = s->misc;
  130. break;
  131. case A_CLK1HZ:
  132. now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  133. r = counter_from_tickoff(now, s->clk1hz_tick_offset, 1);
  134. break;
  135. case A_CLK100HZ:
  136. now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  137. r = counter_from_tickoff(now, s->clk100hz_tick_offset, 100);
  138. break;
  139. case A_COUNTER:
  140. resync_counter(s);
  141. r = s->counter;
  142. break;
  143. case A_PSCNTR:
  144. resync_counter(s);
  145. r = s->pscntr;
  146. break;
  147. default:
  148. qemu_log_mask(LOG_GUEST_ERROR,
  149. "MPS2 FPGAIO read: bad offset %x\n", (int) offset);
  150. r = 0;
  151. break;
  152. }
  153. trace_mps2_fpgaio_read(offset, r, size);
  154. return r;
  155. }
  156. static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value,
  157. unsigned size)
  158. {
  159. MPS2FPGAIO *s = MPS2_FPGAIO(opaque);
  160. int64_t now;
  161. trace_mps2_fpgaio_write(offset, value, size);
  162. switch (offset) {
  163. case A_LED0:
  164. /* LED bits [1:0] control board LEDs. We don't currently have
  165. * a mechanism for displaying this graphically, so use a trace event.
  166. */
  167. trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.',
  168. value & 0x01 ? '*' : '.');
  169. s->led0 = value & 0x3;
  170. break;
  171. case A_PRESCALE:
  172. resync_counter(s);
  173. s->prescale = value;
  174. break;
  175. case A_MISC:
  176. /* These are control bits for some of the other devices on the
  177. * board (SPI, CLCD, etc). We don't implement that yet, so just
  178. * make the bits read as written.
  179. */
  180. qemu_log_mask(LOG_UNIMP,
  181. "MPS2 FPGAIO: MISC control bits unimplemented\n");
  182. s->misc = value;
  183. break;
  184. case A_CLK1HZ:
  185. now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  186. s->clk1hz_tick_offset = tickoff_from_counter(now, value, 1);
  187. break;
  188. case A_CLK100HZ:
  189. now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  190. s->clk100hz_tick_offset = tickoff_from_counter(now, value, 100);
  191. break;
  192. case A_COUNTER:
  193. resync_counter(s);
  194. s->counter = value;
  195. break;
  196. case A_PSCNTR:
  197. resync_counter(s);
  198. s->pscntr = value;
  199. break;
  200. default:
  201. qemu_log_mask(LOG_GUEST_ERROR,
  202. "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset);
  203. break;
  204. }
  205. }
  206. static const MemoryRegionOps mps2_fpgaio_ops = {
  207. .read = mps2_fpgaio_read,
  208. .write = mps2_fpgaio_write,
  209. .endianness = DEVICE_LITTLE_ENDIAN,
  210. };
  211. static void mps2_fpgaio_reset(DeviceState *dev)
  212. {
  213. MPS2FPGAIO *s = MPS2_FPGAIO(dev);
  214. int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  215. trace_mps2_fpgaio_reset();
  216. s->led0 = 0;
  217. s->prescale = 0;
  218. s->misc = 0;
  219. s->clk1hz_tick_offset = tickoff_from_counter(now, 0, 1);
  220. s->clk100hz_tick_offset = tickoff_from_counter(now, 0, 100);
  221. s->counter = 0;
  222. s->pscntr = 0;
  223. s->pscntr_sync_ticks = now;
  224. }
  225. static void mps2_fpgaio_init(Object *obj)
  226. {
  227. SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  228. MPS2FPGAIO *s = MPS2_FPGAIO(obj);
  229. memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s,
  230. "mps2-fpgaio", 0x1000);
  231. sysbus_init_mmio(sbd, &s->iomem);
  232. }
  233. static bool mps2_fpgaio_counters_needed(void *opaque)
  234. {
  235. /* Currently vmstate.c insists all subsections have a 'needed' function */
  236. return true;
  237. }
  238. static const VMStateDescription mps2_fpgaio_counters_vmstate = {
  239. .name = "mps2-fpgaio/counters",
  240. .version_id = 2,
  241. .minimum_version_id = 2,
  242. .needed = mps2_fpgaio_counters_needed,
  243. .fields = (VMStateField[]) {
  244. VMSTATE_INT64(clk1hz_tick_offset, MPS2FPGAIO),
  245. VMSTATE_INT64(clk100hz_tick_offset, MPS2FPGAIO),
  246. VMSTATE_UINT32(counter, MPS2FPGAIO),
  247. VMSTATE_UINT32(pscntr, MPS2FPGAIO),
  248. VMSTATE_INT64(pscntr_sync_ticks, MPS2FPGAIO),
  249. VMSTATE_END_OF_LIST()
  250. }
  251. };
  252. static const VMStateDescription mps2_fpgaio_vmstate = {
  253. .name = "mps2-fpgaio",
  254. .version_id = 1,
  255. .minimum_version_id = 1,
  256. .fields = (VMStateField[]) {
  257. VMSTATE_UINT32(led0, MPS2FPGAIO),
  258. VMSTATE_UINT32(prescale, MPS2FPGAIO),
  259. VMSTATE_UINT32(misc, MPS2FPGAIO),
  260. VMSTATE_END_OF_LIST()
  261. },
  262. .subsections = (const VMStateDescription*[]) {
  263. &mps2_fpgaio_counters_vmstate,
  264. NULL
  265. }
  266. };
  267. static Property mps2_fpgaio_properties[] = {
  268. /* Frequency of the prescale counter */
  269. DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000),
  270. DEFINE_PROP_END_OF_LIST(),
  271. };
  272. static void mps2_fpgaio_class_init(ObjectClass *klass, void *data)
  273. {
  274. DeviceClass *dc = DEVICE_CLASS(klass);
  275. dc->vmsd = &mps2_fpgaio_vmstate;
  276. dc->reset = mps2_fpgaio_reset;
  277. device_class_set_props(dc, mps2_fpgaio_properties);
  278. }
  279. static const TypeInfo mps2_fpgaio_info = {
  280. .name = TYPE_MPS2_FPGAIO,
  281. .parent = TYPE_SYS_BUS_DEVICE,
  282. .instance_size = sizeof(MPS2FPGAIO),
  283. .instance_init = mps2_fpgaio_init,
  284. .class_init = mps2_fpgaio_class_init,
  285. };
  286. static void mps2_fpgaio_register_types(void)
  287. {
  288. type_register_static(&mps2_fpgaio_info);
  289. }
  290. type_init(mps2_fpgaio_register_types);