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macio.c 17 KB

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  1. /*
  2. * PowerMac MacIO device emulation
  3. *
  4. * Copyright (c) 2005-2007 Fabrice Bellard
  5. * Copyright (c) 2007 Jocelyn Mayer
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy
  8. * of this software and associated documentation files (the "Software"), to deal
  9. * in the Software without restriction, including without limitation the rights
  10. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11. * copies of the Software, and to permit persons to whom the Software is
  12. * furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23. * THE SOFTWARE.
  24. */
  25. #include "qemu/osdep.h"
  26. #include "qapi/error.h"
  27. #include "qemu/module.h"
  28. #include "hw/ppc/mac.h"
  29. #include "hw/misc/macio/cuda.h"
  30. #include "hw/pci/pci.h"
  31. #include "hw/ppc/mac_dbdma.h"
  32. #include "hw/qdev-properties.h"
  33. #include "migration/vmstate.h"
  34. #include "hw/char/escc.h"
  35. #include "hw/misc/macio/macio.h"
  36. #include "hw/intc/heathrow_pic.h"
  37. #include "sysemu/sysemu.h"
  38. #include "trace.h"
  39. /* Note: this code is strongly inspirated from the corresponding code
  40. * in PearPC */
  41. /*
  42. * The mac-io has two interfaces to the ESCC. One is called "escc-legacy",
  43. * while the other one is the normal, current ESCC interface.
  44. *
  45. * The magic below creates memory aliases to spawn the escc-legacy device
  46. * purely by rerouting the respective registers to our escc region. This
  47. * works because the only difference between the two memory regions is the
  48. * register layout, not their semantics.
  49. *
  50. * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
  51. */
  52. static void macio_escc_legacy_setup(MacIOState *s)
  53. {
  54. ESCCState *escc = ESCC(&s->escc);
  55. SysBusDevice *sbd = SYS_BUS_DEVICE(escc);
  56. MemoryRegion *escc_legacy = g_new(MemoryRegion, 1);
  57. MemoryRegion *bar = &s->bar;
  58. int i;
  59. static const int maps[] = {
  60. 0x00, 0x00, /* Command B */
  61. 0x02, 0x20, /* Command A */
  62. 0x04, 0x10, /* Data B */
  63. 0x06, 0x30, /* Data A */
  64. 0x08, 0x40, /* Enhancement B */
  65. 0x0A, 0x50, /* Enhancement A */
  66. 0x80, 0x80, /* Recovery count */
  67. 0x90, 0x90, /* Start A */
  68. 0xa0, 0xa0, /* Start B */
  69. 0xb0, 0xb0, /* Detect AB */
  70. };
  71. memory_region_init(escc_legacy, OBJECT(s), "escc-legacy", 256);
  72. for (i = 0; i < ARRAY_SIZE(maps); i += 2) {
  73. MemoryRegion *port = g_new(MemoryRegion, 1);
  74. memory_region_init_alias(port, OBJECT(s), "escc-legacy-port",
  75. sysbus_mmio_get_region(sbd, 0),
  76. maps[i + 1], 0x2);
  77. memory_region_add_subregion(escc_legacy, maps[i], port);
  78. }
  79. memory_region_add_subregion(bar, 0x12000, escc_legacy);
  80. }
  81. static void macio_bar_setup(MacIOState *s)
  82. {
  83. ESCCState *escc = ESCC(&s->escc);
  84. SysBusDevice *sbd = SYS_BUS_DEVICE(escc);
  85. MemoryRegion *bar = &s->bar;
  86. memory_region_add_subregion(bar, 0x13000, sysbus_mmio_get_region(sbd, 0));
  87. macio_escc_legacy_setup(s);
  88. }
  89. static void macio_common_realize(PCIDevice *d, Error **errp)
  90. {
  91. MacIOState *s = MACIO(d);
  92. SysBusDevice *sysbus_dev;
  93. if (!qdev_realize(DEVICE(&s->dbdma), BUS(&s->macio_bus), errp)) {
  94. return;
  95. }
  96. sysbus_dev = SYS_BUS_DEVICE(&s->dbdma);
  97. memory_region_add_subregion(&s->bar, 0x08000,
  98. sysbus_mmio_get_region(sysbus_dev, 0));
  99. qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0);
  100. qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK);
  101. qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4);
  102. qdev_prop_set_chr(DEVICE(&s->escc), "chrA", serial_hd(0));
  103. qdev_prop_set_chr(DEVICE(&s->escc), "chrB", serial_hd(1));
  104. qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial);
  105. qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial);
  106. if (!qdev_realize(DEVICE(&s->escc), BUS(&s->macio_bus), errp)) {
  107. return;
  108. }
  109. macio_bar_setup(s);
  110. pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
  111. }
  112. static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide,
  113. qemu_irq irq0, qemu_irq irq1, int dmaid,
  114. Error **errp)
  115. {
  116. SysBusDevice *sysbus_dev;
  117. sysbus_dev = SYS_BUS_DEVICE(ide);
  118. sysbus_connect_irq(sysbus_dev, 0, irq0);
  119. sysbus_connect_irq(sysbus_dev, 1, irq1);
  120. qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid);
  121. object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma),
  122. &error_abort);
  123. macio_ide_register_dma(ide);
  124. qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp);
  125. }
  126. static void macio_oldworld_realize(PCIDevice *d, Error **errp)
  127. {
  128. MacIOState *s = MACIO(d);
  129. OldWorldMacIOState *os = OLDWORLD_MACIO(d);
  130. DeviceState *pic_dev = DEVICE(os->pic);
  131. Error *err = NULL;
  132. SysBusDevice *sysbus_dev;
  133. macio_common_realize(d, &err);
  134. if (err) {
  135. error_propagate(errp, err);
  136. return;
  137. }
  138. qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
  139. s->frequency);
  140. if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) {
  141. return;
  142. }
  143. sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
  144. memory_region_add_subregion(&s->bar, 0x16000,
  145. sysbus_mmio_get_region(sysbus_dev, 0));
  146. sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
  147. OLDWORLD_CUDA_IRQ));
  148. sysbus_dev = SYS_BUS_DEVICE(&s->escc);
  149. sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
  150. OLDWORLD_ESCCB_IRQ));
  151. sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
  152. OLDWORLD_ESCCA_IRQ));
  153. if (!qdev_realize(DEVICE(&os->nvram), BUS(&s->macio_bus), errp)) {
  154. return;
  155. }
  156. sysbus_dev = SYS_BUS_DEVICE(&os->nvram);
  157. memory_region_add_subregion(&s->bar, 0x60000,
  158. sysbus_mmio_get_region(sysbus_dev, 0));
  159. pmac_format_nvram_partition(&os->nvram, os->nvram.size);
  160. /* Heathrow PIC */
  161. sysbus_dev = SYS_BUS_DEVICE(os->pic);
  162. memory_region_add_subregion(&s->bar, 0x0,
  163. sysbus_mmio_get_region(sysbus_dev, 0));
  164. /* IDE buses */
  165. macio_realize_ide(s, &os->ide[0],
  166. qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ),
  167. qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ),
  168. 0x16, &err);
  169. if (err) {
  170. error_propagate(errp, err);
  171. return;
  172. }
  173. macio_realize_ide(s, &os->ide[1],
  174. qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ),
  175. qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ),
  176. 0x1a, &err);
  177. if (err) {
  178. error_propagate(errp, err);
  179. return;
  180. }
  181. }
  182. static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, int index)
  183. {
  184. gchar *name = g_strdup_printf("ide[%i]", index);
  185. uint32_t addr = 0x1f000 + ((index + 1) * 0x1000);
  186. object_initialize_child(OBJECT(s), name, ide, TYPE_MACIO_IDE);
  187. qdev_prop_set_uint32(DEVICE(ide), "addr", addr);
  188. memory_region_add_subregion(&s->bar, addr, &ide->mem);
  189. g_free(name);
  190. }
  191. static void macio_oldworld_init(Object *obj)
  192. {
  193. MacIOState *s = MACIO(obj);
  194. OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
  195. DeviceState *dev;
  196. int i;
  197. object_property_add_link(obj, "pic", TYPE_HEATHROW,
  198. (Object **) &os->pic,
  199. qdev_prop_allow_set_link_before_realize,
  200. 0);
  201. object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA);
  202. object_initialize_child(OBJECT(s), "nvram", &os->nvram, TYPE_MACIO_NVRAM);
  203. dev = DEVICE(&os->nvram);
  204. qdev_prop_set_uint32(dev, "size", 0x2000);
  205. qdev_prop_set_uint32(dev, "it_shift", 4);
  206. for (i = 0; i < 2; i++) {
  207. macio_init_ide(s, &os->ide[i], i);
  208. }
  209. }
  210. static void timer_write(void *opaque, hwaddr addr, uint64_t value,
  211. unsigned size)
  212. {
  213. trace_macio_timer_write(addr, size, value);
  214. }
  215. static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
  216. {
  217. uint32_t value = 0;
  218. uint64_t systime = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  219. uint64_t kltime;
  220. kltime = muldiv64(systime, 4194300, NANOSECONDS_PER_SECOND * 4);
  221. kltime = muldiv64(kltime, 18432000, 1048575);
  222. switch (addr) {
  223. case 0x38:
  224. value = kltime;
  225. break;
  226. case 0x3c:
  227. value = kltime >> 32;
  228. break;
  229. }
  230. trace_macio_timer_read(addr, size, value);
  231. return value;
  232. }
  233. static const MemoryRegionOps timer_ops = {
  234. .read = timer_read,
  235. .write = timer_write,
  236. .endianness = DEVICE_LITTLE_ENDIAN,
  237. };
  238. static void macio_newworld_realize(PCIDevice *d, Error **errp)
  239. {
  240. MacIOState *s = MACIO(d);
  241. NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
  242. DeviceState *pic_dev = DEVICE(ns->pic);
  243. Error *err = NULL;
  244. SysBusDevice *sysbus_dev;
  245. MemoryRegion *timer_memory = NULL;
  246. macio_common_realize(d, &err);
  247. if (err) {
  248. error_propagate(errp, err);
  249. return;
  250. }
  251. sysbus_dev = SYS_BUS_DEVICE(&s->escc);
  252. sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
  253. NEWWORLD_ESCCB_IRQ));
  254. sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
  255. NEWWORLD_ESCCA_IRQ));
  256. /* OpenPIC */
  257. sysbus_dev = SYS_BUS_DEVICE(ns->pic);
  258. memory_region_add_subregion(&s->bar, 0x40000,
  259. sysbus_mmio_get_region(sysbus_dev, 0));
  260. /* IDE buses */
  261. macio_realize_ide(s, &ns->ide[0],
  262. qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_IRQ),
  263. qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_DMA_IRQ),
  264. 0x16, &err);
  265. if (err) {
  266. error_propagate(errp, err);
  267. return;
  268. }
  269. macio_realize_ide(s, &ns->ide[1],
  270. qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_IRQ),
  271. qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_DMA_IRQ),
  272. 0x1a, &err);
  273. if (err) {
  274. error_propagate(errp, err);
  275. return;
  276. }
  277. /* Timer */
  278. timer_memory = g_new(MemoryRegion, 1);
  279. memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer",
  280. 0x1000);
  281. memory_region_add_subregion(&s->bar, 0x15000, timer_memory);
  282. if (ns->has_pmu) {
  283. /* GPIOs */
  284. sysbus_dev = SYS_BUS_DEVICE(&ns->gpio);
  285. object_property_set_link(OBJECT(&ns->gpio), "pic", OBJECT(pic_dev),
  286. &error_abort);
  287. memory_region_add_subregion(&s->bar, 0x50,
  288. sysbus_mmio_get_region(sysbus_dev, 0));
  289. if (!qdev_realize(DEVICE(&ns->gpio), BUS(&s->macio_bus), errp)) {
  290. return;
  291. }
  292. /* PMU */
  293. object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU);
  294. object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sysbus_dev),
  295. &error_abort);
  296. qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb);
  297. if (!qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), errp)) {
  298. return;
  299. }
  300. sysbus_dev = SYS_BUS_DEVICE(&s->pmu);
  301. sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
  302. NEWWORLD_PMU_IRQ));
  303. memory_region_add_subregion(&s->bar, 0x16000,
  304. sysbus_mmio_get_region(sysbus_dev, 0));
  305. } else {
  306. object_unparent(OBJECT(&ns->gpio));
  307. /* CUDA */
  308. object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA);
  309. qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
  310. s->frequency);
  311. if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) {
  312. return;
  313. }
  314. sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
  315. sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
  316. NEWWORLD_CUDA_IRQ));
  317. memory_region_add_subregion(&s->bar, 0x16000,
  318. sysbus_mmio_get_region(sysbus_dev, 0));
  319. }
  320. }
  321. static void macio_newworld_init(Object *obj)
  322. {
  323. MacIOState *s = MACIO(obj);
  324. NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
  325. int i;
  326. object_property_add_link(obj, "pic", TYPE_OPENPIC,
  327. (Object **) &ns->pic,
  328. qdev_prop_allow_set_link_before_realize,
  329. 0);
  330. object_initialize_child(OBJECT(s), "gpio", &ns->gpio, TYPE_MACIO_GPIO);
  331. for (i = 0; i < 2; i++) {
  332. macio_init_ide(s, &ns->ide[i], i);
  333. }
  334. }
  335. static void macio_instance_init(Object *obj)
  336. {
  337. MacIOState *s = MACIO(obj);
  338. memory_region_init(&s->bar, obj, "macio", 0x80000);
  339. qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
  340. DEVICE(obj), "macio.0");
  341. object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA);
  342. object_initialize_child(OBJECT(s), "escc", &s->escc, TYPE_ESCC);
  343. }
  344. static const VMStateDescription vmstate_macio_oldworld = {
  345. .name = "macio-oldworld",
  346. .version_id = 0,
  347. .minimum_version_id = 0,
  348. .fields = (VMStateField[]) {
  349. VMSTATE_PCI_DEVICE(parent_obj.parent, OldWorldMacIOState),
  350. VMSTATE_END_OF_LIST()
  351. }
  352. };
  353. static void macio_oldworld_class_init(ObjectClass *oc, void *data)
  354. {
  355. PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
  356. DeviceClass *dc = DEVICE_CLASS(oc);
  357. pdc->realize = macio_oldworld_realize;
  358. pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201;
  359. dc->vmsd = &vmstate_macio_oldworld;
  360. }
  361. static const VMStateDescription vmstate_macio_newworld = {
  362. .name = "macio-newworld",
  363. .version_id = 0,
  364. .minimum_version_id = 0,
  365. .fields = (VMStateField[]) {
  366. VMSTATE_PCI_DEVICE(parent_obj.parent, NewWorldMacIOState),
  367. VMSTATE_END_OF_LIST()
  368. }
  369. };
  370. static Property macio_newworld_properties[] = {
  371. DEFINE_PROP_BOOL("has-pmu", NewWorldMacIOState, has_pmu, false),
  372. DEFINE_PROP_BOOL("has-adb", NewWorldMacIOState, has_adb, false),
  373. DEFINE_PROP_END_OF_LIST()
  374. };
  375. static void macio_newworld_class_init(ObjectClass *oc, void *data)
  376. {
  377. PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
  378. DeviceClass *dc = DEVICE_CLASS(oc);
  379. pdc->realize = macio_newworld_realize;
  380. pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL;
  381. dc->vmsd = &vmstate_macio_newworld;
  382. device_class_set_props(dc, macio_newworld_properties);
  383. }
  384. static Property macio_properties[] = {
  385. DEFINE_PROP_UINT64("frequency", MacIOState, frequency, 0),
  386. DEFINE_PROP_END_OF_LIST()
  387. };
  388. static void macio_class_init(ObjectClass *klass, void *data)
  389. {
  390. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  391. DeviceClass *dc = DEVICE_CLASS(klass);
  392. k->vendor_id = PCI_VENDOR_ID_APPLE;
  393. k->class_id = PCI_CLASS_OTHERS << 8;
  394. device_class_set_props(dc, macio_properties);
  395. set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
  396. /* Reason: Uses serial_hds in macio_instance_init */
  397. dc->user_creatable = false;
  398. }
  399. static const TypeInfo macio_bus_info = {
  400. .name = TYPE_MACIO_BUS,
  401. .parent = TYPE_SYSTEM_BUS,
  402. .instance_size = sizeof(MacIOBusState),
  403. };
  404. static const TypeInfo macio_oldworld_type_info = {
  405. .name = TYPE_OLDWORLD_MACIO,
  406. .parent = TYPE_MACIO,
  407. .instance_size = sizeof(OldWorldMacIOState),
  408. .instance_init = macio_oldworld_init,
  409. .class_init = macio_oldworld_class_init,
  410. };
  411. static const TypeInfo macio_newworld_type_info = {
  412. .name = TYPE_NEWWORLD_MACIO,
  413. .parent = TYPE_MACIO,
  414. .instance_size = sizeof(NewWorldMacIOState),
  415. .instance_init = macio_newworld_init,
  416. .class_init = macio_newworld_class_init,
  417. };
  418. static const TypeInfo macio_type_info = {
  419. .name = TYPE_MACIO,
  420. .parent = TYPE_PCI_DEVICE,
  421. .instance_size = sizeof(MacIOState),
  422. .instance_init = macio_instance_init,
  423. .abstract = true,
  424. .class_init = macio_class_init,
  425. .interfaces = (InterfaceInfo[]) {
  426. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  427. { },
  428. },
  429. };
  430. static void macio_register_types(void)
  431. {
  432. type_register_static(&macio_bus_info);
  433. type_register_static(&macio_type_info);
  434. type_register_static(&macio_oldworld_type_info);
  435. type_register_static(&macio_newworld_type_info);
  436. }
  437. type_init(macio_register_types)