sifive_plic.h 2.2 KB

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  1. /*
  2. * SiFive PLIC (Platform Level Interrupt Controller) interface
  3. *
  4. * Copyright (c) 2017 SiFive, Inc.
  5. *
  6. * This provides a RISC-V PLIC device
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms and conditions of the GNU General Public License,
  10. * version 2 or later, as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program. If not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #ifndef HW_SIFIVE_PLIC_H
  21. #define HW_SIFIVE_PLIC_H
  22. #include "hw/sysbus.h"
  23. #include "qom/object.h"
  24. #define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
  25. typedef struct SiFivePLICState SiFivePLICState;
  26. DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
  27. TYPE_SIFIVE_PLIC)
  28. typedef enum PLICMode {
  29. PLICMode_U,
  30. PLICMode_S,
  31. PLICMode_H,
  32. PLICMode_M
  33. } PLICMode;
  34. typedef struct PLICAddr {
  35. uint32_t addrid;
  36. uint32_t hartid;
  37. PLICMode mode;
  38. } PLICAddr;
  39. struct SiFivePLICState {
  40. /*< private >*/
  41. SysBusDevice parent_obj;
  42. /*< public >*/
  43. MemoryRegion mmio;
  44. uint32_t num_addrs;
  45. uint32_t num_harts;
  46. uint32_t bitfield_words;
  47. PLICAddr *addr_config;
  48. uint32_t *source_priority;
  49. uint32_t *target_priority;
  50. uint32_t *pending;
  51. uint32_t *claimed;
  52. uint32_t *enable;
  53. /* config */
  54. char *hart_config;
  55. uint32_t hartid_base;
  56. uint32_t num_sources;
  57. uint32_t num_priorities;
  58. uint32_t priority_base;
  59. uint32_t pending_base;
  60. uint32_t enable_base;
  61. uint32_t enable_stride;
  62. uint32_t context_base;
  63. uint32_t context_stride;
  64. uint32_t aperture_size;
  65. };
  66. DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
  67. uint32_t hartid_base, uint32_t num_sources,
  68. uint32_t num_priorities, uint32_t priority_base,
  69. uint32_t pending_base, uint32_t enable_base,
  70. uint32_t enable_stride, uint32_t context_base,
  71. uint32_t context_stride, uint32_t aperture_size);
  72. #endif