rx_icu.c 11 KB

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  1. /*
  2. * RX Interrupt Control Unit
  3. *
  4. * Warning: Only ICUa is supported.
  5. *
  6. * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
  7. * (Rev.1.40 R01UH0033EJ0140)
  8. *
  9. * Copyright (c) 2019 Yoshinori Sato
  10. *
  11. * SPDX-License-Identifier: GPL-2.0-or-later
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms and conditions of the GNU General Public License,
  15. * version 2 or later, as published by the Free Software Foundation.
  16. *
  17. * This program is distributed in the hope it will be useful, but WITHOUT
  18. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  20. * more details.
  21. *
  22. * You should have received a copy of the GNU General Public License along with
  23. * this program. If not, see <http://www.gnu.org/licenses/>.
  24. */
  25. #include "qemu/osdep.h"
  26. #include "qemu/log.h"
  27. #include "qemu/error-report.h"
  28. #include "hw/irq.h"
  29. #include "hw/registerfields.h"
  30. #include "hw/qdev-properties.h"
  31. #include "hw/intc/rx_icu.h"
  32. #include "migration/vmstate.h"
  33. REG8(IR, 0)
  34. FIELD(IR, IR, 0, 1)
  35. REG8(DTCER, 0x100)
  36. FIELD(DTCER, DTCE, 0, 1)
  37. REG8(IER, 0x200)
  38. REG8(SWINTR, 0x2e0)
  39. FIELD(SWINTR, SWINT, 0, 1)
  40. REG16(FIR, 0x2f0)
  41. FIELD(FIR, FVCT, 0, 8)
  42. FIELD(FIR, FIEN, 15, 1)
  43. REG8(IPR, 0x300)
  44. FIELD(IPR, IPR, 0, 4)
  45. REG8(DMRSR, 0x400)
  46. REG8(IRQCR, 0x500)
  47. FIELD(IRQCR, IRQMD, 2, 2)
  48. REG8(NMISR, 0x580)
  49. FIELD(NMISR, NMIST, 0, 1)
  50. FIELD(NMISR, LVDST, 1, 1)
  51. FIELD(NMISR, OSTST, 2, 1)
  52. REG8(NMIER, 0x581)
  53. FIELD(NMIER, NMIEN, 0, 1)
  54. FIELD(NMIER, LVDEN, 1, 1)
  55. FIELD(NMIER, OSTEN, 2, 1)
  56. REG8(NMICLR, 0x582)
  57. FIELD(NMICLR, NMICLR, 0, 1)
  58. FIELD(NMICLR, OSTCLR, 2, 1)
  59. REG8(NMICR, 0x583)
  60. FIELD(NMICR, NMIMD, 3, 1)
  61. static void set_irq(RXICUState *icu, int n_IRQ, int req)
  62. {
  63. if ((icu->fir & R_FIR_FIEN_MASK) &&
  64. (icu->fir & R_FIR_FVCT_MASK) == n_IRQ) {
  65. qemu_set_irq(icu->_fir, req);
  66. } else {
  67. qemu_set_irq(icu->_irq, req);
  68. }
  69. }
  70. static uint16_t rxicu_level(RXICUState *icu, unsigned n)
  71. {
  72. return (icu->ipr[icu->map[n]] << 8) | n;
  73. }
  74. static void rxicu_request(RXICUState *icu, int n_IRQ)
  75. {
  76. int enable;
  77. enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7));
  78. if (n_IRQ > 0 && enable != 0 && qatomic_read(&icu->req_irq) < 0) {
  79. qatomic_set(&icu->req_irq, n_IRQ);
  80. set_irq(icu, n_IRQ, rxicu_level(icu, n_IRQ));
  81. }
  82. }
  83. static void rxicu_set_irq(void *opaque, int n_IRQ, int level)
  84. {
  85. RXICUState *icu = opaque;
  86. struct IRQSource *src;
  87. int issue;
  88. if (n_IRQ >= NR_IRQS) {
  89. error_report("%s: IRQ %d out of range", __func__, n_IRQ);
  90. return;
  91. }
  92. src = &icu->src[n_IRQ];
  93. level = (level != 0);
  94. switch (src->sense) {
  95. case TRG_LEVEL:
  96. /* level-sensitive irq */
  97. issue = level;
  98. src->level = level;
  99. break;
  100. case TRG_NEDGE:
  101. issue = (level == 0 && src->level == 1);
  102. src->level = level;
  103. break;
  104. case TRG_PEDGE:
  105. issue = (level == 1 && src->level == 0);
  106. src->level = level;
  107. break;
  108. case TRG_BEDGE:
  109. issue = ((level ^ src->level) & 1);
  110. src->level = level;
  111. break;
  112. default:
  113. g_assert_not_reached();
  114. }
  115. if (issue == 0 && src->sense == TRG_LEVEL) {
  116. icu->ir[n_IRQ] = 0;
  117. if (qatomic_read(&icu->req_irq) == n_IRQ) {
  118. /* clear request */
  119. set_irq(icu, n_IRQ, 0);
  120. qatomic_set(&icu->req_irq, -1);
  121. }
  122. return;
  123. }
  124. if (issue) {
  125. icu->ir[n_IRQ] = 1;
  126. rxicu_request(icu, n_IRQ);
  127. }
  128. }
  129. static void rxicu_ack_irq(void *opaque, int no, int level)
  130. {
  131. RXICUState *icu = opaque;
  132. int i;
  133. int n_IRQ;
  134. int max_pri;
  135. n_IRQ = qatomic_read(&icu->req_irq);
  136. if (n_IRQ < 0) {
  137. return;
  138. }
  139. qatomic_set(&icu->req_irq, -1);
  140. if (icu->src[n_IRQ].sense != TRG_LEVEL) {
  141. icu->ir[n_IRQ] = 0;
  142. }
  143. max_pri = 0;
  144. n_IRQ = -1;
  145. for (i = 0; i < NR_IRQS; i++) {
  146. if (icu->ir[i]) {
  147. if (max_pri < icu->ipr[icu->map[i]]) {
  148. n_IRQ = i;
  149. max_pri = icu->ipr[icu->map[i]];
  150. }
  151. }
  152. }
  153. if (n_IRQ >= 0) {
  154. rxicu_request(icu, n_IRQ);
  155. }
  156. }
  157. static uint64_t icu_read(void *opaque, hwaddr addr, unsigned size)
  158. {
  159. RXICUState *icu = opaque;
  160. int reg = addr & 0xff;
  161. if ((addr != A_FIR && size != 1) ||
  162. (addr == A_FIR && size != 2)) {
  163. qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid read size 0x%"
  164. HWADDR_PRIX "\n",
  165. addr);
  166. return UINT64_MAX;
  167. }
  168. switch (addr) {
  169. case A_IR ... A_IR + 0xff:
  170. return icu->ir[reg] & R_IR_IR_MASK;
  171. case A_DTCER ... A_DTCER + 0xff:
  172. return icu->dtcer[reg] & R_DTCER_DTCE_MASK;
  173. case A_IER ... A_IER + 0x1f:
  174. return icu->ier[reg];
  175. case A_SWINTR:
  176. return 0;
  177. case A_FIR:
  178. return icu->fir & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK);
  179. case A_IPR ... A_IPR + 0x8f:
  180. return icu->ipr[reg] & R_IPR_IPR_MASK;
  181. case A_DMRSR:
  182. case A_DMRSR + 4:
  183. case A_DMRSR + 8:
  184. case A_DMRSR + 12:
  185. return icu->dmasr[reg >> 2];
  186. case A_IRQCR ... A_IRQCR + 0x1f:
  187. return icu->src[64 + reg].sense << R_IRQCR_IRQMD_SHIFT;
  188. case A_NMISR:
  189. case A_NMICLR:
  190. return 0;
  191. case A_NMIER:
  192. return icu->nmier;
  193. case A_NMICR:
  194. return icu->nmicr;
  195. default:
  196. qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " "
  197. "not implemented.\n",
  198. addr);
  199. break;
  200. }
  201. return UINT64_MAX;
  202. }
  203. static void icu_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
  204. {
  205. RXICUState *icu = opaque;
  206. int reg = addr & 0xff;
  207. if ((addr != A_FIR && size != 1) ||
  208. (addr == A_FIR && size != 2)) {
  209. qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid write size at "
  210. "0x%" HWADDR_PRIX "\n",
  211. addr);
  212. return;
  213. }
  214. switch (addr) {
  215. case A_IR ... A_IR + 0xff:
  216. if (icu->src[reg].sense != TRG_LEVEL && val == 0) {
  217. icu->ir[reg] = 0;
  218. }
  219. break;
  220. case A_DTCER ... A_DTCER + 0xff:
  221. icu->dtcer[reg] = val & R_DTCER_DTCE_MASK;
  222. qemu_log_mask(LOG_UNIMP, "rx_icu: DTC not implemented\n");
  223. break;
  224. case A_IER ... A_IER + 0x1f:
  225. icu->ier[reg] = val;
  226. break;
  227. case A_SWINTR:
  228. if (val & R_SWINTR_SWINT_MASK) {
  229. qemu_irq_pulse(icu->_swi);
  230. }
  231. break;
  232. case A_FIR:
  233. icu->fir = val & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK);
  234. break;
  235. case A_IPR ... A_IPR + 0x8f:
  236. icu->ipr[reg] = val & R_IPR_IPR_MASK;
  237. break;
  238. case A_DMRSR:
  239. case A_DMRSR + 4:
  240. case A_DMRSR + 8:
  241. case A_DMRSR + 12:
  242. icu->dmasr[reg >> 2] = val;
  243. qemu_log_mask(LOG_UNIMP, "rx_icu: DMAC not implemented\n");
  244. break;
  245. case A_IRQCR ... A_IRQCR + 0x1f:
  246. icu->src[64 + reg].sense = val >> R_IRQCR_IRQMD_SHIFT;
  247. break;
  248. case A_NMICLR:
  249. break;
  250. case A_NMIER:
  251. icu->nmier |= val & (R_NMIER_NMIEN_MASK |
  252. R_NMIER_LVDEN_MASK |
  253. R_NMIER_OSTEN_MASK);
  254. break;
  255. case A_NMICR:
  256. if ((icu->nmier & R_NMIER_NMIEN_MASK) == 0) {
  257. icu->nmicr = val & R_NMICR_NMIMD_MASK;
  258. }
  259. break;
  260. default:
  261. qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " "
  262. "not implemented\n",
  263. addr);
  264. break;
  265. }
  266. }
  267. static const MemoryRegionOps icu_ops = {
  268. .write = icu_write,
  269. .read = icu_read,
  270. .endianness = DEVICE_LITTLE_ENDIAN,
  271. .impl = {
  272. .min_access_size = 1,
  273. .max_access_size = 2,
  274. },
  275. .valid = {
  276. .min_access_size = 1,
  277. .max_access_size = 2,
  278. },
  279. };
  280. static void rxicu_realize(DeviceState *dev, Error **errp)
  281. {
  282. RXICUState *icu = RX_ICU(dev);
  283. int i, j;
  284. if (icu->init_sense == NULL) {
  285. qemu_log_mask(LOG_GUEST_ERROR,
  286. "rx_icu: trigger-level property must be set.");
  287. return;
  288. }
  289. for (i = j = 0; i < NR_IRQS; i++) {
  290. if (icu->init_sense[j] == i) {
  291. icu->src[i].sense = TRG_LEVEL;
  292. if (j < icu->nr_sense) {
  293. j++;
  294. }
  295. } else {
  296. icu->src[i].sense = TRG_PEDGE;
  297. }
  298. }
  299. icu->req_irq = -1;
  300. }
  301. static void rxicu_init(Object *obj)
  302. {
  303. SysBusDevice *d = SYS_BUS_DEVICE(obj);
  304. RXICUState *icu = RX_ICU(obj);
  305. memory_region_init_io(&icu->memory, OBJECT(icu), &icu_ops,
  306. icu, "rx-icu", 0x600);
  307. sysbus_init_mmio(d, &icu->memory);
  308. qdev_init_gpio_in(DEVICE(d), rxicu_set_irq, NR_IRQS);
  309. qdev_init_gpio_in_named(DEVICE(d), rxicu_ack_irq, "ack", 1);
  310. sysbus_init_irq(d, &icu->_irq);
  311. sysbus_init_irq(d, &icu->_fir);
  312. sysbus_init_irq(d, &icu->_swi);
  313. }
  314. static void rxicu_fini(Object *obj)
  315. {
  316. RXICUState *icu = RX_ICU(obj);
  317. g_free(icu->map);
  318. g_free(icu->init_sense);
  319. }
  320. static const VMStateDescription vmstate_rxicu = {
  321. .name = "rx-icu",
  322. .version_id = 1,
  323. .minimum_version_id = 1,
  324. .fields = (VMStateField[]) {
  325. VMSTATE_UINT8_ARRAY(ir, RXICUState, NR_IRQS),
  326. VMSTATE_UINT8_ARRAY(dtcer, RXICUState, NR_IRQS),
  327. VMSTATE_UINT8_ARRAY(ier, RXICUState, NR_IRQS / 8),
  328. VMSTATE_UINT8_ARRAY(ipr, RXICUState, 142),
  329. VMSTATE_UINT8_ARRAY(dmasr, RXICUState, 4),
  330. VMSTATE_UINT16(fir, RXICUState),
  331. VMSTATE_UINT8(nmisr, RXICUState),
  332. VMSTATE_UINT8(nmier, RXICUState),
  333. VMSTATE_UINT8(nmiclr, RXICUState),
  334. VMSTATE_UINT8(nmicr, RXICUState),
  335. VMSTATE_INT16(req_irq, RXICUState),
  336. VMSTATE_END_OF_LIST()
  337. }
  338. };
  339. static Property rxicu_properties[] = {
  340. DEFINE_PROP_ARRAY("ipr-map", RXICUState, nr_irqs, map,
  341. qdev_prop_uint8, uint8_t),
  342. DEFINE_PROP_ARRAY("trigger-level", RXICUState, nr_sense, init_sense,
  343. qdev_prop_uint8, uint8_t),
  344. DEFINE_PROP_END_OF_LIST(),
  345. };
  346. static void rxicu_class_init(ObjectClass *klass, void *data)
  347. {
  348. DeviceClass *dc = DEVICE_CLASS(klass);
  349. dc->realize = rxicu_realize;
  350. dc->vmsd = &vmstate_rxicu;
  351. device_class_set_props(dc, rxicu_properties);
  352. }
  353. static const TypeInfo rxicu_info = {
  354. .name = TYPE_RX_ICU,
  355. .parent = TYPE_SYS_BUS_DEVICE,
  356. .instance_size = sizeof(RXICUState),
  357. .instance_init = rxicu_init,
  358. .instance_finalize = rxicu_fini,
  359. .class_init = rxicu_class_init,
  360. };
  361. static void rxicu_register_types(void)
  362. {
  363. type_register_static(&rxicu_info);
  364. }
  365. type_init(rxicu_register_types)