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aspeed_scu.c 20 KB

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  1. /*
  2. * ASPEED System Control Unit
  3. *
  4. * Andrew Jeffery <andrew@aj.id.au>
  5. *
  6. * Copyright 2016 IBM Corp.
  7. *
  8. * This code is licensed under the GPL version 2 or later. See
  9. * the COPYING file in the top-level directory.
  10. */
  11. #include "qemu/osdep.h"
  12. #include "hw/misc/aspeed_scu.h"
  13. #include "hw/qdev-properties.h"
  14. #include "migration/vmstate.h"
  15. #include "qapi/error.h"
  16. #include "qapi/visitor.h"
  17. #include "qemu/bitops.h"
  18. #include "qemu/log.h"
  19. #include "qemu/guest-random.h"
  20. #include "qemu/module.h"
  21. #include "trace.h"
  22. #define TO_REG(offset) ((offset) >> 2)
  23. #define PROT_KEY TO_REG(0x00)
  24. #define SYS_RST_CTRL TO_REG(0x04)
  25. #define CLK_SEL TO_REG(0x08)
  26. #define CLK_STOP_CTRL TO_REG(0x0C)
  27. #define FREQ_CNTR_CTRL TO_REG(0x10)
  28. #define FREQ_CNTR_EVAL TO_REG(0x14)
  29. #define IRQ_CTRL TO_REG(0x18)
  30. #define D2PLL_PARAM TO_REG(0x1C)
  31. #define MPLL_PARAM TO_REG(0x20)
  32. #define HPLL_PARAM TO_REG(0x24)
  33. #define FREQ_CNTR_RANGE TO_REG(0x28)
  34. #define MISC_CTRL1 TO_REG(0x2C)
  35. #define PCI_CTRL1 TO_REG(0x30)
  36. #define PCI_CTRL2 TO_REG(0x34)
  37. #define PCI_CTRL3 TO_REG(0x38)
  38. #define SYS_RST_STATUS TO_REG(0x3C)
  39. #define SOC_SCRATCH1 TO_REG(0x40)
  40. #define SOC_SCRATCH2 TO_REG(0x44)
  41. #define MAC_CLK_DELAY TO_REG(0x48)
  42. #define MISC_CTRL2 TO_REG(0x4C)
  43. #define VGA_SCRATCH1 TO_REG(0x50)
  44. #define VGA_SCRATCH2 TO_REG(0x54)
  45. #define VGA_SCRATCH3 TO_REG(0x58)
  46. #define VGA_SCRATCH4 TO_REG(0x5C)
  47. #define VGA_SCRATCH5 TO_REG(0x60)
  48. #define VGA_SCRATCH6 TO_REG(0x64)
  49. #define VGA_SCRATCH7 TO_REG(0x68)
  50. #define VGA_SCRATCH8 TO_REG(0x6C)
  51. #define HW_STRAP1 TO_REG(0x70)
  52. #define RNG_CTRL TO_REG(0x74)
  53. #define RNG_DATA TO_REG(0x78)
  54. #define SILICON_REV TO_REG(0x7C)
  55. #define PINMUX_CTRL1 TO_REG(0x80)
  56. #define PINMUX_CTRL2 TO_REG(0x84)
  57. #define PINMUX_CTRL3 TO_REG(0x88)
  58. #define PINMUX_CTRL4 TO_REG(0x8C)
  59. #define PINMUX_CTRL5 TO_REG(0x90)
  60. #define PINMUX_CTRL6 TO_REG(0x94)
  61. #define WDT_RST_CTRL TO_REG(0x9C)
  62. #define PINMUX_CTRL7 TO_REG(0xA0)
  63. #define PINMUX_CTRL8 TO_REG(0xA4)
  64. #define PINMUX_CTRL9 TO_REG(0xA8)
  65. #define WAKEUP_EN TO_REG(0xC0)
  66. #define WAKEUP_CTRL TO_REG(0xC4)
  67. #define HW_STRAP2 TO_REG(0xD0)
  68. #define FREE_CNTR4 TO_REG(0xE0)
  69. #define FREE_CNTR4_EXT TO_REG(0xE4)
  70. #define CPU2_CTRL TO_REG(0x100)
  71. #define CPU2_BASE_SEG1 TO_REG(0x104)
  72. #define CPU2_BASE_SEG2 TO_REG(0x108)
  73. #define CPU2_BASE_SEG3 TO_REG(0x10C)
  74. #define CPU2_BASE_SEG4 TO_REG(0x110)
  75. #define CPU2_BASE_SEG5 TO_REG(0x114)
  76. #define CPU2_CACHE_CTRL TO_REG(0x118)
  77. #define UART_HPLL_CLK TO_REG(0x160)
  78. #define PCIE_CTRL TO_REG(0x180)
  79. #define BMC_MMIO_CTRL TO_REG(0x184)
  80. #define RELOC_DECODE_BASE1 TO_REG(0x188)
  81. #define RELOC_DECODE_BASE2 TO_REG(0x18C)
  82. #define MAILBOX_DECODE_BASE TO_REG(0x190)
  83. #define SRAM_DECODE_BASE1 TO_REG(0x194)
  84. #define SRAM_DECODE_BASE2 TO_REG(0x198)
  85. #define BMC_REV TO_REG(0x19C)
  86. #define BMC_DEV_ID TO_REG(0x1A4)
  87. #define AST2600_PROT_KEY TO_REG(0x00)
  88. #define AST2600_SILICON_REV TO_REG(0x04)
  89. #define AST2600_SILICON_REV2 TO_REG(0x14)
  90. #define AST2600_SYS_RST_CTRL TO_REG(0x40)
  91. #define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44)
  92. #define AST2600_SYS_RST_CTRL2 TO_REG(0x50)
  93. #define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54)
  94. #define AST2600_CLK_STOP_CTRL TO_REG(0x80)
  95. #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
  96. #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
  97. #define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94)
  98. #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
  99. #define AST2600_HPLL_PARAM TO_REG(0x200)
  100. #define AST2600_HPLL_EXT TO_REG(0x204)
  101. #define AST2600_MPLL_EXT TO_REG(0x224)
  102. #define AST2600_EPLL_EXT TO_REG(0x244)
  103. #define AST2600_CLK_SEL TO_REG(0x300)
  104. #define AST2600_CLK_SEL2 TO_REG(0x304)
  105. #define AST2600_CLK_SEL3 TO_REG(0x310)
  106. #define AST2600_HW_STRAP1 TO_REG(0x500)
  107. #define AST2600_HW_STRAP1_CLR TO_REG(0x504)
  108. #define AST2600_HW_STRAP1_PROT TO_REG(0x508)
  109. #define AST2600_HW_STRAP2 TO_REG(0x510)
  110. #define AST2600_HW_STRAP2_CLR TO_REG(0x514)
  111. #define AST2600_HW_STRAP2_PROT TO_REG(0x518)
  112. #define AST2600_RNG_CTRL TO_REG(0x524)
  113. #define AST2600_RNG_DATA TO_REG(0x540)
  114. #define AST2600_CLK TO_REG(0x40)
  115. #define SCU_IO_REGION_SIZE 0x1000
  116. static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
  117. [SYS_RST_CTRL] = 0xFFCFFEDCU,
  118. [CLK_SEL] = 0xF3F40000U,
  119. [CLK_STOP_CTRL] = 0x19FC3E8BU,
  120. [D2PLL_PARAM] = 0x00026108U,
  121. [MPLL_PARAM] = 0x00030291U,
  122. [HPLL_PARAM] = 0x00000291U,
  123. [MISC_CTRL1] = 0x00000010U,
  124. [PCI_CTRL1] = 0x20001A03U,
  125. [PCI_CTRL2] = 0x20001A03U,
  126. [PCI_CTRL3] = 0x04000030U,
  127. [SYS_RST_STATUS] = 0x00000001U,
  128. [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
  129. [MISC_CTRL2] = 0x00000023U,
  130. [RNG_CTRL] = 0x0000000EU,
  131. [PINMUX_CTRL2] = 0x0000F000U,
  132. [PINMUX_CTRL3] = 0x01000000U,
  133. [PINMUX_CTRL4] = 0x000000FFU,
  134. [PINMUX_CTRL5] = 0x0000A000U,
  135. [WDT_RST_CTRL] = 0x003FFFF3U,
  136. [PINMUX_CTRL8] = 0xFFFF0000U,
  137. [PINMUX_CTRL9] = 0x000FFFFFU,
  138. [FREE_CNTR4] = 0x000000FFU,
  139. [FREE_CNTR4_EXT] = 0x000000FFU,
  140. [CPU2_BASE_SEG1] = 0x80000000U,
  141. [CPU2_BASE_SEG4] = 0x1E600000U,
  142. [CPU2_BASE_SEG5] = 0xC0000000U,
  143. [UART_HPLL_CLK] = 0x00001903U,
  144. [PCIE_CTRL] = 0x0000007BU,
  145. [BMC_DEV_ID] = 0x00002402U
  146. };
  147. /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
  148. /* AST2500 revision A1 */
  149. static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
  150. [SYS_RST_CTRL] = 0xFFCFFEDCU,
  151. [CLK_SEL] = 0xF3F40000U,
  152. [CLK_STOP_CTRL] = 0x19FC3E8BU,
  153. [D2PLL_PARAM] = 0x00026108U,
  154. [MPLL_PARAM] = 0x00030291U,
  155. [HPLL_PARAM] = 0x93000400U,
  156. [MISC_CTRL1] = 0x00000010U,
  157. [PCI_CTRL1] = 0x20001A03U,
  158. [PCI_CTRL2] = 0x20001A03U,
  159. [PCI_CTRL3] = 0x04000030U,
  160. [SYS_RST_STATUS] = 0x00000001U,
  161. [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
  162. [MISC_CTRL2] = 0x00000023U,
  163. [RNG_CTRL] = 0x0000000EU,
  164. [PINMUX_CTRL2] = 0x0000F000U,
  165. [PINMUX_CTRL3] = 0x03000000U,
  166. [PINMUX_CTRL4] = 0x00000000U,
  167. [PINMUX_CTRL5] = 0x0000A000U,
  168. [WDT_RST_CTRL] = 0x023FFFF3U,
  169. [PINMUX_CTRL8] = 0xFFFF0000U,
  170. [PINMUX_CTRL9] = 0x000FFFFFU,
  171. [FREE_CNTR4] = 0x000000FFU,
  172. [FREE_CNTR4_EXT] = 0x000000FFU,
  173. [CPU2_BASE_SEG1] = 0x80000000U,
  174. [CPU2_BASE_SEG4] = 0x1E600000U,
  175. [CPU2_BASE_SEG5] = 0xC0000000U,
  176. [UART_HPLL_CLK] = 0x00001903U,
  177. [PCIE_CTRL] = 0x0000007BU,
  178. [BMC_DEV_ID] = 0x00002402U
  179. };
  180. static uint32_t aspeed_scu_get_random(void)
  181. {
  182. uint32_t num;
  183. qemu_guest_getrandom_nofail(&num, sizeof(num));
  184. return num;
  185. }
  186. uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
  187. {
  188. AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
  189. uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]);
  190. return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
  191. / asc->apb_divider;
  192. }
  193. static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
  194. {
  195. AspeedSCUState *s = ASPEED_SCU(opaque);
  196. int reg = TO_REG(offset);
  197. if (reg >= ASPEED_SCU_NR_REGS) {
  198. qemu_log_mask(LOG_GUEST_ERROR,
  199. "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
  200. __func__, offset);
  201. return 0;
  202. }
  203. switch (reg) {
  204. case RNG_DATA:
  205. /* On hardware, RNG_DATA works regardless of
  206. * the state of the enable bit in RNG_CTRL
  207. */
  208. s->regs[RNG_DATA] = aspeed_scu_get_random();
  209. break;
  210. case WAKEUP_EN:
  211. qemu_log_mask(LOG_GUEST_ERROR,
  212. "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
  213. __func__, offset);
  214. break;
  215. }
  216. return s->regs[reg];
  217. }
  218. static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
  219. unsigned size)
  220. {
  221. AspeedSCUState *s = ASPEED_SCU(opaque);
  222. int reg = TO_REG(offset);
  223. if (reg >= ASPEED_SCU_NR_REGS) {
  224. qemu_log_mask(LOG_GUEST_ERROR,
  225. "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
  226. __func__, offset);
  227. return;
  228. }
  229. if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
  230. !s->regs[PROT_KEY]) {
  231. qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
  232. return;
  233. }
  234. trace_aspeed_scu_write(offset, size, data);
  235. switch (reg) {
  236. case PROT_KEY:
  237. s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
  238. return;
  239. case CLK_SEL:
  240. s->regs[reg] = data;
  241. break;
  242. case HW_STRAP1:
  243. if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
  244. s->regs[HW_STRAP1] |= data;
  245. return;
  246. }
  247. /* Jump to assignment below */
  248. break;
  249. case SILICON_REV:
  250. if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
  251. s->regs[HW_STRAP1] &= ~data;
  252. } else {
  253. qemu_log_mask(LOG_GUEST_ERROR,
  254. "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
  255. __func__, offset);
  256. }
  257. /* Avoid assignment below, we've handled everything */
  258. return;
  259. case FREQ_CNTR_EVAL:
  260. case VGA_SCRATCH1 ... VGA_SCRATCH8:
  261. case RNG_DATA:
  262. case FREE_CNTR4:
  263. case FREE_CNTR4_EXT:
  264. qemu_log_mask(LOG_GUEST_ERROR,
  265. "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
  266. __func__, offset);
  267. return;
  268. }
  269. s->regs[reg] = data;
  270. }
  271. static const MemoryRegionOps aspeed_scu_ops = {
  272. .read = aspeed_scu_read,
  273. .write = aspeed_scu_write,
  274. .endianness = DEVICE_LITTLE_ENDIAN,
  275. .valid.min_access_size = 4,
  276. .valid.max_access_size = 4,
  277. .valid.unaligned = false,
  278. };
  279. static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
  280. {
  281. if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
  282. return 25000000;
  283. } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
  284. return 48000000;
  285. } else {
  286. return 24000000;
  287. }
  288. }
  289. /*
  290. * Strapped frequencies for the AST2400 in MHz. They depend on the
  291. * clkin frequency.
  292. */
  293. static const uint32_t hpll_ast2400_freqs[][4] = {
  294. { 384, 360, 336, 408 }, /* 24MHz or 48MHz */
  295. { 400, 375, 350, 425 }, /* 25MHz */
  296. };
  297. static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
  298. {
  299. uint8_t freq_select;
  300. bool clk_25m_in;
  301. uint32_t clkin = aspeed_scu_get_clkin(s);
  302. if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
  303. return 0;
  304. }
  305. if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
  306. uint32_t multiplier = 1;
  307. if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
  308. uint32_t n = (hpll_reg >> 5) & 0x3f;
  309. uint32_t od = (hpll_reg >> 4) & 0x1;
  310. uint32_t d = hpll_reg & 0xf;
  311. multiplier = (2 - od) * ((n + 2) / (d + 1));
  312. }
  313. return clkin * multiplier;
  314. }
  315. /* HW strapping */
  316. clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
  317. freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);
  318. return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
  319. }
  320. static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
  321. {
  322. uint32_t multiplier = 1;
  323. uint32_t clkin = aspeed_scu_get_clkin(s);
  324. if (hpll_reg & SCU_H_PLL_OFF) {
  325. return 0;
  326. }
  327. if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
  328. uint32_t p = (hpll_reg >> 13) & 0x3f;
  329. uint32_t m = (hpll_reg >> 5) & 0xff;
  330. uint32_t n = hpll_reg & 0x1f;
  331. multiplier = ((m + 1) / (n + 1)) / (p + 1);
  332. }
  333. return clkin * multiplier;
  334. }
  335. static void aspeed_scu_reset(DeviceState *dev)
  336. {
  337. AspeedSCUState *s = ASPEED_SCU(dev);
  338. AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
  339. memcpy(s->regs, asc->resets, asc->nr_regs * 4);
  340. s->regs[SILICON_REV] = s->silicon_rev;
  341. s->regs[HW_STRAP1] = s->hw_strap1;
  342. s->regs[HW_STRAP2] = s->hw_strap2;
  343. s->regs[PROT_KEY] = s->hw_prot_key;
  344. }
  345. static uint32_t aspeed_silicon_revs[] = {
  346. AST2400_A0_SILICON_REV,
  347. AST2400_A1_SILICON_REV,
  348. AST2500_A0_SILICON_REV,
  349. AST2500_A1_SILICON_REV,
  350. AST2600_A0_SILICON_REV,
  351. };
  352. bool is_supported_silicon_rev(uint32_t silicon_rev)
  353. {
  354. int i;
  355. for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
  356. if (silicon_rev == aspeed_silicon_revs[i]) {
  357. return true;
  358. }
  359. }
  360. return false;
  361. }
  362. static void aspeed_scu_realize(DeviceState *dev, Error **errp)
  363. {
  364. SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  365. AspeedSCUState *s = ASPEED_SCU(dev);
  366. AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
  367. if (!is_supported_silicon_rev(s->silicon_rev)) {
  368. error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
  369. s->silicon_rev);
  370. return;
  371. }
  372. memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s,
  373. TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
  374. sysbus_init_mmio(sbd, &s->iomem);
  375. }
  376. static const VMStateDescription vmstate_aspeed_scu = {
  377. .name = "aspeed.scu",
  378. .version_id = 2,
  379. .minimum_version_id = 2,
  380. .fields = (VMStateField[]) {
  381. VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS),
  382. VMSTATE_END_OF_LIST()
  383. }
  384. };
  385. static Property aspeed_scu_properties[] = {
  386. DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
  387. DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
  388. DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
  389. DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
  390. DEFINE_PROP_END_OF_LIST(),
  391. };
  392. static void aspeed_scu_class_init(ObjectClass *klass, void *data)
  393. {
  394. DeviceClass *dc = DEVICE_CLASS(klass);
  395. dc->realize = aspeed_scu_realize;
  396. dc->reset = aspeed_scu_reset;
  397. dc->desc = "ASPEED System Control Unit";
  398. dc->vmsd = &vmstate_aspeed_scu;
  399. dc->props = aspeed_scu_properties;
  400. }
  401. static const TypeInfo aspeed_scu_info = {
  402. .name = TYPE_ASPEED_SCU,
  403. .parent = TYPE_SYS_BUS_DEVICE,
  404. .instance_size = sizeof(AspeedSCUState),
  405. .class_init = aspeed_scu_class_init,
  406. .class_size = sizeof(AspeedSCUClass),
  407. .abstract = true,
  408. };
  409. static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
  410. {
  411. DeviceClass *dc = DEVICE_CLASS(klass);
  412. AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
  413. dc->desc = "ASPEED 2400 System Control Unit";
  414. asc->resets = ast2400_a0_resets;
  415. asc->calc_hpll = aspeed_2400_scu_calc_hpll;
  416. asc->apb_divider = 2;
  417. asc->nr_regs = ASPEED_SCU_NR_REGS;
  418. asc->ops = &aspeed_scu_ops;
  419. }
  420. static const TypeInfo aspeed_2400_scu_info = {
  421. .name = TYPE_ASPEED_2400_SCU,
  422. .parent = TYPE_ASPEED_SCU,
  423. .instance_size = sizeof(AspeedSCUState),
  424. .class_init = aspeed_2400_scu_class_init,
  425. };
  426. static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
  427. {
  428. DeviceClass *dc = DEVICE_CLASS(klass);
  429. AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
  430. dc->desc = "ASPEED 2500 System Control Unit";
  431. asc->resets = ast2500_a1_resets;
  432. asc->calc_hpll = aspeed_2500_scu_calc_hpll;
  433. asc->apb_divider = 4;
  434. asc->nr_regs = ASPEED_SCU_NR_REGS;
  435. asc->ops = &aspeed_scu_ops;
  436. }
  437. static const TypeInfo aspeed_2500_scu_info = {
  438. .name = TYPE_ASPEED_2500_SCU,
  439. .parent = TYPE_ASPEED_SCU,
  440. .instance_size = sizeof(AspeedSCUState),
  441. .class_init = aspeed_2500_scu_class_init,
  442. };
  443. static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset,
  444. unsigned size)
  445. {
  446. AspeedSCUState *s = ASPEED_SCU(opaque);
  447. int reg = TO_REG(offset);
  448. if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
  449. qemu_log_mask(LOG_GUEST_ERROR,
  450. "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
  451. __func__, offset);
  452. return 0;
  453. }
  454. switch (reg) {
  455. case AST2600_HPLL_EXT:
  456. case AST2600_EPLL_EXT:
  457. case AST2600_MPLL_EXT:
  458. /* PLLs are always "locked" */
  459. return s->regs[reg] | BIT(31);
  460. case AST2600_RNG_DATA:
  461. /*
  462. * On hardware, RNG_DATA works regardless of the state of the
  463. * enable bit in RNG_CTRL
  464. *
  465. * TODO: Check this is true for ast2600
  466. */
  467. s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random();
  468. break;
  469. }
  470. return s->regs[reg];
  471. }
  472. static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data,
  473. unsigned size)
  474. {
  475. AspeedSCUState *s = ASPEED_SCU(opaque);
  476. int reg = TO_REG(offset);
  477. if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
  478. qemu_log_mask(LOG_GUEST_ERROR,
  479. "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
  480. __func__, offset);
  481. return;
  482. }
  483. if (reg > PROT_KEY && !s->regs[PROT_KEY]) {
  484. qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
  485. }
  486. trace_aspeed_scu_write(offset, size, data);
  487. switch (reg) {
  488. case AST2600_PROT_KEY:
  489. s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
  490. return;
  491. case AST2600_HW_STRAP1:
  492. case AST2600_HW_STRAP2:
  493. if (s->regs[reg + 2]) {
  494. return;
  495. }
  496. /* fall through */
  497. case AST2600_SYS_RST_CTRL:
  498. case AST2600_SYS_RST_CTRL2:
  499. /* W1S (Write 1 to set) registers */
  500. s->regs[reg] |= data;
  501. return;
  502. case AST2600_SYS_RST_CTRL_CLR:
  503. case AST2600_SYS_RST_CTRL2_CLR:
  504. case AST2600_HW_STRAP1_CLR:
  505. case AST2600_HW_STRAP2_CLR:
  506. /* W1C (Write 1 to clear) registers */
  507. s->regs[reg] &= ~data;
  508. return;
  509. case AST2600_RNG_DATA:
  510. case AST2600_SILICON_REV:
  511. case AST2600_SILICON_REV2:
  512. /* Add read only registers here */
  513. qemu_log_mask(LOG_GUEST_ERROR,
  514. "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
  515. __func__, offset);
  516. return;
  517. }
  518. s->regs[reg] = data;
  519. }
  520. static const MemoryRegionOps aspeed_ast2600_scu_ops = {
  521. .read = aspeed_ast2600_scu_read,
  522. .write = aspeed_ast2600_scu_write,
  523. .endianness = DEVICE_LITTLE_ENDIAN,
  524. .valid.min_access_size = 4,
  525. .valid.max_access_size = 4,
  526. .valid.unaligned = false,
  527. };
  528. static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
  529. [AST2600_SILICON_REV] = AST2600_SILICON_REV,
  530. [AST2600_SILICON_REV2] = AST2600_SILICON_REV,
  531. [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100,
  532. [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
  533. [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
  534. [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
  535. [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
  536. [AST2600_HPLL_PARAM] = 0x1000405F,
  537. };
  538. static void aspeed_ast2600_scu_reset(DeviceState *dev)
  539. {
  540. AspeedSCUState *s = ASPEED_SCU(dev);
  541. AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
  542. memcpy(s->regs, asc->resets, asc->nr_regs * 4);
  543. s->regs[AST2600_SILICON_REV] = s->silicon_rev;
  544. s->regs[AST2600_SILICON_REV2] = s->silicon_rev;
  545. s->regs[AST2600_HW_STRAP1] = s->hw_strap1;
  546. s->regs[AST2600_HW_STRAP2] = s->hw_strap2;
  547. s->regs[PROT_KEY] = s->hw_prot_key;
  548. }
  549. static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
  550. {
  551. DeviceClass *dc = DEVICE_CLASS(klass);
  552. AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
  553. dc->desc = "ASPEED 2600 System Control Unit";
  554. dc->reset = aspeed_ast2600_scu_reset;
  555. asc->resets = ast2600_a0_resets;
  556. asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
  557. asc->apb_divider = 4;
  558. asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
  559. asc->ops = &aspeed_ast2600_scu_ops;
  560. }
  561. static const TypeInfo aspeed_2600_scu_info = {
  562. .name = TYPE_ASPEED_2600_SCU,
  563. .parent = TYPE_ASPEED_SCU,
  564. .instance_size = sizeof(AspeedSCUState),
  565. .class_init = aspeed_2600_scu_class_init,
  566. };
  567. static void aspeed_scu_register_types(void)
  568. {
  569. type_register_static(&aspeed_scu_info);
  570. type_register_static(&aspeed_2400_scu_info);
  571. type_register_static(&aspeed_2500_scu_info);
  572. type_register_static(&aspeed_2600_scu_info);
  573. }
  574. type_init(aspeed_scu_register_types);