grlib_apbuart.c 8.1 KB

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  1. /*
  2. * QEMU GRLIB APB UART Emulator
  3. *
  4. * Copyright (c) 2010-2019 AdaCore
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "qemu/osdep.h"
  25. #include "hw/irq.h"
  26. #include "hw/qdev-properties.h"
  27. #include "hw/sparc/grlib.h"
  28. #include "hw/sysbus.h"
  29. #include "qemu/module.h"
  30. #include "chardev/char-fe.h"
  31. #include "trace.h"
  32. #define UART_REG_SIZE 20 /* Size of memory mapped registers */
  33. /* UART status register fields */
  34. #define UART_DATA_READY (1 << 0)
  35. #define UART_TRANSMIT_SHIFT_EMPTY (1 << 1)
  36. #define UART_TRANSMIT_FIFO_EMPTY (1 << 2)
  37. #define UART_BREAK_RECEIVED (1 << 3)
  38. #define UART_OVERRUN (1 << 4)
  39. #define UART_PARITY_ERROR (1 << 5)
  40. #define UART_FRAMING_ERROR (1 << 6)
  41. #define UART_TRANSMIT_FIFO_HALF (1 << 7)
  42. #define UART_RECEIVE_FIFO_HALF (1 << 8)
  43. #define UART_TRANSMIT_FIFO_FULL (1 << 9)
  44. #define UART_RECEIVE_FIFO_FULL (1 << 10)
  45. /* UART control register fields */
  46. #define UART_RECEIVE_ENABLE (1 << 0)
  47. #define UART_TRANSMIT_ENABLE (1 << 1)
  48. #define UART_RECEIVE_INTERRUPT (1 << 2)
  49. #define UART_TRANSMIT_INTERRUPT (1 << 3)
  50. #define UART_PARITY_SELECT (1 << 4)
  51. #define UART_PARITY_ENABLE (1 << 5)
  52. #define UART_FLOW_CONTROL (1 << 6)
  53. #define UART_LOOPBACK (1 << 7)
  54. #define UART_EXTERNAL_CLOCK (1 << 8)
  55. #define UART_RECEIVE_FIFO_INTERRUPT (1 << 9)
  56. #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
  57. #define UART_FIFO_DEBUG_MODE (1 << 11)
  58. #define UART_OUTPUT_ENABLE (1 << 12)
  59. #define UART_FIFO_AVAILABLE (1 << 31)
  60. /* Memory mapped register offsets */
  61. #define DATA_OFFSET 0x00
  62. #define STATUS_OFFSET 0x04
  63. #define CONTROL_OFFSET 0x08
  64. #define SCALER_OFFSET 0x0C /* not supported */
  65. #define FIFO_DEBUG_OFFSET 0x10 /* not supported */
  66. #define FIFO_LENGTH 1024
  67. #define GRLIB_APB_UART(obj) \
  68. OBJECT_CHECK(UART, (obj), TYPE_GRLIB_APB_UART)
  69. typedef struct UART {
  70. SysBusDevice parent_obj;
  71. MemoryRegion iomem;
  72. qemu_irq irq;
  73. CharBackend chr;
  74. /* registers */
  75. uint32_t status;
  76. uint32_t control;
  77. /* FIFO */
  78. char buffer[FIFO_LENGTH];
  79. int len;
  80. int current;
  81. } UART;
  82. static int uart_data_to_read(UART *uart)
  83. {
  84. return uart->current < uart->len;
  85. }
  86. static char uart_pop(UART *uart)
  87. {
  88. char ret;
  89. if (uart->len == 0) {
  90. uart->status &= ~UART_DATA_READY;
  91. return 0;
  92. }
  93. ret = uart->buffer[uart->current++];
  94. if (uart->current >= uart->len) {
  95. /* Flush */
  96. uart->len = 0;
  97. uart->current = 0;
  98. }
  99. if (!uart_data_to_read(uart)) {
  100. uart->status &= ~UART_DATA_READY;
  101. }
  102. return ret;
  103. }
  104. static void uart_add_to_fifo(UART *uart,
  105. const uint8_t *buffer,
  106. int length)
  107. {
  108. if (uart->len + length > FIFO_LENGTH) {
  109. abort();
  110. }
  111. memcpy(uart->buffer + uart->len, buffer, length);
  112. uart->len += length;
  113. }
  114. static int grlib_apbuart_can_receive(void *opaque)
  115. {
  116. UART *uart = opaque;
  117. return FIFO_LENGTH - uart->len;
  118. }
  119. static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size)
  120. {
  121. UART *uart = opaque;
  122. if (uart->control & UART_RECEIVE_ENABLE) {
  123. uart_add_to_fifo(uart, buf, size);
  124. uart->status |= UART_DATA_READY;
  125. if (uart->control & UART_RECEIVE_INTERRUPT) {
  126. qemu_irq_pulse(uart->irq);
  127. }
  128. }
  129. }
  130. static void grlib_apbuart_event(void *opaque, int event)
  131. {
  132. trace_grlib_apbuart_event(event);
  133. }
  134. static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr,
  135. unsigned size)
  136. {
  137. UART *uart = opaque;
  138. addr &= 0xff;
  139. /* Unit registers */
  140. switch (addr) {
  141. case DATA_OFFSET:
  142. case DATA_OFFSET + 3: /* when only one byte read */
  143. return uart_pop(uart);
  144. case STATUS_OFFSET:
  145. /* Read Only */
  146. return uart->status;
  147. case CONTROL_OFFSET:
  148. return uart->control;
  149. case SCALER_OFFSET:
  150. /* Not supported */
  151. return 0;
  152. default:
  153. trace_grlib_apbuart_readl_unknown(addr);
  154. return 0;
  155. }
  156. }
  157. static void grlib_apbuart_write(void *opaque, hwaddr addr,
  158. uint64_t value, unsigned size)
  159. {
  160. UART *uart = opaque;
  161. unsigned char c = 0;
  162. addr &= 0xff;
  163. /* Unit registers */
  164. switch (addr) {
  165. case DATA_OFFSET:
  166. case DATA_OFFSET + 3: /* When only one byte write */
  167. /* Transmit when character device available and transmitter enabled */
  168. if (qemu_chr_fe_backend_connected(&uart->chr) &&
  169. (uart->control & UART_TRANSMIT_ENABLE)) {
  170. c = value & 0xFF;
  171. /* XXX this blocks entire thread. Rewrite to use
  172. * qemu_chr_fe_write and background I/O callbacks */
  173. qemu_chr_fe_write_all(&uart->chr, &c, 1);
  174. /* Generate interrupt */
  175. if (uart->control & UART_TRANSMIT_INTERRUPT) {
  176. qemu_irq_pulse(uart->irq);
  177. }
  178. }
  179. return;
  180. case STATUS_OFFSET:
  181. /* Read Only */
  182. return;
  183. case CONTROL_OFFSET:
  184. uart->control = value;
  185. return;
  186. case SCALER_OFFSET:
  187. /* Not supported */
  188. return;
  189. default:
  190. break;
  191. }
  192. trace_grlib_apbuart_writel_unknown(addr, value);
  193. }
  194. static const MemoryRegionOps grlib_apbuart_ops = {
  195. .write = grlib_apbuart_write,
  196. .read = grlib_apbuart_read,
  197. .endianness = DEVICE_NATIVE_ENDIAN,
  198. };
  199. static void grlib_apbuart_realize(DeviceState *dev, Error **errp)
  200. {
  201. UART *uart = GRLIB_APB_UART(dev);
  202. SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  203. qemu_chr_fe_set_handlers(&uart->chr,
  204. grlib_apbuart_can_receive,
  205. grlib_apbuart_receive,
  206. grlib_apbuart_event,
  207. NULL, uart, NULL, true);
  208. sysbus_init_irq(sbd, &uart->irq);
  209. memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,
  210. "uart", UART_REG_SIZE);
  211. sysbus_init_mmio(sbd, &uart->iomem);
  212. }
  213. static void grlib_apbuart_reset(DeviceState *d)
  214. {
  215. UART *uart = GRLIB_APB_UART(d);
  216. /* Transmitter FIFO and shift registers are always empty in QEMU */
  217. uart->status = UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY;
  218. /* Everything is off */
  219. uart->control = 0;
  220. /* Flush receive FIFO */
  221. uart->len = 0;
  222. uart->current = 0;
  223. }
  224. static Property grlib_apbuart_properties[] = {
  225. DEFINE_PROP_CHR("chrdev", UART, chr),
  226. DEFINE_PROP_END_OF_LIST(),
  227. };
  228. static void grlib_apbuart_class_init(ObjectClass *klass, void *data)
  229. {
  230. DeviceClass *dc = DEVICE_CLASS(klass);
  231. dc->realize = grlib_apbuart_realize;
  232. dc->reset = grlib_apbuart_reset;
  233. dc->props = grlib_apbuart_properties;
  234. }
  235. static const TypeInfo grlib_apbuart_info = {
  236. .name = TYPE_GRLIB_APB_UART,
  237. .parent = TYPE_SYS_BUS_DEVICE,
  238. .instance_size = sizeof(UART),
  239. .class_init = grlib_apbuart_class_init,
  240. };
  241. static void grlib_apbuart_register_types(void)
  242. {
  243. type_register_static(&grlib_apbuart_info);
  244. }
  245. type_init(grlib_apbuart_register_types)