xlnx-zynqmp.c 23 KB

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  1. /*
  2. * Xilinx Zynq MPSoC emulation
  3. *
  4. * Copyright (C) 2015 Xilinx Inc
  5. * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15. * for more details.
  16. */
  17. #include "qemu/osdep.h"
  18. #include "qapi/error.h"
  19. #include "qemu/module.h"
  20. #include "cpu.h"
  21. #include "hw/arm/xlnx-zynqmp.h"
  22. #include "hw/intc/arm_gic_common.h"
  23. #include "hw/boards.h"
  24. #include "exec/address-spaces.h"
  25. #include "sysemu/kvm.h"
  26. #include "sysemu/sysemu.h"
  27. #include "kvm_arm.h"
  28. #define GIC_NUM_SPI_INTR 160
  29. #define ARM_PHYS_TIMER_PPI 30
  30. #define ARM_VIRT_TIMER_PPI 27
  31. #define ARM_HYP_TIMER_PPI 26
  32. #define ARM_SEC_TIMER_PPI 29
  33. #define GIC_MAINTENANCE_PPI 25
  34. #define GEM_REVISION 0x40070106
  35. #define GIC_BASE_ADDR 0xf9000000
  36. #define GIC_DIST_ADDR 0xf9010000
  37. #define GIC_CPU_ADDR 0xf9020000
  38. #define GIC_VIFACE_ADDR 0xf9040000
  39. #define GIC_VCPU_ADDR 0xf9060000
  40. #define SATA_INTR 133
  41. #define SATA_ADDR 0xFD0C0000
  42. #define SATA_NUM_PORTS 2
  43. #define QSPI_ADDR 0xff0f0000
  44. #define LQSPI_ADDR 0xc0000000
  45. #define QSPI_IRQ 15
  46. #define DP_ADDR 0xfd4a0000
  47. #define DP_IRQ 113
  48. #define DPDMA_ADDR 0xfd4c0000
  49. #define DPDMA_IRQ 116
  50. #define IPI_ADDR 0xFF300000
  51. #define IPI_IRQ 64
  52. #define RTC_ADDR 0xffa60000
  53. #define RTC_IRQ 26
  54. #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
  55. static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  56. 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  57. };
  58. static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  59. 57, 59, 61, 63,
  60. };
  61. static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  62. 0xFF000000, 0xFF010000,
  63. };
  64. static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  65. 21, 22,
  66. };
  67. static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  68. 0xFF160000, 0xFF170000,
  69. };
  70. static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  71. 48, 49,
  72. };
  73. static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  74. 0xFF040000, 0xFF050000,
  75. };
  76. static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  77. 19, 20,
  78. };
  79. static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
  80. 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
  81. 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
  82. };
  83. static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
  84. 124, 125, 126, 127, 128, 129, 130, 131
  85. };
  86. static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
  87. 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
  88. 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
  89. };
  90. static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
  91. 77, 78, 79, 80, 81, 82, 83, 84
  92. };
  93. typedef struct XlnxZynqMPGICRegion {
  94. int region_index;
  95. uint32_t address;
  96. uint32_t offset;
  97. bool virt;
  98. } XlnxZynqMPGICRegion;
  99. static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  100. /* Distributor */
  101. {
  102. .region_index = 0,
  103. .address = GIC_DIST_ADDR,
  104. .offset = 0,
  105. .virt = false
  106. },
  107. /* CPU interface */
  108. {
  109. .region_index = 1,
  110. .address = GIC_CPU_ADDR,
  111. .offset = 0,
  112. .virt = false
  113. },
  114. {
  115. .region_index = 1,
  116. .address = GIC_CPU_ADDR + 0x10000,
  117. .offset = 0x1000,
  118. .virt = false
  119. },
  120. /* Virtual interface */
  121. {
  122. .region_index = 2,
  123. .address = GIC_VIFACE_ADDR,
  124. .offset = 0,
  125. .virt = true
  126. },
  127. /* Virtual CPU interface */
  128. {
  129. .region_index = 3,
  130. .address = GIC_VCPU_ADDR,
  131. .offset = 0,
  132. .virt = true
  133. },
  134. {
  135. .region_index = 3,
  136. .address = GIC_VCPU_ADDR + 0x10000,
  137. .offset = 0x1000,
  138. .virt = true
  139. },
  140. };
  141. static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  142. {
  143. return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
  144. }
  145. static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
  146. const char *boot_cpu, Error **errp)
  147. {
  148. Error *err = NULL;
  149. int i;
  150. int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
  151. XLNX_ZYNQMP_NUM_RPU_CPUS);
  152. if (num_rpus <= 0) {
  153. /* Don't create rpu-cluster object if there's nothing to put in it */
  154. return;
  155. }
  156. object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
  157. sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER,
  158. &error_abort, NULL);
  159. qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
  160. for (i = 0; i < num_rpus; i++) {
  161. char *name;
  162. object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
  163. &s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
  164. ARM_CPU_TYPE_NAME("cortex-r5f"),
  165. &error_abort, NULL);
  166. name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
  167. if (strcmp(name, boot_cpu)) {
  168. /* Secondary CPUs start in PSCI powered-down state */
  169. object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
  170. "start-powered-off", &error_abort);
  171. } else {
  172. s->boot_cpu_ptr = &s->rpu_cpu[i];
  173. }
  174. g_free(name);
  175. object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
  176. &error_abort);
  177. object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
  178. &err);
  179. if (err) {
  180. error_propagate(errp, err);
  181. return;
  182. }
  183. }
  184. qdev_init_nofail(DEVICE(&s->rpu_cluster));
  185. }
  186. static void xlnx_zynqmp_init(Object *obj)
  187. {
  188. MachineState *ms = MACHINE(qdev_get_machine());
  189. XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
  190. int i;
  191. int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
  192. object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
  193. sizeof(s->apu_cluster), TYPE_CPU_CLUSTER,
  194. &error_abort, NULL);
  195. qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
  196. for (i = 0; i < num_apus; i++) {
  197. object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
  198. &s->apu_cpu[i], sizeof(s->apu_cpu[i]),
  199. ARM_CPU_TYPE_NAME("cortex-a53"),
  200. &error_abort, NULL);
  201. }
  202. sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
  203. gic_class_name());
  204. for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
  205. sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]),
  206. TYPE_CADENCE_GEM);
  207. }
  208. for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
  209. sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
  210. TYPE_CADENCE_UART);
  211. }
  212. sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
  213. TYPE_SYSBUS_AHCI);
  214. for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
  215. sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i],
  216. sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI);
  217. }
  218. for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
  219. sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
  220. TYPE_XILINX_SPIPS);
  221. }
  222. sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi),
  223. TYPE_XLNX_ZYNQMP_QSPIPS);
  224. sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP);
  225. sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma),
  226. TYPE_XLNX_DPDMA);
  227. sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi),
  228. TYPE_XLNX_ZYNQMP_IPI);
  229. sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
  230. TYPE_XLNX_ZYNQMP_RTC);
  231. for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
  232. sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]),
  233. TYPE_XLNX_ZDMA);
  234. }
  235. for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
  236. sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]),
  237. TYPE_XLNX_ZDMA);
  238. }
  239. }
  240. static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
  241. {
  242. MachineState *ms = MACHINE(qdev_get_machine());
  243. XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
  244. MemoryRegion *system_memory = get_system_memory();
  245. uint8_t i;
  246. uint64_t ram_size;
  247. int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
  248. const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
  249. ram_addr_t ddr_low_size, ddr_high_size;
  250. qemu_irq gic_spi[GIC_NUM_SPI_INTR];
  251. Error *err = NULL;
  252. ram_size = memory_region_size(s->ddr_ram);
  253. /* Create the DDR Memory Regions. User friendly checks should happen at
  254. * the board level
  255. */
  256. if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
  257. /* The RAM size is above the maximum available for the low DDR.
  258. * Create the high DDR memory region as well.
  259. */
  260. assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
  261. ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
  262. ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
  263. memory_region_init_alias(&s->ddr_ram_high, NULL,
  264. "ddr-ram-high", s->ddr_ram,
  265. ddr_low_size, ddr_high_size);
  266. memory_region_add_subregion(get_system_memory(),
  267. XLNX_ZYNQMP_HIGH_RAM_START,
  268. &s->ddr_ram_high);
  269. } else {
  270. /* RAM must be non-zero */
  271. assert(ram_size);
  272. ddr_low_size = ram_size;
  273. }
  274. memory_region_init_alias(&s->ddr_ram_low, NULL,
  275. "ddr-ram-low", s->ddr_ram,
  276. 0, ddr_low_size);
  277. memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
  278. /* Create the four OCM banks */
  279. for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
  280. char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
  281. memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
  282. XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
  283. memory_region_add_subregion(get_system_memory(),
  284. XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
  285. i * XLNX_ZYNQMP_OCM_RAM_SIZE,
  286. &s->ocm_ram[i]);
  287. g_free(ocm_name);
  288. }
  289. qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
  290. qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
  291. qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
  292. qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
  293. qdev_prop_set_bit(DEVICE(&s->gic),
  294. "has-virtualization-extensions", s->virt);
  295. qdev_init_nofail(DEVICE(&s->apu_cluster));
  296. /* Realize APUs before realizing the GIC. KVM requires this. */
  297. for (i = 0; i < num_apus; i++) {
  298. char *name;
  299. object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
  300. "psci-conduit", &error_abort);
  301. name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
  302. if (strcmp(name, boot_cpu)) {
  303. /* Secondary CPUs start in PSCI powered-down state */
  304. object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
  305. "start-powered-off", &error_abort);
  306. } else {
  307. s->boot_cpu_ptr = &s->apu_cpu[i];
  308. }
  309. g_free(name);
  310. object_property_set_bool(OBJECT(&s->apu_cpu[i]),
  311. s->secure, "has_el3", NULL);
  312. object_property_set_bool(OBJECT(&s->apu_cpu[i]),
  313. s->virt, "has_el2", NULL);
  314. object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
  315. "reset-cbar", &error_abort);
  316. object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
  317. "core-count", &error_abort);
  318. object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
  319. &err);
  320. if (err) {
  321. error_propagate(errp, err);
  322. return;
  323. }
  324. }
  325. object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  326. if (err) {
  327. error_propagate(errp, err);
  328. return;
  329. }
  330. assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
  331. for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
  332. SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
  333. const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
  334. MemoryRegion *mr;
  335. uint32_t addr = r->address;
  336. int j;
  337. if (r->virt && !s->virt) {
  338. continue;
  339. }
  340. mr = sysbus_mmio_get_region(gic, r->region_index);
  341. for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
  342. MemoryRegion *alias = &s->gic_mr[i][j];
  343. memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
  344. r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
  345. memory_region_add_subregion(system_memory, addr, alias);
  346. addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
  347. }
  348. }
  349. for (i = 0; i < num_apus; i++) {
  350. qemu_irq irq;
  351. sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
  352. qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
  353. ARM_CPU_IRQ));
  354. sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
  355. qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
  356. ARM_CPU_FIQ));
  357. sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
  358. qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
  359. ARM_CPU_VIRQ));
  360. sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
  361. qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
  362. ARM_CPU_VFIQ));
  363. irq = qdev_get_gpio_in(DEVICE(&s->gic),
  364. arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
  365. qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
  366. irq = qdev_get_gpio_in(DEVICE(&s->gic),
  367. arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
  368. qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
  369. irq = qdev_get_gpio_in(DEVICE(&s->gic),
  370. arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
  371. qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
  372. irq = qdev_get_gpio_in(DEVICE(&s->gic),
  373. arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
  374. qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
  375. if (s->virt) {
  376. irq = qdev_get_gpio_in(DEVICE(&s->gic),
  377. arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
  378. sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
  379. }
  380. }
  381. if (s->has_rpu) {
  382. info_report("The 'has_rpu' property is no longer required, to use the "
  383. "RPUs just use -smp 6.");
  384. }
  385. xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
  386. if (err) {
  387. error_propagate(errp, err);
  388. return;
  389. }
  390. if (!s->boot_cpu_ptr) {
  391. error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
  392. return;
  393. }
  394. for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
  395. gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
  396. }
  397. for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
  398. NICInfo *nd = &nd_table[i];
  399. if (nd->used) {
  400. qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
  401. qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
  402. }
  403. object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
  404. &error_abort);
  405. object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
  406. &error_abort);
  407. object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
  408. if (err) {
  409. error_propagate(errp, err);
  410. return;
  411. }
  412. sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
  413. sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
  414. gic_spi[gem_intr[i]]);
  415. }
  416. for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
  417. qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
  418. object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
  419. if (err) {
  420. error_propagate(errp, err);
  421. return;
  422. }
  423. sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
  424. sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
  425. gic_spi[uart_intr[i]]);
  426. }
  427. object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
  428. &error_abort);
  429. object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
  430. if (err) {
  431. error_propagate(errp, err);
  432. return;
  433. }
  434. sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
  435. sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
  436. for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
  437. char *bus_name = g_strdup_printf("sd-bus%d", i);
  438. SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
  439. Object *sdhci = OBJECT(&s->sdhci[i]);
  440. /* Compatible with:
  441. * - SD Host Controller Specification Version 3.00
  442. * - SDIO Specification Version 3.0
  443. * - eMMC Specification Version 4.51
  444. */
  445. object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
  446. object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
  447. object_property_set_uint(sdhci, UHS_I, "uhs", &err);
  448. object_property_set_bool(sdhci, true, "realized", &err);
  449. if (err) {
  450. error_propagate(errp, err);
  451. return;
  452. }
  453. sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
  454. sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
  455. /* Alias controller SD bus to the SoC itself */
  456. object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
  457. &error_abort);
  458. g_free(bus_name);
  459. }
  460. for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
  461. gchar *bus_name;
  462. object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
  463. sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
  464. sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
  465. gic_spi[spi_intr[i]]);
  466. /* Alias controller SPI bus to the SoC itself */
  467. bus_name = g_strdup_printf("spi%d", i);
  468. object_property_add_alias(OBJECT(s), bus_name,
  469. OBJECT(&s->spi[i]), "spi0",
  470. &error_abort);
  471. g_free(bus_name);
  472. }
  473. object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
  474. sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
  475. sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
  476. sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
  477. for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
  478. gchar *bus_name;
  479. gchar *target_bus;
  480. /* Alias controller SPI bus to the SoC itself */
  481. bus_name = g_strdup_printf("qspi%d", i);
  482. target_bus = g_strdup_printf("spi%d", i);
  483. object_property_add_alias(OBJECT(s), bus_name,
  484. OBJECT(&s->qspi), target_bus,
  485. &error_abort);
  486. g_free(bus_name);
  487. g_free(target_bus);
  488. }
  489. object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
  490. if (err) {
  491. error_propagate(errp, err);
  492. return;
  493. }
  494. sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
  495. sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
  496. object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
  497. if (err) {
  498. error_propagate(errp, err);
  499. return;
  500. }
  501. object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
  502. &error_abort);
  503. sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
  504. sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
  505. object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
  506. if (err) {
  507. error_propagate(errp, err);
  508. return;
  509. }
  510. sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
  511. sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
  512. object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
  513. if (err) {
  514. error_propagate(errp, err);
  515. return;
  516. }
  517. sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
  518. sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
  519. for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
  520. object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
  521. object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
  522. if (err) {
  523. error_propagate(errp, err);
  524. return;
  525. }
  526. sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
  527. sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
  528. gic_spi[gdma_ch_intr[i]]);
  529. }
  530. for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
  531. object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err);
  532. if (err) {
  533. error_propagate(errp, err);
  534. return;
  535. }
  536. sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
  537. sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
  538. gic_spi[adma_ch_intr[i]]);
  539. }
  540. }
  541. static Property xlnx_zynqmp_props[] = {
  542. DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
  543. DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
  544. DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
  545. DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
  546. DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
  547. MemoryRegion *),
  548. DEFINE_PROP_END_OF_LIST()
  549. };
  550. static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
  551. {
  552. DeviceClass *dc = DEVICE_CLASS(oc);
  553. dc->props = xlnx_zynqmp_props;
  554. dc->realize = xlnx_zynqmp_realize;
  555. /* Reason: Uses serial_hds in realize function, thus can't be used twice */
  556. dc->user_creatable = false;
  557. }
  558. static const TypeInfo xlnx_zynqmp_type_info = {
  559. .name = TYPE_XLNX_ZYNQMP,
  560. .parent = TYPE_DEVICE,
  561. .instance_size = sizeof(XlnxZynqMPState),
  562. .instance_init = xlnx_zynqmp_init,
  563. .class_init = xlnx_zynqmp_class_init,
  564. };
  565. static void xlnx_zynqmp_register_types(void)
  566. {
  567. type_register_static(&xlnx_zynqmp_type_info);
  568. }
  569. type_init(xlnx_zynqmp_register_types)