pflash_cfi02.c 33 KB

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  1. /*
  2. * CFI parallel flash with AMD command set emulation
  3. *
  4. * Copyright (c) 2005 Jocelyn Mayer
  5. *
  6. * This library is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU Lesser General Public
  8. * License as published by the Free Software Foundation; either
  9. * version 2.1 of the License, or (at your option) any later version.
  10. *
  11. * This library is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * Lesser General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU Lesser General Public
  17. * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. /*
  20. * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  21. * Supported commands/modes are:
  22. * - flash read
  23. * - flash write
  24. * - flash ID read
  25. * - sector erase
  26. * - chip erase
  27. * - unlock bypass command
  28. * - CFI queries
  29. *
  30. * It does not support flash interleaving.
  31. * It does not implement software data protection as found in many real chips
  32. */
  33. #include "qemu/osdep.h"
  34. #include "hw/block/block.h"
  35. #include "hw/block/flash.h"
  36. #include "hw/qdev-properties.h"
  37. #include "hw/qdev-properties-system.h"
  38. #include "qapi/error.h"
  39. #include "qemu/error-report.h"
  40. #include "qemu/bitmap.h"
  41. #include "qemu/timer.h"
  42. #include "sysemu/block-backend.h"
  43. #include "qemu/host-utils.h"
  44. #include "qemu/module.h"
  45. #include "hw/sysbus.h"
  46. #include "migration/vmstate.h"
  47. #include "trace.h"
  48. #define PFLASH_LAZY_ROMD_THRESHOLD 42
  49. /*
  50. * The size of the cfi_table indirectly depends on this and the start of the
  51. * PRI table directly depends on it. 4 is the maximum size (and also what
  52. * seems common) without changing the PRT table address.
  53. */
  54. #define PFLASH_MAX_ERASE_REGIONS 4
  55. /* Special write cycles for CFI queries. */
  56. enum {
  57. WCYCLE_CFI = 7,
  58. WCYCLE_AUTOSELECT_CFI = 8,
  59. };
  60. struct PFlashCFI02 {
  61. /*< private >*/
  62. SysBusDevice parent_obj;
  63. /*< public >*/
  64. BlockBackend *blk;
  65. uint32_t uniform_nb_blocs;
  66. uint32_t uniform_sector_len;
  67. uint32_t total_sectors;
  68. uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS];
  69. uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS];
  70. uint32_t chip_len;
  71. uint8_t mappings;
  72. uint8_t width;
  73. uint8_t be;
  74. int wcycle; /* if 0, the flash is read normally */
  75. int bypass;
  76. int ro;
  77. uint8_t cmd;
  78. uint8_t status;
  79. /* FIXME: implement array device properties */
  80. uint16_t ident0;
  81. uint16_t ident1;
  82. uint16_t ident2;
  83. uint16_t ident3;
  84. uint16_t unlock_addr0;
  85. uint16_t unlock_addr1;
  86. uint8_t cfi_table[0x4d];
  87. QEMUTimer timer;
  88. /*
  89. * The device replicates the flash memory across its memory space. Emulate
  90. * that by having a container (.mem) filled with an array of aliases
  91. * (.mem_mappings) pointing to the flash memory (.orig_mem).
  92. */
  93. MemoryRegion mem;
  94. MemoryRegion *mem_mappings; /* array; one per mapping */
  95. MemoryRegion orig_mem;
  96. bool rom_mode;
  97. int read_counter; /* used for lazy switch-back to rom mode */
  98. int sectors_to_erase;
  99. uint64_t erase_time_remaining;
  100. unsigned long *sector_erase_map;
  101. char *name;
  102. void *storage;
  103. };
  104. /*
  105. * Toggle status bit DQ7.
  106. */
  107. static inline void toggle_dq7(PFlashCFI02 *pfl)
  108. {
  109. pfl->status ^= 0x80;
  110. }
  111. /*
  112. * Set status bit DQ7 to bit 7 of value.
  113. */
  114. static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value)
  115. {
  116. pfl->status &= 0x7F;
  117. pfl->status |= value & 0x80;
  118. }
  119. /*
  120. * Toggle status bit DQ6.
  121. */
  122. static inline void toggle_dq6(PFlashCFI02 *pfl)
  123. {
  124. pfl->status ^= 0x40;
  125. }
  126. /*
  127. * Turn on DQ3.
  128. */
  129. static inline void assert_dq3(PFlashCFI02 *pfl)
  130. {
  131. pfl->status |= 0x08;
  132. }
  133. /*
  134. * Turn off DQ3.
  135. */
  136. static inline void reset_dq3(PFlashCFI02 *pfl)
  137. {
  138. pfl->status &= ~0x08;
  139. }
  140. /*
  141. * Toggle status bit DQ2.
  142. */
  143. static inline void toggle_dq2(PFlashCFI02 *pfl)
  144. {
  145. pfl->status ^= 0x04;
  146. }
  147. /*
  148. * Set up replicated mappings of the same region.
  149. */
  150. static void pflash_setup_mappings(PFlashCFI02 *pfl)
  151. {
  152. unsigned i;
  153. hwaddr size = memory_region_size(&pfl->orig_mem);
  154. memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
  155. pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
  156. for (i = 0; i < pfl->mappings; ++i) {
  157. memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
  158. "pflash-alias", &pfl->orig_mem, 0, size);
  159. memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
  160. }
  161. }
  162. static void pflash_reset_state_machine(PFlashCFI02 *pfl)
  163. {
  164. trace_pflash_reset(pfl->name);
  165. pfl->cmd = 0x00;
  166. pfl->wcycle = 0;
  167. }
  168. static void pflash_mode_read_array(PFlashCFI02 *pfl)
  169. {
  170. trace_pflash_mode_read_array(pfl->name);
  171. pflash_reset_state_machine(pfl);
  172. pfl->rom_mode = true;
  173. memory_region_rom_device_set_romd(&pfl->orig_mem, true);
  174. }
  175. static size_t pflash_regions_count(PFlashCFI02 *pfl)
  176. {
  177. return pfl->cfi_table[0x2c];
  178. }
  179. /*
  180. * Returns the time it takes to erase the number of sectors scheduled for
  181. * erasure based on CFI address 0x21 which is "Typical timeout per individual
  182. * block erase 2^N ms."
  183. */
  184. static uint64_t pflash_erase_time(PFlashCFI02 *pfl)
  185. {
  186. /*
  187. * If there are no sectors to erase (which can happen if all of the sectors
  188. * to be erased are protected), then erase takes 100 us. Protected sectors
  189. * aren't supported so this should never happen.
  190. */
  191. return ((1ULL << pfl->cfi_table[0x21]) * pfl->sectors_to_erase) * SCALE_US;
  192. }
  193. /*
  194. * Returns true if the device is currently in erase suspend mode.
  195. */
  196. static inline bool pflash_erase_suspend_mode(PFlashCFI02 *pfl)
  197. {
  198. return pfl->erase_time_remaining > 0;
  199. }
  200. static void pflash_timer(void *opaque)
  201. {
  202. PFlashCFI02 *pfl = opaque;
  203. trace_pflash_timer_expired(pfl->name, pfl->cmd);
  204. if (pfl->cmd == 0x30) {
  205. /*
  206. * Sector erase. If DQ3 is 0 when the timer expires, then the 50
  207. * us erase timeout has expired so we need to start the timer for the
  208. * sector erase algorithm. Otherwise, the erase completed and we should
  209. * go back to read array mode.
  210. */
  211. if ((pfl->status & 0x08) == 0) {
  212. assert_dq3(pfl);
  213. uint64_t timeout = pflash_erase_time(pfl);
  214. timer_mod(&pfl->timer,
  215. qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
  216. trace_pflash_erase_timeout(pfl->name, pfl->sectors_to_erase);
  217. return;
  218. }
  219. trace_pflash_erase_complete(pfl->name);
  220. bitmap_zero(pfl->sector_erase_map, pfl->total_sectors);
  221. pfl->sectors_to_erase = 0;
  222. reset_dq3(pfl);
  223. }
  224. /* Reset flash */
  225. toggle_dq7(pfl);
  226. if (pfl->bypass) {
  227. pfl->wcycle = 2;
  228. pfl->cmd = 0;
  229. } else {
  230. pflash_mode_read_array(pfl);
  231. }
  232. }
  233. /*
  234. * Read data from flash.
  235. */
  236. static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset,
  237. unsigned int width)
  238. {
  239. uint8_t *p = (uint8_t *)pfl->storage + offset;
  240. uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width);
  241. trace_pflash_data_read(pfl->name, offset, width, ret);
  242. return ret;
  243. }
  244. typedef struct {
  245. uint32_t len;
  246. uint32_t num;
  247. } SectorInfo;
  248. /*
  249. * offset should be a byte offset of the QEMU device and _not_ a device
  250. * offset.
  251. */
  252. static SectorInfo pflash_sector_info(PFlashCFI02 *pfl, hwaddr offset)
  253. {
  254. assert(offset < pfl->chip_len);
  255. hwaddr addr = 0;
  256. uint32_t sector_num = 0;
  257. for (int i = 0; i < pflash_regions_count(pfl); ++i) {
  258. uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i];
  259. if (addr <= offset && offset < addr + region_size) {
  260. return (SectorInfo) {
  261. .len = pfl->sector_len[i],
  262. .num = sector_num + (offset - addr) / pfl->sector_len[i],
  263. };
  264. }
  265. sector_num += pfl->nb_blocs[i];
  266. addr += region_size;
  267. }
  268. abort();
  269. }
  270. /*
  271. * Returns true if the offset refers to a flash sector that is currently being
  272. * erased.
  273. */
  274. static bool pflash_sector_is_erasing(PFlashCFI02 *pfl, hwaddr offset)
  275. {
  276. long sector_num = pflash_sector_info(pfl, offset).num;
  277. return test_bit(sector_num, pfl->sector_erase_map);
  278. }
  279. static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
  280. {
  281. PFlashCFI02 *pfl = opaque;
  282. hwaddr boff;
  283. uint64_t ret;
  284. /* Lazy reset to ROMD mode after a certain amount of read accesses */
  285. if (!pfl->rom_mode && pfl->wcycle == 0 &&
  286. ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
  287. pflash_mode_read_array(pfl);
  288. }
  289. offset &= pfl->chip_len - 1;
  290. boff = offset & 0xFF;
  291. if (pfl->width == 2) {
  292. boff = boff >> 1;
  293. } else if (pfl->width == 4) {
  294. boff = boff >> 2;
  295. }
  296. switch (pfl->cmd) {
  297. default:
  298. /* This should never happen : reset state & treat it as a read*/
  299. trace_pflash_read_unknown_state(pfl->name, pfl->cmd);
  300. pflash_reset_state_machine(pfl);
  301. /* fall through to the read code */
  302. case 0x80: /* Erase (unlock) */
  303. /* We accept reads during second unlock sequence... */
  304. case 0x00:
  305. if (pflash_erase_suspend_mode(pfl) &&
  306. pflash_sector_is_erasing(pfl, offset)) {
  307. /* Toggle bit 2, but not 6. */
  308. toggle_dq2(pfl);
  309. /* Status register read */
  310. ret = pfl->status;
  311. trace_pflash_read_status(pfl->name, ret);
  312. break;
  313. }
  314. /* Flash area read */
  315. ret = pflash_data_read(pfl, offset, width);
  316. break;
  317. case 0x90: /* flash ID read */
  318. switch (boff) {
  319. case 0x00:
  320. case 0x01:
  321. ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
  322. break;
  323. case 0x02:
  324. ret = 0x00; /* Pretend all sectors are unprotected */
  325. break;
  326. case 0x0E:
  327. case 0x0F:
  328. ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
  329. if (ret != (uint8_t)-1) {
  330. break;
  331. }
  332. /* Fall through to data read. */
  333. default:
  334. ret = pflash_data_read(pfl, offset, width);
  335. }
  336. trace_pflash_read_done(pfl->name, boff, ret);
  337. break;
  338. case 0x10: /* Chip Erase */
  339. case 0x30: /* Sector Erase */
  340. /* Toggle bit 2 during erase, but not program. */
  341. toggle_dq2(pfl);
  342. /* fall through */
  343. case 0xA0: /* Program */
  344. /* Toggle bit 6 */
  345. toggle_dq6(pfl);
  346. /* Status register read */
  347. ret = pfl->status;
  348. trace_pflash_read_status(pfl->name, ret);
  349. break;
  350. case 0x98:
  351. /* CFI query mode */
  352. if (boff < sizeof(pfl->cfi_table)) {
  353. ret = pfl->cfi_table[boff];
  354. } else {
  355. ret = 0;
  356. }
  357. break;
  358. }
  359. trace_pflash_io_read(pfl->name, offset, width, ret, pfl->cmd, pfl->wcycle);
  360. return ret;
  361. }
  362. /* update flash content on disk */
  363. static void pflash_update(PFlashCFI02 *pfl, int offset, int size)
  364. {
  365. int offset_end;
  366. int ret;
  367. if (pfl->blk) {
  368. offset_end = offset + size;
  369. /* widen to sector boundaries */
  370. offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
  371. offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
  372. ret = blk_pwrite(pfl->blk, offset, offset_end - offset,
  373. pfl->storage + offset, 0);
  374. if (ret < 0) {
  375. /* TODO set error bit in status */
  376. error_report("Could not update PFLASH: %s", strerror(-ret));
  377. }
  378. }
  379. }
  380. static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset)
  381. {
  382. SectorInfo sector_info = pflash_sector_info(pfl, offset);
  383. uint64_t sector_len = sector_info.len;
  384. offset &= ~(sector_len - 1);
  385. trace_pflash_sector_erase_start(pfl->name, pfl->width * 2, offset,
  386. pfl->width * 2, offset + sector_len - 1);
  387. if (!pfl->ro) {
  388. uint8_t *p = pfl->storage;
  389. memset(p + offset, 0xff, sector_len);
  390. pflash_update(pfl, offset, sector_len);
  391. }
  392. set_dq7(pfl, 0x00);
  393. ++pfl->sectors_to_erase;
  394. set_bit(sector_info.num, pfl->sector_erase_map);
  395. /* Set (or reset) the 50 us timer for additional erase commands. */
  396. timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000);
  397. }
  398. static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
  399. unsigned int width)
  400. {
  401. PFlashCFI02 *pfl = opaque;
  402. hwaddr boff;
  403. uint8_t *p;
  404. uint8_t cmd;
  405. trace_pflash_io_write(pfl->name, offset, width, value, pfl->wcycle);
  406. cmd = value;
  407. if (pfl->cmd != 0xA0) {
  408. /* Reset does nothing during chip erase and sector erase. */
  409. if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) {
  410. if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) {
  411. /* Return to autoselect mode. */
  412. pfl->wcycle = 3;
  413. pfl->cmd = 0x90;
  414. return;
  415. }
  416. goto reset_flash;
  417. }
  418. }
  419. offset &= pfl->chip_len - 1;
  420. boff = offset;
  421. if (pfl->width == 2) {
  422. boff = boff >> 1;
  423. } else if (pfl->width == 4) {
  424. boff = boff >> 2;
  425. }
  426. /* Only the least-significant 11 bits are used in most cases. */
  427. boff &= 0x7FF;
  428. switch (pfl->wcycle) {
  429. case 0:
  430. /* Set the device in I/O access mode if required */
  431. if (pfl->rom_mode) {
  432. pfl->rom_mode = false;
  433. memory_region_rom_device_set_romd(&pfl->orig_mem, false);
  434. }
  435. pfl->read_counter = 0;
  436. /* We're in read mode */
  437. check_unlock0:
  438. if (boff == 0x55 && cmd == 0x98) {
  439. /* Enter CFI query mode */
  440. pfl->wcycle = WCYCLE_CFI;
  441. pfl->cmd = 0x98;
  442. return;
  443. }
  444. /* Handle erase resume in erase suspend mode, otherwise reset. */
  445. if (cmd == 0x30) { /* Erase Resume */
  446. if (pflash_erase_suspend_mode(pfl)) {
  447. /* Resume the erase. */
  448. timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
  449. pfl->erase_time_remaining);
  450. pfl->erase_time_remaining = 0;
  451. pfl->wcycle = 6;
  452. pfl->cmd = 0x30;
  453. set_dq7(pfl, 0x00);
  454. assert_dq3(pfl);
  455. return;
  456. }
  457. goto reset_flash;
  458. }
  459. /* Ignore erase suspend. */
  460. if (cmd == 0xB0) { /* Erase Suspend */
  461. return;
  462. }
  463. if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
  464. trace_pflash_unlock0_failed(pfl->name, boff,
  465. cmd, pfl->unlock_addr0);
  466. goto reset_flash;
  467. }
  468. trace_pflash_write(pfl->name, "unlock sequence started");
  469. break;
  470. case 1:
  471. /* We started an unlock sequence */
  472. check_unlock1:
  473. if (boff != pfl->unlock_addr1 || cmd != 0x55) {
  474. trace_pflash_unlock1_failed(pfl->name, boff, cmd);
  475. goto reset_flash;
  476. }
  477. trace_pflash_write(pfl->name, "unlock sequence done");
  478. break;
  479. case 2:
  480. /* We finished an unlock sequence */
  481. if (!pfl->bypass && boff != pfl->unlock_addr0) {
  482. trace_pflash_write_failed(pfl->name, boff, cmd);
  483. goto reset_flash;
  484. }
  485. switch (cmd) {
  486. case 0x20:
  487. pfl->bypass = 1;
  488. goto do_bypass;
  489. case 0x80: /* Erase */
  490. case 0x90: /* Autoselect */
  491. case 0xA0: /* Program */
  492. pfl->cmd = cmd;
  493. trace_pflash_write_start(pfl->name, cmd);
  494. break;
  495. default:
  496. trace_pflash_write_unknown(pfl->name, cmd);
  497. goto reset_flash;
  498. }
  499. break;
  500. case 3:
  501. switch (pfl->cmd) {
  502. case 0x80: /* Erase */
  503. /* We need another unlock sequence */
  504. goto check_unlock0;
  505. case 0xA0: /* Program */
  506. if (pflash_erase_suspend_mode(pfl) &&
  507. pflash_sector_is_erasing(pfl, offset)) {
  508. /* Ignore writes to erasing sectors. */
  509. if (pfl->bypass) {
  510. goto do_bypass;
  511. }
  512. goto reset_flash;
  513. }
  514. trace_pflash_data_write(pfl->name, offset, width, value);
  515. if (!pfl->ro) {
  516. p = (uint8_t *)pfl->storage + offset;
  517. if (pfl->be) {
  518. uint64_t current = ldn_be_p(p, width);
  519. stn_be_p(p, width, current & value);
  520. } else {
  521. uint64_t current = ldn_le_p(p, width);
  522. stn_le_p(p, width, current & value);
  523. }
  524. pflash_update(pfl, offset, width);
  525. }
  526. /*
  527. * While programming, status bit DQ7 should hold the opposite
  528. * value from how it was programmed.
  529. */
  530. set_dq7(pfl, ~value);
  531. /* Let's pretend write is immediate */
  532. if (pfl->bypass)
  533. goto do_bypass;
  534. goto reset_flash;
  535. case 0x90: /* Autoselect */
  536. if (pfl->bypass && cmd == 0x00) {
  537. /* Unlock bypass reset */
  538. goto reset_flash;
  539. }
  540. /*
  541. * We can enter CFI query mode from autoselect mode, but we must
  542. * return to autoselect mode after a reset.
  543. */
  544. if (boff == 0x55 && cmd == 0x98) {
  545. /* Enter autoselect CFI query mode */
  546. pfl->wcycle = WCYCLE_AUTOSELECT_CFI;
  547. pfl->cmd = 0x98;
  548. return;
  549. }
  550. /* fall through */
  551. default:
  552. trace_pflash_write_invalid(pfl->name, pfl->cmd);
  553. goto reset_flash;
  554. }
  555. case 4:
  556. switch (pfl->cmd) {
  557. case 0xA0: /* Program */
  558. /* Ignore writes while flash data write is occurring */
  559. /* As we suppose write is immediate, this should never happen */
  560. return;
  561. case 0x80: /* Erase */
  562. goto check_unlock1;
  563. default:
  564. /* Should never happen */
  565. trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 5);
  566. goto reset_flash;
  567. }
  568. break;
  569. case 5:
  570. if (pflash_erase_suspend_mode(pfl)) {
  571. /* Erasing is not supported in erase suspend mode. */
  572. goto reset_flash;
  573. }
  574. switch (cmd) {
  575. case 0x10: /* Chip Erase */
  576. if (boff != pfl->unlock_addr0) {
  577. trace_pflash_chip_erase_invalid(pfl->name, offset);
  578. goto reset_flash;
  579. }
  580. /* Chip erase */
  581. trace_pflash_chip_erase_start(pfl->name);
  582. if (!pfl->ro) {
  583. memset(pfl->storage, 0xff, pfl->chip_len);
  584. pflash_update(pfl, 0, pfl->chip_len);
  585. }
  586. set_dq7(pfl, 0x00);
  587. /* Wait the time specified at CFI address 0x22. */
  588. timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
  589. (1ULL << pfl->cfi_table[0x22]) * SCALE_MS);
  590. break;
  591. case 0x30: /* Sector erase */
  592. pflash_sector_erase(pfl, offset);
  593. break;
  594. default:
  595. trace_pflash_write_invalid_command(pfl->name, cmd);
  596. goto reset_flash;
  597. }
  598. pfl->cmd = cmd;
  599. break;
  600. case 6:
  601. switch (pfl->cmd) {
  602. case 0x10: /* Chip Erase */
  603. /* Ignore writes during chip erase */
  604. return;
  605. case 0x30: /* Sector erase */
  606. if (cmd == 0xB0) {
  607. /*
  608. * If erase suspend happens during the erase timeout (so DQ3 is
  609. * 0), then the device suspends erasing immediately. Set the
  610. * remaining time to be the total time to erase. Otherwise,
  611. * there is a maximum amount of time it can take to enter
  612. * suspend mode. Let's ignore that and suspend immediately and
  613. * set the remaining time to the actual time remaining on the
  614. * timer.
  615. */
  616. if ((pfl->status & 0x08) == 0) {
  617. pfl->erase_time_remaining = pflash_erase_time(pfl);
  618. } else {
  619. int64_t delta = timer_expire_time_ns(&pfl->timer) -
  620. qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  621. /* Make sure we have a positive time remaining. */
  622. pfl->erase_time_remaining = delta <= 0 ? 1 : delta;
  623. }
  624. reset_dq3(pfl);
  625. timer_del(&pfl->timer);
  626. pflash_reset_state_machine(pfl);
  627. return;
  628. }
  629. /*
  630. * If DQ3 is 0, additional sector erase commands can be
  631. * written and anything else (other than an erase suspend) resets
  632. * the device.
  633. */
  634. if ((pfl->status & 0x08) == 0) {
  635. if (cmd == 0x30) {
  636. pflash_sector_erase(pfl, offset);
  637. } else {
  638. goto reset_flash;
  639. }
  640. }
  641. /* Ignore writes during the actual erase. */
  642. return;
  643. default:
  644. /* Should never happen */
  645. trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 6);
  646. goto reset_flash;
  647. }
  648. break;
  649. /* Special values for CFI queries */
  650. case WCYCLE_CFI:
  651. case WCYCLE_AUTOSELECT_CFI:
  652. trace_pflash_write(pfl->name, "invalid write in CFI query mode");
  653. goto reset_flash;
  654. default:
  655. /* Should never happen */
  656. trace_pflash_write(pfl->name, "invalid write state (wc 7)");
  657. goto reset_flash;
  658. }
  659. pfl->wcycle++;
  660. return;
  661. /* Reset flash */
  662. reset_flash:
  663. pfl->bypass = 0;
  664. pflash_reset_state_machine(pfl);
  665. return;
  666. do_bypass:
  667. pfl->wcycle = 2;
  668. pfl->cmd = 0;
  669. }
  670. static const MemoryRegionOps pflash_cfi02_ops = {
  671. .read = pflash_read,
  672. .write = pflash_write,
  673. .valid.min_access_size = 1,
  674. .valid.max_access_size = 4,
  675. .endianness = DEVICE_NATIVE_ENDIAN,
  676. };
  677. static void pflash_cfi02_fill_cfi_table(PFlashCFI02 *pfl, int nb_regions)
  678. {
  679. /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
  680. const uint16_t pri_ofs = 0x40;
  681. /* Standard "QRY" string */
  682. pfl->cfi_table[0x10] = 'Q';
  683. pfl->cfi_table[0x11] = 'R';
  684. pfl->cfi_table[0x12] = 'Y';
  685. /* Command set (AMD/Fujitsu) */
  686. pfl->cfi_table[0x13] = 0x02;
  687. pfl->cfi_table[0x14] = 0x00;
  688. /* Primary extended table address */
  689. pfl->cfi_table[0x15] = pri_ofs;
  690. pfl->cfi_table[0x16] = pri_ofs >> 8;
  691. /* Alternate command set (none) */
  692. pfl->cfi_table[0x17] = 0x00;
  693. pfl->cfi_table[0x18] = 0x00;
  694. /* Alternate extended table (none) */
  695. pfl->cfi_table[0x19] = 0x00;
  696. pfl->cfi_table[0x1A] = 0x00;
  697. /* Vcc min */
  698. pfl->cfi_table[0x1B] = 0x27;
  699. /* Vcc max */
  700. pfl->cfi_table[0x1C] = 0x36;
  701. /* Vpp min (no Vpp pin) */
  702. pfl->cfi_table[0x1D] = 0x00;
  703. /* Vpp max (no Vpp pin) */
  704. pfl->cfi_table[0x1E] = 0x00;
  705. /* Timeout per single byte/word write (128 ms) */
  706. pfl->cfi_table[0x1F] = 0x07;
  707. /* Timeout for min size buffer write (NA) */
  708. pfl->cfi_table[0x20] = 0x00;
  709. /* Typical timeout for block erase (512 ms) */
  710. pfl->cfi_table[0x21] = 0x09;
  711. /* Typical timeout for full chip erase (4096 ms) */
  712. pfl->cfi_table[0x22] = 0x0C;
  713. /* Reserved */
  714. pfl->cfi_table[0x23] = 0x01;
  715. /* Max timeout for buffer write (NA) */
  716. pfl->cfi_table[0x24] = 0x00;
  717. /* Max timeout for block erase */
  718. pfl->cfi_table[0x25] = 0x0A;
  719. /* Max timeout for chip erase */
  720. pfl->cfi_table[0x26] = 0x0D;
  721. /* Device size */
  722. pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
  723. /* Flash device interface (8 & 16 bits) */
  724. pfl->cfi_table[0x28] = 0x02;
  725. pfl->cfi_table[0x29] = 0x00;
  726. /* Max number of bytes in multi-bytes write */
  727. /*
  728. * XXX: disable buffered write as it's not supported
  729. * pfl->cfi_table[0x2A] = 0x05;
  730. */
  731. pfl->cfi_table[0x2A] = 0x00;
  732. pfl->cfi_table[0x2B] = 0x00;
  733. /* Number of erase block regions */
  734. pfl->cfi_table[0x2c] = nb_regions;
  735. /* Erase block regions */
  736. for (int i = 0; i < nb_regions; ++i) {
  737. uint32_t sector_len_per_device = pfl->sector_len[i];
  738. pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
  739. pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
  740. pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
  741. pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
  742. }
  743. assert(0x2c + 4 * nb_regions < pri_ofs);
  744. /* Extended */
  745. pfl->cfi_table[0x00 + pri_ofs] = 'P';
  746. pfl->cfi_table[0x01 + pri_ofs] = 'R';
  747. pfl->cfi_table[0x02 + pri_ofs] = 'I';
  748. /* Extended version 1.0 */
  749. pfl->cfi_table[0x03 + pri_ofs] = '1';
  750. pfl->cfi_table[0x04 + pri_ofs] = '0';
  751. /* Address sensitive unlock required. */
  752. pfl->cfi_table[0x05 + pri_ofs] = 0x00;
  753. /* Erase suspend to read/write. */
  754. pfl->cfi_table[0x06 + pri_ofs] = 0x02;
  755. /* Sector protect not supported. */
  756. pfl->cfi_table[0x07 + pri_ofs] = 0x00;
  757. /* Temporary sector unprotect not supported. */
  758. pfl->cfi_table[0x08 + pri_ofs] = 0x00;
  759. /* Sector protect/unprotect scheme. */
  760. pfl->cfi_table[0x09 + pri_ofs] = 0x00;
  761. /* Simultaneous operation not supported. */
  762. pfl->cfi_table[0x0a + pri_ofs] = 0x00;
  763. /* Burst mode not supported. */
  764. pfl->cfi_table[0x0b + pri_ofs] = 0x00;
  765. /* Page mode not supported. */
  766. pfl->cfi_table[0x0c + pri_ofs] = 0x00;
  767. assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
  768. }
  769. static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
  770. {
  771. ERRP_GUARD();
  772. PFlashCFI02 *pfl = PFLASH_CFI02(dev);
  773. int ret;
  774. if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) {
  775. error_setg(errp, "attribute \"sector-length\" not specified or zero.");
  776. return;
  777. }
  778. if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) {
  779. error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
  780. return;
  781. }
  782. if (pfl->name == NULL) {
  783. error_setg(errp, "attribute \"name\" not specified.");
  784. return;
  785. }
  786. int nb_regions;
  787. pfl->chip_len = 0;
  788. pfl->total_sectors = 0;
  789. for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) {
  790. if (pfl->nb_blocs[nb_regions] == 0) {
  791. break;
  792. }
  793. pfl->total_sectors += pfl->nb_blocs[nb_regions];
  794. uint64_t sector_len_per_device = pfl->sector_len[nb_regions];
  795. /*
  796. * The size of each flash sector must be a power of 2 and it must be
  797. * aligned at the same power of 2.
  798. */
  799. if (sector_len_per_device & 0xff ||
  800. sector_len_per_device >= (1 << 24) ||
  801. !is_power_of_2(sector_len_per_device))
  802. {
  803. error_setg(errp, "unsupported configuration: "
  804. "sector length[%d] per device = %" PRIx64 ".",
  805. nb_regions, sector_len_per_device);
  806. return;
  807. }
  808. if (pfl->chip_len & (sector_len_per_device - 1)) {
  809. error_setg(errp, "unsupported configuration: "
  810. "flash region %d not correctly aligned.",
  811. nb_regions);
  812. return;
  813. }
  814. pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] *
  815. pfl->nb_blocs[nb_regions];
  816. }
  817. uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs *
  818. pfl->uniform_sector_len;
  819. if (nb_regions == 0) {
  820. nb_regions = 1;
  821. pfl->nb_blocs[0] = pfl->uniform_nb_blocs;
  822. pfl->sector_len[0] = pfl->uniform_sector_len;
  823. pfl->chip_len = uniform_len;
  824. pfl->total_sectors = pfl->uniform_nb_blocs;
  825. } else if (uniform_len != 0 && uniform_len != pfl->chip_len) {
  826. error_setg(errp, "\"num-blocks\"*\"sector-length\" "
  827. "different from \"num-blocks0\"*\'sector-length0\" + ... + "
  828. "\"num-blocks3\"*\"sector-length3\"");
  829. return;
  830. }
  831. memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl),
  832. &pflash_cfi02_ops, pfl, pfl->name,
  833. pfl->chip_len, errp);
  834. if (*errp) {
  835. return;
  836. }
  837. pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
  838. if (pfl->blk) {
  839. uint64_t perm;
  840. pfl->ro = !blk_supports_write_perm(pfl->blk);
  841. perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
  842. ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
  843. if (ret < 0) {
  844. return;
  845. }
  846. } else {
  847. pfl->ro = 0;
  848. }
  849. if (pfl->blk) {
  850. if (!blk_check_size_and_read_all(pfl->blk, dev, pfl->storage,
  851. pfl->chip_len, errp)) {
  852. vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
  853. return;
  854. }
  855. }
  856. /* Only 11 bits are used in the comparison. */
  857. pfl->unlock_addr0 &= 0x7FF;
  858. pfl->unlock_addr1 &= 0x7FF;
  859. /* Allocate memory for a bitmap for sectors being erased. */
  860. pfl->sector_erase_map = bitmap_new(pfl->total_sectors);
  861. pfl->rom_mode = true;
  862. if (pfl->mappings > 1) {
  863. pflash_setup_mappings(pfl);
  864. sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
  865. } else {
  866. sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->orig_mem);
  867. }
  868. timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
  869. pfl->status = 0;
  870. pflash_cfi02_fill_cfi_table(pfl, nb_regions);
  871. }
  872. static void pflash_cfi02_reset(DeviceState *dev)
  873. {
  874. PFlashCFI02 *pfl = PFLASH_CFI02(dev);
  875. pflash_reset_state_machine(pfl);
  876. }
  877. static Property pflash_cfi02_properties[] = {
  878. DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
  879. DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0),
  880. DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0),
  881. DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0),
  882. DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0),
  883. DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0),
  884. DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0),
  885. DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0),
  886. DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0),
  887. DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0),
  888. DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0),
  889. DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
  890. DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
  891. DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
  892. DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
  893. DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
  894. DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
  895. DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
  896. DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
  897. DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
  898. DEFINE_PROP_STRING("name", PFlashCFI02, name),
  899. DEFINE_PROP_END_OF_LIST(),
  900. };
  901. static void pflash_cfi02_unrealize(DeviceState *dev)
  902. {
  903. PFlashCFI02 *pfl = PFLASH_CFI02(dev);
  904. timer_del(&pfl->timer);
  905. g_free(pfl->sector_erase_map);
  906. }
  907. static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
  908. {
  909. DeviceClass *dc = DEVICE_CLASS(klass);
  910. dc->realize = pflash_cfi02_realize;
  911. device_class_set_legacy_reset(dc, pflash_cfi02_reset);
  912. dc->unrealize = pflash_cfi02_unrealize;
  913. device_class_set_props(dc, pflash_cfi02_properties);
  914. set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
  915. }
  916. static const TypeInfo pflash_cfi02_info = {
  917. .name = TYPE_PFLASH_CFI02,
  918. .parent = TYPE_SYS_BUS_DEVICE,
  919. .instance_size = sizeof(PFlashCFI02),
  920. .class_init = pflash_cfi02_class_init,
  921. };
  922. static void pflash_cfi02_register_types(void)
  923. {
  924. type_register_static(&pflash_cfi02_info);
  925. }
  926. type_init(pflash_cfi02_register_types)
  927. PFlashCFI02 *pflash_cfi02_register(hwaddr base,
  928. const char *name,
  929. hwaddr size,
  930. BlockBackend *blk,
  931. uint32_t sector_len,
  932. int nb_mappings, int width,
  933. uint16_t id0, uint16_t id1,
  934. uint16_t id2, uint16_t id3,
  935. uint16_t unlock_addr0,
  936. uint16_t unlock_addr1,
  937. int be)
  938. {
  939. DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02);
  940. if (blk) {
  941. qdev_prop_set_drive(dev, "drive", blk);
  942. }
  943. assert(QEMU_IS_ALIGNED(size, sector_len));
  944. qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
  945. qdev_prop_set_uint32(dev, "sector-length", sector_len);
  946. qdev_prop_set_uint8(dev, "width", width);
  947. qdev_prop_set_uint8(dev, "mappings", nb_mappings);
  948. qdev_prop_set_uint8(dev, "big-endian", !!be);
  949. qdev_prop_set_uint16(dev, "id0", id0);
  950. qdev_prop_set_uint16(dev, "id1", id1);
  951. qdev_prop_set_uint16(dev, "id2", id2);
  952. qdev_prop_set_uint16(dev, "id3", id3);
  953. qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
  954. qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
  955. qdev_prop_set_string(dev, "name", name);
  956. sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
  957. sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
  958. return PFLASH_CFI02(dev);
  959. }