qtest.c 18 KB

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  1. /*
  2. * Test Server
  3. *
  4. * Copyright IBM, Corp. 2011
  5. *
  6. * Authors:
  7. * Anthony Liguori <aliguori@us.ibm.com>
  8. *
  9. * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10. * See the COPYING file in the top-level directory.
  11. *
  12. */
  13. #include "qemu/osdep.h"
  14. #include "sysemu/qtest.h"
  15. #include "hw/qdev.h"
  16. #include "sysemu/char.h"
  17. #include "exec/ioport.h"
  18. #include "exec/memory.h"
  19. #include "hw/irq.h"
  20. #include "sysemu/accel.h"
  21. #include "sysemu/sysemu.h"
  22. #include "sysemu/cpus.h"
  23. #include "qemu/config-file.h"
  24. #include "qemu/option.h"
  25. #include "qemu/error-report.h"
  26. #define MAX_IRQ 256
  27. bool qtest_allowed;
  28. static DeviceState *irq_intercept_dev;
  29. static FILE *qtest_log_fp;
  30. static CharDriverState *qtest_chr;
  31. static GString *inbuf;
  32. static int irq_levels[MAX_IRQ];
  33. static qemu_timeval start_time;
  34. static bool qtest_opened;
  35. #define FMT_timeval "%ld.%06ld"
  36. /**
  37. * QTest Protocol
  38. *
  39. * Line based protocol, request/response based. Server can send async messages
  40. * so clients should always handle many async messages before the response
  41. * comes in.
  42. *
  43. * Valid requests
  44. *
  45. * Clock management:
  46. *
  47. * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
  48. * let you adjust the value of the clock (monotonically). All the commands
  49. * return the current value of the clock in nanoseconds.
  50. *
  51. * > clock_step
  52. * < OK VALUE
  53. *
  54. * Advance the clock to the next deadline. Useful when waiting for
  55. * asynchronous events.
  56. *
  57. * > clock_step NS
  58. * < OK VALUE
  59. *
  60. * Advance the clock by NS nanoseconds.
  61. *
  62. * > clock_set NS
  63. * < OK VALUE
  64. *
  65. * Advance the clock to NS nanoseconds (do nothing if it's already past).
  66. *
  67. * PIO and memory access:
  68. *
  69. * > outb ADDR VALUE
  70. * < OK
  71. *
  72. * > outw ADDR VALUE
  73. * < OK
  74. *
  75. * > outl ADDR VALUE
  76. * < OK
  77. *
  78. * > inb ADDR
  79. * < OK VALUE
  80. *
  81. * > inw ADDR
  82. * < OK VALUE
  83. *
  84. * > inl ADDR
  85. * < OK VALUE
  86. *
  87. * > writeb ADDR VALUE
  88. * < OK
  89. *
  90. * > writew ADDR VALUE
  91. * < OK
  92. *
  93. * > writel ADDR VALUE
  94. * < OK
  95. *
  96. * > writeq ADDR VALUE
  97. * < OK
  98. *
  99. * > readb ADDR
  100. * < OK VALUE
  101. *
  102. * > readw ADDR
  103. * < OK VALUE
  104. *
  105. * > readl ADDR
  106. * < OK VALUE
  107. *
  108. * > readq ADDR
  109. * < OK VALUE
  110. *
  111. * > read ADDR SIZE
  112. * < OK DATA
  113. *
  114. * > write ADDR SIZE DATA
  115. * < OK
  116. *
  117. * > b64read ADDR SIZE
  118. * < OK B64_DATA
  119. *
  120. * > b64write ADDR SIZE B64_DATA
  121. * < OK
  122. *
  123. * > memset ADDR SIZE VALUE
  124. * < OK
  125. *
  126. * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
  127. *
  128. * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
  129. * than the expected size, the value will be zero filled at the end of the data
  130. * sequence.
  131. *
  132. * B64_DATA is an arbitrarily long base64 encoded string.
  133. * If the sizes do not match, the data will be truncated.
  134. *
  135. * IRQ management:
  136. *
  137. * > irq_intercept_in QOM-PATH
  138. * < OK
  139. *
  140. * > irq_intercept_out QOM-PATH
  141. * < OK
  142. *
  143. * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
  144. * QOM-PATH. When the pin is triggered, one of the following async messages
  145. * will be printed to the qtest stream:
  146. *
  147. * IRQ raise NUM
  148. * IRQ lower NUM
  149. *
  150. * where NUM is an IRQ number. For the PC, interrupts can be intercepted
  151. * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
  152. * NUM=0 even though it is remapped to GSI 2).
  153. */
  154. static int hex2nib(char ch)
  155. {
  156. if (ch >= '0' && ch <= '9') {
  157. return ch - '0';
  158. } else if (ch >= 'a' && ch <= 'f') {
  159. return 10 + (ch - 'a');
  160. } else if (ch >= 'A' && ch <= 'F') {
  161. return 10 + (ch - 'A');
  162. } else {
  163. return -1;
  164. }
  165. }
  166. static void qtest_get_time(qemu_timeval *tv)
  167. {
  168. qemu_gettimeofday(tv);
  169. tv->tv_sec -= start_time.tv_sec;
  170. tv->tv_usec -= start_time.tv_usec;
  171. if (tv->tv_usec < 0) {
  172. tv->tv_usec += 1000000;
  173. tv->tv_sec -= 1;
  174. }
  175. }
  176. static void qtest_send_prefix(CharDriverState *chr)
  177. {
  178. qemu_timeval tv;
  179. if (!qtest_log_fp || !qtest_opened) {
  180. return;
  181. }
  182. qtest_get_time(&tv);
  183. fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
  184. (long) tv.tv_sec, (long) tv.tv_usec);
  185. }
  186. static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt, ...)
  187. {
  188. va_list ap;
  189. if (!qtest_log_fp || !qtest_opened) {
  190. return;
  191. }
  192. qtest_send_prefix(NULL);
  193. va_start(ap, fmt);
  194. vfprintf(qtest_log_fp, fmt, ap);
  195. va_end(ap);
  196. }
  197. static void do_qtest_send(CharDriverState *chr, const char *str, size_t len)
  198. {
  199. qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
  200. if (qtest_log_fp && qtest_opened) {
  201. fprintf(qtest_log_fp, "%s", str);
  202. }
  203. }
  204. static void qtest_send(CharDriverState *chr, const char *str)
  205. {
  206. do_qtest_send(chr, str, strlen(str));
  207. }
  208. static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharDriverState *chr,
  209. const char *fmt, ...)
  210. {
  211. va_list ap;
  212. gchar *buffer;
  213. va_start(ap, fmt);
  214. buffer = g_strdup_vprintf(fmt, ap);
  215. qtest_send(chr, buffer);
  216. va_end(ap);
  217. }
  218. static void qtest_irq_handler(void *opaque, int n, int level)
  219. {
  220. qemu_irq old_irq = *(qemu_irq *)opaque;
  221. qemu_set_irq(old_irq, level);
  222. if (irq_levels[n] != level) {
  223. CharDriverState *chr = qtest_chr;
  224. irq_levels[n] = level;
  225. qtest_send_prefix(chr);
  226. qtest_sendf(chr, "IRQ %s %d\n",
  227. level ? "raise" : "lower", n);
  228. }
  229. }
  230. static void qtest_process_command(CharDriverState *chr, gchar **words)
  231. {
  232. const gchar *command;
  233. g_assert(words);
  234. command = words[0];
  235. if (qtest_log_fp) {
  236. qemu_timeval tv;
  237. int i;
  238. qtest_get_time(&tv);
  239. fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
  240. (long) tv.tv_sec, (long) tv.tv_usec);
  241. for (i = 0; words[i]; i++) {
  242. fprintf(qtest_log_fp, " %s", words[i]);
  243. }
  244. fprintf(qtest_log_fp, "\n");
  245. }
  246. g_assert(command);
  247. if (strcmp(words[0], "irq_intercept_out") == 0
  248. || strcmp(words[0], "irq_intercept_in") == 0) {
  249. DeviceState *dev;
  250. NamedGPIOList *ngl;
  251. g_assert(words[1]);
  252. dev = DEVICE(object_resolve_path(words[1], NULL));
  253. if (!dev) {
  254. qtest_send_prefix(chr);
  255. qtest_send(chr, "FAIL Unknown device\n");
  256. return;
  257. }
  258. if (irq_intercept_dev) {
  259. qtest_send_prefix(chr);
  260. if (irq_intercept_dev != dev) {
  261. qtest_send(chr, "FAIL IRQ intercept already enabled\n");
  262. } else {
  263. qtest_send(chr, "OK\n");
  264. }
  265. return;
  266. }
  267. QLIST_FOREACH(ngl, &dev->gpios, node) {
  268. /* We don't support intercept of named GPIOs yet */
  269. if (ngl->name) {
  270. continue;
  271. }
  272. if (words[0][14] == 'o') {
  273. int i;
  274. for (i = 0; i < ngl->num_out; ++i) {
  275. qemu_irq *disconnected = g_new0(qemu_irq, 1);
  276. qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
  277. disconnected, i);
  278. *disconnected = qdev_intercept_gpio_out(dev, icpt,
  279. ngl->name, i);
  280. }
  281. } else {
  282. qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
  283. ngl->num_in);
  284. }
  285. }
  286. irq_intercept_dev = dev;
  287. qtest_send_prefix(chr);
  288. qtest_send(chr, "OK\n");
  289. } else if (strcmp(words[0], "outb") == 0 ||
  290. strcmp(words[0], "outw") == 0 ||
  291. strcmp(words[0], "outl") == 0) {
  292. uint16_t addr;
  293. uint32_t value;
  294. g_assert(words[1] && words[2]);
  295. addr = strtoul(words[1], NULL, 0);
  296. value = strtoul(words[2], NULL, 0);
  297. if (words[0][3] == 'b') {
  298. cpu_outb(addr, value);
  299. } else if (words[0][3] == 'w') {
  300. cpu_outw(addr, value);
  301. } else if (words[0][3] == 'l') {
  302. cpu_outl(addr, value);
  303. }
  304. qtest_send_prefix(chr);
  305. qtest_send(chr, "OK\n");
  306. } else if (strcmp(words[0], "inb") == 0 ||
  307. strcmp(words[0], "inw") == 0 ||
  308. strcmp(words[0], "inl") == 0) {
  309. uint16_t addr;
  310. uint32_t value = -1U;
  311. g_assert(words[1]);
  312. addr = strtoul(words[1], NULL, 0);
  313. if (words[0][2] == 'b') {
  314. value = cpu_inb(addr);
  315. } else if (words[0][2] == 'w') {
  316. value = cpu_inw(addr);
  317. } else if (words[0][2] == 'l') {
  318. value = cpu_inl(addr);
  319. }
  320. qtest_send_prefix(chr);
  321. qtest_sendf(chr, "OK 0x%04x\n", value);
  322. } else if (strcmp(words[0], "writeb") == 0 ||
  323. strcmp(words[0], "writew") == 0 ||
  324. strcmp(words[0], "writel") == 0 ||
  325. strcmp(words[0], "writeq") == 0) {
  326. uint64_t addr;
  327. uint64_t value;
  328. g_assert(words[1] && words[2]);
  329. addr = strtoull(words[1], NULL, 0);
  330. value = strtoull(words[2], NULL, 0);
  331. if (words[0][5] == 'b') {
  332. uint8_t data = value;
  333. cpu_physical_memory_write(addr, &data, 1);
  334. } else if (words[0][5] == 'w') {
  335. uint16_t data = value;
  336. tswap16s(&data);
  337. cpu_physical_memory_write(addr, &data, 2);
  338. } else if (words[0][5] == 'l') {
  339. uint32_t data = value;
  340. tswap32s(&data);
  341. cpu_physical_memory_write(addr, &data, 4);
  342. } else if (words[0][5] == 'q') {
  343. uint64_t data = value;
  344. tswap64s(&data);
  345. cpu_physical_memory_write(addr, &data, 8);
  346. }
  347. qtest_send_prefix(chr);
  348. qtest_send(chr, "OK\n");
  349. } else if (strcmp(words[0], "readb") == 0 ||
  350. strcmp(words[0], "readw") == 0 ||
  351. strcmp(words[0], "readl") == 0 ||
  352. strcmp(words[0], "readq") == 0) {
  353. uint64_t addr;
  354. uint64_t value = UINT64_C(-1);
  355. g_assert(words[1]);
  356. addr = strtoull(words[1], NULL, 0);
  357. if (words[0][4] == 'b') {
  358. uint8_t data;
  359. cpu_physical_memory_read(addr, &data, 1);
  360. value = data;
  361. } else if (words[0][4] == 'w') {
  362. uint16_t data;
  363. cpu_physical_memory_read(addr, &data, 2);
  364. value = tswap16(data);
  365. } else if (words[0][4] == 'l') {
  366. uint32_t data;
  367. cpu_physical_memory_read(addr, &data, 4);
  368. value = tswap32(data);
  369. } else if (words[0][4] == 'q') {
  370. cpu_physical_memory_read(addr, &value, 8);
  371. tswap64s(&value);
  372. }
  373. qtest_send_prefix(chr);
  374. qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
  375. } else if (strcmp(words[0], "read") == 0) {
  376. uint64_t addr, len, i;
  377. uint8_t *data;
  378. char *enc;
  379. g_assert(words[1] && words[2]);
  380. addr = strtoull(words[1], NULL, 0);
  381. len = strtoull(words[2], NULL, 0);
  382. data = g_malloc(len);
  383. cpu_physical_memory_read(addr, data, len);
  384. enc = g_malloc(2 * len + 1);
  385. for (i = 0; i < len; i++) {
  386. sprintf(&enc[i * 2], "%02x", data[i]);
  387. }
  388. qtest_send_prefix(chr);
  389. qtest_sendf(chr, "OK 0x%s\n", enc);
  390. g_free(data);
  391. g_free(enc);
  392. } else if (strcmp(words[0], "b64read") == 0) {
  393. uint64_t addr, len;
  394. uint8_t *data;
  395. gchar *b64_data;
  396. g_assert(words[1] && words[2]);
  397. addr = strtoull(words[1], NULL, 0);
  398. len = strtoull(words[2], NULL, 0);
  399. data = g_malloc(len);
  400. cpu_physical_memory_read(addr, data, len);
  401. b64_data = g_base64_encode(data, len);
  402. qtest_send_prefix(chr);
  403. qtest_sendf(chr, "OK %s\n", b64_data);
  404. g_free(data);
  405. g_free(b64_data);
  406. } else if (strcmp(words[0], "write") == 0) {
  407. uint64_t addr, len, i;
  408. uint8_t *data;
  409. size_t data_len;
  410. g_assert(words[1] && words[2] && words[3]);
  411. addr = strtoull(words[1], NULL, 0);
  412. len = strtoull(words[2], NULL, 0);
  413. data_len = strlen(words[3]);
  414. if (data_len < 3) {
  415. qtest_send(chr, "ERR invalid argument size\n");
  416. return;
  417. }
  418. data = g_malloc(len);
  419. for (i = 0; i < len; i++) {
  420. if ((i * 2 + 4) <= data_len) {
  421. data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
  422. data[i] |= hex2nib(words[3][i * 2 + 3]);
  423. } else {
  424. data[i] = 0;
  425. }
  426. }
  427. cpu_physical_memory_write(addr, data, len);
  428. g_free(data);
  429. qtest_send_prefix(chr);
  430. qtest_send(chr, "OK\n");
  431. } else if (strcmp(words[0], "memset") == 0) {
  432. uint64_t addr, len;
  433. uint8_t *data;
  434. uint8_t pattern;
  435. g_assert(words[1] && words[2] && words[3]);
  436. addr = strtoull(words[1], NULL, 0);
  437. len = strtoull(words[2], NULL, 0);
  438. pattern = strtoull(words[3], NULL, 0);
  439. data = g_malloc(len);
  440. memset(data, pattern, len);
  441. cpu_physical_memory_write(addr, data, len);
  442. g_free(data);
  443. qtest_send_prefix(chr);
  444. qtest_send(chr, "OK\n");
  445. } else if (strcmp(words[0], "b64write") == 0) {
  446. uint64_t addr, len;
  447. uint8_t *data;
  448. size_t data_len;
  449. gsize out_len;
  450. g_assert(words[1] && words[2] && words[3]);
  451. addr = strtoull(words[1], NULL, 0);
  452. len = strtoull(words[2], NULL, 0);
  453. data_len = strlen(words[3]);
  454. if (data_len < 3) {
  455. qtest_send(chr, "ERR invalid argument size\n");
  456. return;
  457. }
  458. data = g_base64_decode_inplace(words[3], &out_len);
  459. if (out_len != len) {
  460. qtest_log_send("b64write: data length mismatch (told %"PRIu64", "
  461. "found %zu)\n",
  462. len, out_len);
  463. out_len = MIN(out_len, len);
  464. }
  465. cpu_physical_memory_write(addr, data, out_len);
  466. qtest_send_prefix(chr);
  467. qtest_send(chr, "OK\n");
  468. } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
  469. int64_t ns;
  470. if (words[1]) {
  471. ns = strtoll(words[1], NULL, 0);
  472. } else {
  473. ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
  474. }
  475. qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
  476. qtest_send_prefix(chr);
  477. qtest_sendf(chr, "OK %"PRIi64"\n",
  478. (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
  479. } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
  480. int64_t ns;
  481. g_assert(words[1]);
  482. ns = strtoll(words[1], NULL, 0);
  483. qtest_clock_warp(ns);
  484. qtest_send_prefix(chr);
  485. qtest_sendf(chr, "OK %"PRIi64"\n",
  486. (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
  487. } else {
  488. qtest_send_prefix(chr);
  489. qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
  490. }
  491. }
  492. static void qtest_process_inbuf(CharDriverState *chr, GString *inbuf)
  493. {
  494. char *end;
  495. while ((end = strchr(inbuf->str, '\n')) != NULL) {
  496. size_t offset;
  497. GString *cmd;
  498. gchar **words;
  499. offset = end - inbuf->str;
  500. cmd = g_string_new_len(inbuf->str, offset);
  501. g_string_erase(inbuf, 0, offset + 1);
  502. words = g_strsplit(cmd->str, " ", 0);
  503. qtest_process_command(chr, words);
  504. g_strfreev(words);
  505. g_string_free(cmd, TRUE);
  506. }
  507. }
  508. static void qtest_read(void *opaque, const uint8_t *buf, int size)
  509. {
  510. CharDriverState *chr = opaque;
  511. g_string_append_len(inbuf, (const gchar *)buf, size);
  512. qtest_process_inbuf(chr, inbuf);
  513. }
  514. static int qtest_can_read(void *opaque)
  515. {
  516. return 1024;
  517. }
  518. static void qtest_event(void *opaque, int event)
  519. {
  520. int i;
  521. switch (event) {
  522. case CHR_EVENT_OPENED:
  523. /*
  524. * We used to call qemu_system_reset() here, hoping we could
  525. * use the same process for multiple tests that way. Never
  526. * used. Injects an extra reset even when it's not used, and
  527. * that can mess up tests, e.g. -boot once.
  528. */
  529. for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
  530. irq_levels[i] = 0;
  531. }
  532. qemu_gettimeofday(&start_time);
  533. qtest_opened = true;
  534. if (qtest_log_fp) {
  535. fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
  536. (long) start_time.tv_sec, (long) start_time.tv_usec);
  537. }
  538. break;
  539. case CHR_EVENT_CLOSED:
  540. qtest_opened = false;
  541. if (qtest_log_fp) {
  542. qemu_timeval tv;
  543. qtest_get_time(&tv);
  544. fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
  545. (long) tv.tv_sec, (long) tv.tv_usec);
  546. }
  547. break;
  548. default:
  549. break;
  550. }
  551. }
  552. static int qtest_init_accel(MachineState *ms)
  553. {
  554. QemuOpts *opts = qemu_opts_create(qemu_find_opts("icount"), NULL, 0,
  555. &error_abort);
  556. qemu_opt_set(opts, "shift", "0", &error_abort);
  557. configure_icount(opts, &error_abort);
  558. qemu_opts_del(opts);
  559. return 0;
  560. }
  561. void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
  562. {
  563. CharDriverState *chr;
  564. chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
  565. if (chr == NULL) {
  566. error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
  567. qtest_chrdev);
  568. return;
  569. }
  570. if (qtest_log) {
  571. if (strcmp(qtest_log, "none") != 0) {
  572. qtest_log_fp = fopen(qtest_log, "w+");
  573. }
  574. } else {
  575. qtest_log_fp = stderr;
  576. }
  577. qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
  578. qemu_chr_fe_set_echo(chr, true);
  579. inbuf = g_string_new("");
  580. qtest_chr = chr;
  581. }
  582. bool qtest_driver(void)
  583. {
  584. return qtest_chr;
  585. }
  586. static void qtest_accel_class_init(ObjectClass *oc, void *data)
  587. {
  588. AccelClass *ac = ACCEL_CLASS(oc);
  589. ac->name = "QTest";
  590. ac->available = qtest_available;
  591. ac->init_machine = qtest_init_accel;
  592. ac->allowed = &qtest_allowed;
  593. }
  594. #define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
  595. static const TypeInfo qtest_accel_type = {
  596. .name = TYPE_QTEST_ACCEL,
  597. .parent = TYPE_ACCEL,
  598. .class_init = qtest_accel_class_init,
  599. };
  600. static void qtest_type_init(void)
  601. {
  602. type_register_static(&qtest_accel_type);
  603. }
  604. type_init(qtest_type_init);