numa.c 16 KB

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  1. /*
  2. * NUMA parameter parsing routines
  3. *
  4. * Copyright (c) 2014 Fujitsu Ltd.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "qemu/osdep.h"
  25. #include "sysemu/numa.h"
  26. #include "exec/cpu-common.h"
  27. #include "qemu/bitmap.h"
  28. #include "qom/cpu.h"
  29. #include "qemu/error-report.h"
  30. #include "include/exec/cpu-common.h" /* for RAM_ADDR_FMT */
  31. #include "qapi-visit.h"
  32. #include "qapi/opts-visitor.h"
  33. #include "qapi/dealloc-visitor.h"
  34. #include "hw/boards.h"
  35. #include "sysemu/hostmem.h"
  36. #include "qmp-commands.h"
  37. #include "hw/mem/pc-dimm.h"
  38. #include "qemu/option.h"
  39. #include "qemu/config-file.h"
  40. QemuOptsList qemu_numa_opts = {
  41. .name = "numa",
  42. .implied_opt_name = "type",
  43. .head = QTAILQ_HEAD_INITIALIZER(qemu_numa_opts.head),
  44. .desc = { { 0 } } /* validated with OptsVisitor */
  45. };
  46. static int have_memdevs = -1;
  47. static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one.
  48. * For all nodes, nodeid < max_numa_nodeid
  49. */
  50. int nb_numa_nodes;
  51. NodeInfo numa_info[MAX_NODES];
  52. void numa_set_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node)
  53. {
  54. struct numa_addr_range *range;
  55. /*
  56. * Memory-less nodes can come here with 0 size in which case,
  57. * there is nothing to do.
  58. */
  59. if (!size) {
  60. return;
  61. }
  62. range = g_malloc0(sizeof(*range));
  63. range->mem_start = addr;
  64. range->mem_end = addr + size - 1;
  65. QLIST_INSERT_HEAD(&numa_info[node].addr, range, entry);
  66. }
  67. void numa_unset_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node)
  68. {
  69. struct numa_addr_range *range, *next;
  70. QLIST_FOREACH_SAFE(range, &numa_info[node].addr, entry, next) {
  71. if (addr == range->mem_start && (addr + size - 1) == range->mem_end) {
  72. QLIST_REMOVE(range, entry);
  73. g_free(range);
  74. return;
  75. }
  76. }
  77. }
  78. static void numa_set_mem_ranges(void)
  79. {
  80. int i;
  81. ram_addr_t mem_start = 0;
  82. /*
  83. * Deduce start address of each node and use it to store
  84. * the address range info in numa_info address range list
  85. */
  86. for (i = 0; i < nb_numa_nodes; i++) {
  87. numa_set_mem_node_id(mem_start, numa_info[i].node_mem, i);
  88. mem_start += numa_info[i].node_mem;
  89. }
  90. }
  91. /*
  92. * Check if @addr falls under NUMA @node.
  93. */
  94. static bool numa_addr_belongs_to_node(ram_addr_t addr, uint32_t node)
  95. {
  96. struct numa_addr_range *range;
  97. QLIST_FOREACH(range, &numa_info[node].addr, entry) {
  98. if (addr >= range->mem_start && addr <= range->mem_end) {
  99. return true;
  100. }
  101. }
  102. return false;
  103. }
  104. /*
  105. * Given an address, return the index of the NUMA node to which the
  106. * address belongs to.
  107. */
  108. uint32_t numa_get_node(ram_addr_t addr, Error **errp)
  109. {
  110. uint32_t i;
  111. /* For non NUMA configurations, check if the addr falls under node 0 */
  112. if (!nb_numa_nodes) {
  113. if (numa_addr_belongs_to_node(addr, 0)) {
  114. return 0;
  115. }
  116. }
  117. for (i = 0; i < nb_numa_nodes; i++) {
  118. if (numa_addr_belongs_to_node(addr, i)) {
  119. return i;
  120. }
  121. }
  122. error_setg(errp, "Address 0x" RAM_ADDR_FMT " doesn't belong to any "
  123. "NUMA node", addr);
  124. return -1;
  125. }
  126. static void numa_node_parse(NumaNodeOptions *node, QemuOpts *opts, Error **errp)
  127. {
  128. uint16_t nodenr;
  129. uint16List *cpus = NULL;
  130. if (node->has_nodeid) {
  131. nodenr = node->nodeid;
  132. } else {
  133. nodenr = nb_numa_nodes;
  134. }
  135. if (nodenr >= MAX_NODES) {
  136. error_setg(errp, "Max number of NUMA nodes reached: %"
  137. PRIu16 "", nodenr);
  138. return;
  139. }
  140. if (numa_info[nodenr].present) {
  141. error_setg(errp, "Duplicate NUMA nodeid: %" PRIu16, nodenr);
  142. return;
  143. }
  144. for (cpus = node->cpus; cpus; cpus = cpus->next) {
  145. if (cpus->value >= max_cpus) {
  146. error_setg(errp,
  147. "CPU index (%" PRIu16 ")"
  148. " should be smaller than maxcpus (%d)",
  149. cpus->value, max_cpus);
  150. return;
  151. }
  152. bitmap_set(numa_info[nodenr].node_cpu, cpus->value, 1);
  153. }
  154. if (node->has_mem && node->has_memdev) {
  155. error_setg(errp, "qemu: cannot specify both mem= and memdev=");
  156. return;
  157. }
  158. if (have_memdevs == -1) {
  159. have_memdevs = node->has_memdev;
  160. }
  161. if (node->has_memdev != have_memdevs) {
  162. error_setg(errp, "qemu: memdev option must be specified for either "
  163. "all or no nodes");
  164. return;
  165. }
  166. if (node->has_mem) {
  167. uint64_t mem_size = node->mem;
  168. const char *mem_str = qemu_opt_get(opts, "mem");
  169. /* Fix up legacy suffix-less format */
  170. if (g_ascii_isdigit(mem_str[strlen(mem_str) - 1])) {
  171. mem_size <<= 20;
  172. }
  173. numa_info[nodenr].node_mem = mem_size;
  174. }
  175. if (node->has_memdev) {
  176. Object *o;
  177. o = object_resolve_path_type(node->memdev, TYPE_MEMORY_BACKEND, NULL);
  178. if (!o) {
  179. error_setg(errp, "memdev=%s is ambiguous", node->memdev);
  180. return;
  181. }
  182. object_ref(o);
  183. numa_info[nodenr].node_mem = object_property_get_int(o, "size", NULL);
  184. numa_info[nodenr].node_memdev = MEMORY_BACKEND(o);
  185. }
  186. numa_info[nodenr].present = true;
  187. max_numa_nodeid = MAX(max_numa_nodeid, nodenr + 1);
  188. }
  189. static int parse_numa(void *opaque, QemuOpts *opts, Error **errp)
  190. {
  191. NumaOptions *object = NULL;
  192. Error *err = NULL;
  193. {
  194. OptsVisitor *ov = opts_visitor_new(opts);
  195. visit_type_NumaOptions(opts_get_visitor(ov), &object, NULL, &err);
  196. opts_visitor_cleanup(ov);
  197. }
  198. if (err) {
  199. goto error;
  200. }
  201. switch (object->type) {
  202. case NUMA_OPTIONS_KIND_NODE:
  203. numa_node_parse(object->u.node, opts, &err);
  204. if (err) {
  205. goto error;
  206. }
  207. nb_numa_nodes++;
  208. break;
  209. default:
  210. abort();
  211. }
  212. return 0;
  213. error:
  214. error_report_err(err);
  215. if (object) {
  216. QapiDeallocVisitor *dv = qapi_dealloc_visitor_new();
  217. visit_type_NumaOptions(qapi_dealloc_get_visitor(dv),
  218. &object, NULL, NULL);
  219. qapi_dealloc_visitor_cleanup(dv);
  220. }
  221. return -1;
  222. }
  223. static char *enumerate_cpus(unsigned long *cpus, int max_cpus)
  224. {
  225. int cpu;
  226. bool first = true;
  227. GString *s = g_string_new(NULL);
  228. for (cpu = find_first_bit(cpus, max_cpus);
  229. cpu < max_cpus;
  230. cpu = find_next_bit(cpus, max_cpus, cpu + 1)) {
  231. g_string_append_printf(s, "%s%d", first ? "" : " ", cpu);
  232. first = false;
  233. }
  234. return g_string_free(s, FALSE);
  235. }
  236. static void validate_numa_cpus(void)
  237. {
  238. int i;
  239. DECLARE_BITMAP(seen_cpus, MAX_CPUMASK_BITS);
  240. bitmap_zero(seen_cpus, MAX_CPUMASK_BITS);
  241. for (i = 0; i < nb_numa_nodes; i++) {
  242. if (bitmap_intersects(seen_cpus, numa_info[i].node_cpu,
  243. MAX_CPUMASK_BITS)) {
  244. bitmap_and(seen_cpus, seen_cpus,
  245. numa_info[i].node_cpu, MAX_CPUMASK_BITS);
  246. error_report("CPU(s) present in multiple NUMA nodes: %s",
  247. enumerate_cpus(seen_cpus, max_cpus));
  248. exit(EXIT_FAILURE);
  249. }
  250. bitmap_or(seen_cpus, seen_cpus,
  251. numa_info[i].node_cpu, MAX_CPUMASK_BITS);
  252. }
  253. if (!bitmap_full(seen_cpus, max_cpus)) {
  254. char *msg;
  255. bitmap_complement(seen_cpus, seen_cpus, max_cpus);
  256. msg = enumerate_cpus(seen_cpus, max_cpus);
  257. error_report("warning: CPU(s) not present in any NUMA nodes: %s", msg);
  258. error_report("warning: All CPU(s) up to maxcpus should be described "
  259. "in NUMA config");
  260. g_free(msg);
  261. }
  262. }
  263. void parse_numa_opts(MachineClass *mc)
  264. {
  265. int i;
  266. if (qemu_opts_foreach(qemu_find_opts("numa"), parse_numa, NULL, NULL)) {
  267. exit(1);
  268. }
  269. assert(max_numa_nodeid <= MAX_NODES);
  270. /* No support for sparse NUMA node IDs yet: */
  271. for (i = max_numa_nodeid - 1; i >= 0; i--) {
  272. /* Report large node IDs first, to make mistakes easier to spot */
  273. if (!numa_info[i].present) {
  274. error_report("numa: Node ID missing: %d", i);
  275. exit(1);
  276. }
  277. }
  278. /* This must be always true if all nodes are present: */
  279. assert(nb_numa_nodes == max_numa_nodeid);
  280. if (nb_numa_nodes > 0) {
  281. uint64_t numa_total;
  282. if (nb_numa_nodes > MAX_NODES) {
  283. nb_numa_nodes = MAX_NODES;
  284. }
  285. /* If no memory size is given for any node, assume the default case
  286. * and distribute the available memory equally across all nodes
  287. */
  288. for (i = 0; i < nb_numa_nodes; i++) {
  289. if (numa_info[i].node_mem != 0) {
  290. break;
  291. }
  292. }
  293. if (i == nb_numa_nodes) {
  294. uint64_t usedmem = 0;
  295. /* On Linux, each node's border has to be 8MB aligned,
  296. * the final node gets the rest.
  297. */
  298. for (i = 0; i < nb_numa_nodes - 1; i++) {
  299. numa_info[i].node_mem = (ram_size / nb_numa_nodes) &
  300. ~((1 << 23UL) - 1);
  301. usedmem += numa_info[i].node_mem;
  302. }
  303. numa_info[i].node_mem = ram_size - usedmem;
  304. }
  305. numa_total = 0;
  306. for (i = 0; i < nb_numa_nodes; i++) {
  307. numa_total += numa_info[i].node_mem;
  308. }
  309. if (numa_total != ram_size) {
  310. error_report("total memory for NUMA nodes (0x%" PRIx64 ")"
  311. " should equal RAM size (0x" RAM_ADDR_FMT ")",
  312. numa_total, ram_size);
  313. exit(1);
  314. }
  315. for (i = 0; i < nb_numa_nodes; i++) {
  316. QLIST_INIT(&numa_info[i].addr);
  317. }
  318. numa_set_mem_ranges();
  319. for (i = 0; i < nb_numa_nodes; i++) {
  320. if (!bitmap_empty(numa_info[i].node_cpu, MAX_CPUMASK_BITS)) {
  321. break;
  322. }
  323. }
  324. /* Historically VCPUs were assigned in round-robin order to NUMA
  325. * nodes. However it causes issues with guest not handling it nice
  326. * in case where cores/threads from a multicore CPU appear on
  327. * different nodes. So allow boards to override default distribution
  328. * rule grouping VCPUs by socket so that VCPUs from the same socket
  329. * would be on the same node.
  330. */
  331. if (i == nb_numa_nodes) {
  332. for (i = 0; i < max_cpus; i++) {
  333. unsigned node_id = i % nb_numa_nodes;
  334. if (mc->cpu_index_to_socket_id) {
  335. node_id = mc->cpu_index_to_socket_id(i) % nb_numa_nodes;
  336. }
  337. set_bit(i, numa_info[node_id].node_cpu);
  338. }
  339. }
  340. validate_numa_cpus();
  341. } else {
  342. numa_set_mem_node_id(0, ram_size, 0);
  343. }
  344. }
  345. void numa_post_machine_init(void)
  346. {
  347. CPUState *cpu;
  348. int i;
  349. CPU_FOREACH(cpu) {
  350. for (i = 0; i < nb_numa_nodes; i++) {
  351. if (test_bit(cpu->cpu_index, numa_info[i].node_cpu)) {
  352. cpu->numa_node = i;
  353. }
  354. }
  355. }
  356. }
  357. static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner,
  358. const char *name,
  359. uint64_t ram_size)
  360. {
  361. if (mem_path) {
  362. #ifdef __linux__
  363. Error *err = NULL;
  364. memory_region_init_ram_from_file(mr, owner, name, ram_size, false,
  365. mem_path, &err);
  366. if (err) {
  367. error_report_err(err);
  368. if (mem_prealloc) {
  369. exit(1);
  370. }
  371. /* Legacy behavior: if allocation failed, fall back to
  372. * regular RAM allocation.
  373. */
  374. memory_region_init_ram(mr, owner, name, ram_size, &error_fatal);
  375. }
  376. #else
  377. fprintf(stderr, "-mem-path not supported on this host\n");
  378. exit(1);
  379. #endif
  380. } else {
  381. memory_region_init_ram(mr, owner, name, ram_size, &error_fatal);
  382. }
  383. vmstate_register_ram_global(mr);
  384. }
  385. void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
  386. const char *name,
  387. uint64_t ram_size)
  388. {
  389. uint64_t addr = 0;
  390. int i;
  391. if (nb_numa_nodes == 0 || !have_memdevs) {
  392. allocate_system_memory_nonnuma(mr, owner, name, ram_size);
  393. return;
  394. }
  395. memory_region_init(mr, owner, name, ram_size);
  396. for (i = 0; i < MAX_NODES; i++) {
  397. uint64_t size = numa_info[i].node_mem;
  398. HostMemoryBackend *backend = numa_info[i].node_memdev;
  399. if (!backend) {
  400. continue;
  401. }
  402. MemoryRegion *seg = host_memory_backend_get_memory(backend,
  403. &error_fatal);
  404. if (memory_region_is_mapped(seg)) {
  405. char *path = object_get_canonical_path_component(OBJECT(backend));
  406. error_report("memory backend %s is used multiple times. Each "
  407. "-numa option must use a different memdev value.",
  408. path);
  409. exit(1);
  410. }
  411. memory_region_add_subregion(mr, addr, seg);
  412. vmstate_register_ram_global(seg);
  413. addr += size;
  414. }
  415. }
  416. static void numa_stat_memory_devices(uint64_t node_mem[])
  417. {
  418. MemoryDeviceInfoList *info_list = NULL;
  419. MemoryDeviceInfoList **prev = &info_list;
  420. MemoryDeviceInfoList *info;
  421. qmp_pc_dimm_device_list(qdev_get_machine(), &prev);
  422. for (info = info_list; info; info = info->next) {
  423. MemoryDeviceInfo *value = info->value;
  424. if (value) {
  425. switch (value->type) {
  426. case MEMORY_DEVICE_INFO_KIND_DIMM:
  427. node_mem[value->u.dimm->node] += value->u.dimm->size;
  428. break;
  429. default:
  430. break;
  431. }
  432. }
  433. }
  434. qapi_free_MemoryDeviceInfoList(info_list);
  435. }
  436. void query_numa_node_mem(uint64_t node_mem[])
  437. {
  438. int i;
  439. if (nb_numa_nodes <= 0) {
  440. return;
  441. }
  442. numa_stat_memory_devices(node_mem);
  443. for (i = 0; i < nb_numa_nodes; i++) {
  444. node_mem[i] += numa_info[i].node_mem;
  445. }
  446. }
  447. static int query_memdev(Object *obj, void *opaque)
  448. {
  449. MemdevList **list = opaque;
  450. MemdevList *m = NULL;
  451. if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
  452. m = g_malloc0(sizeof(*m));
  453. m->value = g_malloc0(sizeof(*m->value));
  454. m->value->size = object_property_get_int(obj, "size",
  455. &error_abort);
  456. m->value->merge = object_property_get_bool(obj, "merge",
  457. &error_abort);
  458. m->value->dump = object_property_get_bool(obj, "dump",
  459. &error_abort);
  460. m->value->prealloc = object_property_get_bool(obj,
  461. "prealloc",
  462. &error_abort);
  463. m->value->policy = object_property_get_enum(obj,
  464. "policy",
  465. "HostMemPolicy",
  466. &error_abort);
  467. object_property_get_uint16List(obj, "host-nodes",
  468. &m->value->host_nodes,
  469. &error_abort);
  470. m->next = *list;
  471. *list = m;
  472. }
  473. return 0;
  474. }
  475. MemdevList *qmp_query_memdev(Error **errp)
  476. {
  477. Object *obj = object_get_objects_root();
  478. MemdevList *list = NULL;
  479. object_child_foreach(obj, query_memdev, &list);
  480. return list;
  481. }