unin_pci.c 15 KB

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  1. /*
  2. * QEMU Uninorth PCI host (for all Mac99 and newer machines)
  3. *
  4. * Copyright (c) 2006 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "hw.h"
  25. #include "ppc_mac.h"
  26. #include "pci/pci.h"
  27. #include "pci/pci_host.h"
  28. /* debug UniNorth */
  29. //#define DEBUG_UNIN
  30. #ifdef DEBUG_UNIN
  31. #define UNIN_DPRINTF(fmt, ...) \
  32. do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  33. #else
  34. #define UNIN_DPRINTF(fmt, ...)
  35. #endif
  36. static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
  37. #define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
  38. #define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
  39. #define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
  40. #define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
  41. #define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
  42. OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
  43. #define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
  44. OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
  45. #define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
  46. OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
  47. #define U3_AGP_HOST_BRIDGE(obj) \
  48. OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
  49. typedef struct UNINState {
  50. PCIHostState parent_obj;
  51. MemoryRegion pci_mmio;
  52. MemoryRegion pci_hole;
  53. } UNINState;
  54. static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
  55. {
  56. int retval;
  57. int devfn = pci_dev->devfn & 0x00FFFFFF;
  58. retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
  59. return retval;
  60. }
  61. static void pci_unin_set_irq(void *opaque, int irq_num, int level)
  62. {
  63. qemu_irq *pic = opaque;
  64. UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
  65. unin_irq_line[irq_num], level);
  66. qemu_set_irq(pic[unin_irq_line[irq_num]], level);
  67. }
  68. static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
  69. {
  70. uint32_t retval;
  71. if (reg & (1u << 31)) {
  72. /* XXX OpenBIOS compatibility hack */
  73. retval = reg | (addr & 3);
  74. } else if (reg & 1) {
  75. /* CFA1 style */
  76. retval = (reg & ~7u) | (addr & 7);
  77. } else {
  78. uint32_t slot, func;
  79. /* Grab CFA0 style values */
  80. slot = ffs(reg & 0xfffff800) - 1;
  81. func = (reg >> 8) & 7;
  82. /* ... and then convert them to x86 format */
  83. /* config pointer */
  84. retval = (reg & (0xff - 7)) | (addr & 7);
  85. /* slot */
  86. retval |= slot << 11;
  87. /* fn */
  88. retval |= func << 8;
  89. }
  90. UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
  91. reg, addr, retval);
  92. return retval;
  93. }
  94. static void unin_data_write(void *opaque, hwaddr addr,
  95. uint64_t val, unsigned len)
  96. {
  97. UNINState *s = opaque;
  98. PCIHostState *phb = PCI_HOST_BRIDGE(s);
  99. UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
  100. addr, len, val);
  101. pci_data_write(phb->bus,
  102. unin_get_config_reg(phb->config_reg, addr),
  103. val, len);
  104. }
  105. static uint64_t unin_data_read(void *opaque, hwaddr addr,
  106. unsigned len)
  107. {
  108. UNINState *s = opaque;
  109. PCIHostState *phb = PCI_HOST_BRIDGE(s);
  110. uint32_t val;
  111. val = pci_data_read(phb->bus,
  112. unin_get_config_reg(phb->config_reg, addr),
  113. len);
  114. UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
  115. addr, len, val);
  116. return val;
  117. }
  118. static const MemoryRegionOps unin_data_ops = {
  119. .read = unin_data_read,
  120. .write = unin_data_write,
  121. .endianness = DEVICE_LITTLE_ENDIAN,
  122. };
  123. static int pci_unin_main_init_device(SysBusDevice *dev)
  124. {
  125. PCIHostState *h;
  126. /* Use values found on a real PowerMac */
  127. /* Uninorth main bus */
  128. h = PCI_HOST_BRIDGE(dev);
  129. memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
  130. dev, "pci-conf-idx", 0x1000);
  131. memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
  132. "pci-conf-data", 0x1000);
  133. sysbus_init_mmio(dev, &h->conf_mem);
  134. sysbus_init_mmio(dev, &h->data_mem);
  135. return 0;
  136. }
  137. static int pci_u3_agp_init_device(SysBusDevice *dev)
  138. {
  139. PCIHostState *h;
  140. /* Uninorth U3 AGP bus */
  141. h = PCI_HOST_BRIDGE(dev);
  142. memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
  143. dev, "pci-conf-idx", 0x1000);
  144. memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
  145. "pci-conf-data", 0x1000);
  146. sysbus_init_mmio(dev, &h->conf_mem);
  147. sysbus_init_mmio(dev, &h->data_mem);
  148. return 0;
  149. }
  150. static int pci_unin_agp_init_device(SysBusDevice *dev)
  151. {
  152. PCIHostState *h;
  153. /* Uninorth AGP bus */
  154. h = PCI_HOST_BRIDGE(dev);
  155. memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
  156. dev, "pci-conf-idx", 0x1000);
  157. memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
  158. dev, "pci-conf-data", 0x1000);
  159. sysbus_init_mmio(dev, &h->conf_mem);
  160. sysbus_init_mmio(dev, &h->data_mem);
  161. return 0;
  162. }
  163. static int pci_unin_internal_init_device(SysBusDevice *dev)
  164. {
  165. PCIHostState *h;
  166. /* Uninorth internal bus */
  167. h = PCI_HOST_BRIDGE(dev);
  168. memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
  169. dev, "pci-conf-idx", 0x1000);
  170. memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
  171. dev, "pci-conf-data", 0x1000);
  172. sysbus_init_mmio(dev, &h->conf_mem);
  173. sysbus_init_mmio(dev, &h->data_mem);
  174. return 0;
  175. }
  176. PCIBus *pci_pmac_init(qemu_irq *pic,
  177. MemoryRegion *address_space_mem,
  178. MemoryRegion *address_space_io)
  179. {
  180. DeviceState *dev;
  181. SysBusDevice *s;
  182. PCIHostState *h;
  183. UNINState *d;
  184. /* Use values found on a real PowerMac */
  185. /* Uninorth main bus */
  186. dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
  187. qdev_init_nofail(dev);
  188. s = SYS_BUS_DEVICE(dev);
  189. h = PCI_HOST_BRIDGE(s);
  190. d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
  191. memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
  192. memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
  193. 0x80000000ULL, 0x70000000ULL);
  194. memory_region_add_subregion(address_space_mem, 0x80000000ULL,
  195. &d->pci_hole);
  196. h->bus = pci_register_bus(dev, "pci",
  197. pci_unin_set_irq, pci_unin_map_irq,
  198. pic,
  199. &d->pci_mmio,
  200. address_space_io,
  201. PCI_DEVFN(11, 0), 4);
  202. #if 0
  203. pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
  204. #endif
  205. sysbus_mmio_map(s, 0, 0xf2800000);
  206. sysbus_mmio_map(s, 1, 0xf2c00000);
  207. /* DEC 21154 bridge */
  208. #if 0
  209. /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
  210. pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
  211. #endif
  212. /* Uninorth AGP bus */
  213. pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
  214. dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
  215. qdev_init_nofail(dev);
  216. s = SYS_BUS_DEVICE(dev);
  217. sysbus_mmio_map(s, 0, 0xf0800000);
  218. sysbus_mmio_map(s, 1, 0xf0c00000);
  219. /* Uninorth internal bus */
  220. #if 0
  221. /* XXX: not needed for now */
  222. pci_create_simple(h->bus, PCI_DEVFN(14, 0),
  223. "uni-north-internal-pci");
  224. dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
  225. qdev_init_nofail(dev);
  226. s = SYS_BUS_DEVICE(dev);
  227. sysbus_mmio_map(s, 0, 0xf4800000);
  228. sysbus_mmio_map(s, 1, 0xf4c00000);
  229. #endif
  230. return h->bus;
  231. }
  232. PCIBus *pci_pmac_u3_init(qemu_irq *pic,
  233. MemoryRegion *address_space_mem,
  234. MemoryRegion *address_space_io)
  235. {
  236. DeviceState *dev;
  237. SysBusDevice *s;
  238. PCIHostState *h;
  239. UNINState *d;
  240. /* Uninorth AGP bus */
  241. dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
  242. qdev_init_nofail(dev);
  243. s = SYS_BUS_DEVICE(dev);
  244. h = PCI_HOST_BRIDGE(dev);
  245. d = U3_AGP_HOST_BRIDGE(dev);
  246. memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
  247. memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
  248. 0x80000000ULL, 0x70000000ULL);
  249. memory_region_add_subregion(address_space_mem, 0x80000000ULL,
  250. &d->pci_hole);
  251. h->bus = pci_register_bus(dev, "pci",
  252. pci_unin_set_irq, pci_unin_map_irq,
  253. pic,
  254. &d->pci_mmio,
  255. address_space_io,
  256. PCI_DEVFN(11, 0), 4);
  257. sysbus_mmio_map(s, 0, 0xf0800000);
  258. sysbus_mmio_map(s, 1, 0xf0c00000);
  259. pci_create_simple(h->bus, 11 << 3, "u3-agp");
  260. return h->bus;
  261. }
  262. static int unin_main_pci_host_init(PCIDevice *d)
  263. {
  264. d->config[0x0C] = 0x08; // cache_line_size
  265. d->config[0x0D] = 0x10; // latency_timer
  266. d->config[0x34] = 0x00; // capabilities_pointer
  267. return 0;
  268. }
  269. static int unin_agp_pci_host_init(PCIDevice *d)
  270. {
  271. d->config[0x0C] = 0x08; // cache_line_size
  272. d->config[0x0D] = 0x10; // latency_timer
  273. // d->config[0x34] = 0x80; // capabilities_pointer
  274. return 0;
  275. }
  276. static int u3_agp_pci_host_init(PCIDevice *d)
  277. {
  278. /* cache line size */
  279. d->config[0x0C] = 0x08;
  280. /* latency timer */
  281. d->config[0x0D] = 0x10;
  282. return 0;
  283. }
  284. static int unin_internal_pci_host_init(PCIDevice *d)
  285. {
  286. d->config[0x0C] = 0x08; // cache_line_size
  287. d->config[0x0D] = 0x10; // latency_timer
  288. d->config[0x34] = 0x00; // capabilities_pointer
  289. return 0;
  290. }
  291. static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
  292. {
  293. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  294. k->init = unin_main_pci_host_init;
  295. k->vendor_id = PCI_VENDOR_ID_APPLE;
  296. k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
  297. k->revision = 0x00;
  298. k->class_id = PCI_CLASS_BRIDGE_HOST;
  299. }
  300. static const TypeInfo unin_main_pci_host_info = {
  301. .name = "uni-north-pci",
  302. .parent = TYPE_PCI_DEVICE,
  303. .instance_size = sizeof(PCIDevice),
  304. .class_init = unin_main_pci_host_class_init,
  305. };
  306. static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
  307. {
  308. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  309. k->init = u3_agp_pci_host_init;
  310. k->vendor_id = PCI_VENDOR_ID_APPLE;
  311. k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
  312. k->revision = 0x00;
  313. k->class_id = PCI_CLASS_BRIDGE_HOST;
  314. }
  315. static const TypeInfo u3_agp_pci_host_info = {
  316. .name = "u3-agp",
  317. .parent = TYPE_PCI_DEVICE,
  318. .instance_size = sizeof(PCIDevice),
  319. .class_init = u3_agp_pci_host_class_init,
  320. };
  321. static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
  322. {
  323. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  324. k->init = unin_agp_pci_host_init;
  325. k->vendor_id = PCI_VENDOR_ID_APPLE;
  326. k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
  327. k->revision = 0x00;
  328. k->class_id = PCI_CLASS_BRIDGE_HOST;
  329. }
  330. static const TypeInfo unin_agp_pci_host_info = {
  331. .name = "uni-north-agp",
  332. .parent = TYPE_PCI_DEVICE,
  333. .instance_size = sizeof(PCIDevice),
  334. .class_init = unin_agp_pci_host_class_init,
  335. };
  336. static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
  337. {
  338. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  339. k->init = unin_internal_pci_host_init;
  340. k->vendor_id = PCI_VENDOR_ID_APPLE;
  341. k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
  342. k->revision = 0x00;
  343. k->class_id = PCI_CLASS_BRIDGE_HOST;
  344. }
  345. static const TypeInfo unin_internal_pci_host_info = {
  346. .name = "uni-north-internal-pci",
  347. .parent = TYPE_PCI_DEVICE,
  348. .instance_size = sizeof(PCIDevice),
  349. .class_init = unin_internal_pci_host_class_init,
  350. };
  351. static void pci_unin_main_class_init(ObjectClass *klass, void *data)
  352. {
  353. SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
  354. sbc->init = pci_unin_main_init_device;
  355. }
  356. static const TypeInfo pci_unin_main_info = {
  357. .name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
  358. .parent = TYPE_PCI_HOST_BRIDGE,
  359. .instance_size = sizeof(UNINState),
  360. .class_init = pci_unin_main_class_init,
  361. };
  362. static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
  363. {
  364. SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
  365. sbc->init = pci_u3_agp_init_device;
  366. }
  367. static const TypeInfo pci_u3_agp_info = {
  368. .name = TYPE_U3_AGP_HOST_BRIDGE,
  369. .parent = TYPE_PCI_HOST_BRIDGE,
  370. .instance_size = sizeof(UNINState),
  371. .class_init = pci_u3_agp_class_init,
  372. };
  373. static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
  374. {
  375. SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
  376. sbc->init = pci_unin_agp_init_device;
  377. }
  378. static const TypeInfo pci_unin_agp_info = {
  379. .name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
  380. .parent = TYPE_PCI_HOST_BRIDGE,
  381. .instance_size = sizeof(UNINState),
  382. .class_init = pci_unin_agp_class_init,
  383. };
  384. static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
  385. {
  386. SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
  387. sbc->init = pci_unin_internal_init_device;
  388. }
  389. static const TypeInfo pci_unin_internal_info = {
  390. .name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
  391. .parent = TYPE_PCI_HOST_BRIDGE,
  392. .instance_size = sizeof(UNINState),
  393. .class_init = pci_unin_internal_class_init,
  394. };
  395. static void unin_register_types(void)
  396. {
  397. type_register_static(&unin_main_pci_host_info);
  398. type_register_static(&u3_agp_pci_host_info);
  399. type_register_static(&unin_agp_pci_host_info);
  400. type_register_static(&unin_internal_pci_host_info);
  401. type_register_static(&pci_unin_main_info);
  402. type_register_static(&pci_u3_agp_info);
  403. type_register_static(&pci_unin_agp_info);
  404. type_register_static(&pci_unin_internal_info);
  405. }
  406. type_init(unin_register_types)