pci.json 8.8 KB

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  1. # -*- Mode: Python -*-
  2. # vim: filetype=python
  3. #
  4. # This work is licensed under the terms of the GNU GPL, version 2 or later.
  5. # See the COPYING file in the top-level directory.
  6. # SPDX-License-Identifier: GPL-2.0-or-later
  7. ##
  8. # = PCI
  9. ##
  10. ##
  11. # @PciMemoryRange:
  12. #
  13. # A PCI device memory region
  14. #
  15. # @base: the starting address (guest physical)
  16. #
  17. # @limit: the ending address (guest physical)
  18. #
  19. # Since: 0.14
  20. ##
  21. { 'struct': 'PciMemoryRange', 'data': {'base': 'int', 'limit': 'int'} }
  22. ##
  23. # @PciMemoryRegion:
  24. #
  25. # Information about a PCI device I/O region.
  26. #
  27. # @bar: the index of the Base Address Register for this region
  28. #
  29. # @type:
  30. # - 'io' if the region is a PIO region
  31. # - 'memory' if the region is a MMIO region
  32. #
  33. # @address: memory address
  34. #
  35. # @size: memory size
  36. #
  37. # @prefetch: if @type is 'memory', true if the memory is prefetchable
  38. #
  39. # @mem_type_64: if @type is 'memory', true if the BAR is 64-bit
  40. #
  41. # Since: 0.14
  42. ##
  43. { 'struct': 'PciMemoryRegion',
  44. 'data': {'bar': 'int', 'type': 'str', 'address': 'int', 'size': 'int',
  45. '*prefetch': 'bool', '*mem_type_64': 'bool' } }
  46. ##
  47. # @PciBusInfo:
  48. #
  49. # Information about a bus of a PCI Bridge device
  50. #
  51. # @number: primary bus interface number. This should be the number of
  52. # the bus the device resides on.
  53. #
  54. # @secondary: secondary bus interface number. This is the number of
  55. # the main bus for the bridge
  56. #
  57. # @subordinate: This is the highest number bus that resides below the
  58. # bridge.
  59. #
  60. # @io_range: The PIO range for all devices on this bridge
  61. #
  62. # @memory_range: The MMIO range for all devices on this bridge
  63. #
  64. # @prefetchable_range: The range of prefetchable MMIO for all devices
  65. # on this bridge
  66. #
  67. # Since: 2.4
  68. ##
  69. { 'struct': 'PciBusInfo',
  70. 'data': {'number': 'int', 'secondary': 'int', 'subordinate': 'int',
  71. 'io_range': 'PciMemoryRange',
  72. 'memory_range': 'PciMemoryRange',
  73. 'prefetchable_range': 'PciMemoryRange' } }
  74. ##
  75. # @PciBridgeInfo:
  76. #
  77. # Information about a PCI Bridge device
  78. #
  79. # @bus: information about the bus the device resides on
  80. #
  81. # @devices: a list of @PciDeviceInfo for each device on this bridge
  82. #
  83. # Since: 0.14
  84. ##
  85. { 'struct': 'PciBridgeInfo',
  86. 'data': {'bus': 'PciBusInfo', '*devices': ['PciDeviceInfo']} }
  87. ##
  88. # @PciDeviceClass:
  89. #
  90. # Information about the Class of a PCI device
  91. #
  92. # @desc: a string description of the device's class (not stable, and
  93. # should only be treated as informational)
  94. #
  95. # @class: the class code of the device
  96. #
  97. # Since: 2.4
  98. ##
  99. { 'struct': 'PciDeviceClass',
  100. 'data': {'*desc': 'str', 'class': 'int'} }
  101. ##
  102. # @PciDeviceId:
  103. #
  104. # Information about the Id of a PCI device
  105. #
  106. # @device: the PCI device id
  107. #
  108. # @vendor: the PCI vendor id
  109. #
  110. # @subsystem: the PCI subsystem id (since 3.1)
  111. #
  112. # @subsystem-vendor: the PCI subsystem vendor id (since 3.1)
  113. #
  114. # Since: 2.4
  115. ##
  116. { 'struct': 'PciDeviceId',
  117. 'data': {'device': 'int', 'vendor': 'int', '*subsystem': 'int',
  118. '*subsystem-vendor': 'int'} }
  119. ##
  120. # @PciDeviceInfo:
  121. #
  122. # Information about a PCI device
  123. #
  124. # @bus: the bus number of the device
  125. #
  126. # @slot: the slot the device is located in
  127. #
  128. # @function: the function of the slot used by the device
  129. #
  130. # @class_info: the class of the device
  131. #
  132. # @id: the PCI device id
  133. #
  134. # @irq: if an IRQ is assigned to the device, the IRQ number
  135. #
  136. # @irq_pin: the IRQ pin, zero means no IRQ (since 5.1)
  137. #
  138. # @qdev_id: the device name of the PCI device
  139. #
  140. # @pci_bridge: if the device is a PCI bridge, the bridge information
  141. #
  142. # @regions: a list of the PCI I/O regions associated with the device
  143. #
  144. # Since: 0.14
  145. ##
  146. { 'struct': 'PciDeviceInfo',
  147. 'data': {'bus': 'int', 'slot': 'int', 'function': 'int',
  148. 'class_info': 'PciDeviceClass', 'id': 'PciDeviceId',
  149. '*irq': 'int', 'irq_pin': 'int', 'qdev_id': 'str',
  150. '*pci_bridge': 'PciBridgeInfo', 'regions': ['PciMemoryRegion'] }}
  151. ##
  152. # @PciInfo:
  153. #
  154. # Information about a PCI bus
  155. #
  156. # @bus: the bus index
  157. #
  158. # @devices: a list of devices on this bus
  159. #
  160. # Since: 0.14
  161. ##
  162. { 'struct': 'PciInfo', 'data': {'bus': 'int', 'devices': ['PciDeviceInfo']} }
  163. ##
  164. # @query-pci:
  165. #
  166. # Return information about the PCI bus topology of the guest.
  167. #
  168. # Returns: a list of @PciInfo for each PCI bus. Each bus is
  169. # represented by a json-object, which has a key with a json-array
  170. # of all PCI devices attached to it. Each device is represented
  171. # by a json-object.
  172. #
  173. # Since: 0.14
  174. #
  175. # .. qmp-example::
  176. #
  177. # -> { "execute": "query-pci" }
  178. # <- { "return": [
  179. # {
  180. # "bus": 0,
  181. # "devices": [
  182. # {
  183. # "bus": 0,
  184. # "qdev_id": "",
  185. # "slot": 0,
  186. # "class_info": {
  187. # "class": 1536,
  188. # "desc": "Host bridge"
  189. # },
  190. # "id": {
  191. # "device": 32902,
  192. # "vendor": 4663
  193. # },
  194. # "function": 0,
  195. # "regions": [
  196. # ]
  197. # },
  198. # {
  199. # "bus": 0,
  200. # "qdev_id": "",
  201. # "slot": 1,
  202. # "class_info": {
  203. # "class": 1537,
  204. # "desc": "ISA bridge"
  205. # },
  206. # "id": {
  207. # "device": 32902,
  208. # "vendor": 28672
  209. # },
  210. # "function": 0,
  211. # "regions": [
  212. # ]
  213. # },
  214. # {
  215. # "bus": 0,
  216. # "qdev_id": "",
  217. # "slot": 1,
  218. # "class_info": {
  219. # "class": 257,
  220. # "desc": "IDE controller"
  221. # },
  222. # "id": {
  223. # "device": 32902,
  224. # "vendor": 28688
  225. # },
  226. # "function": 1,
  227. # "regions": [
  228. # {
  229. # "bar": 4,
  230. # "size": 16,
  231. # "address": 49152,
  232. # "type": "io"
  233. # }
  234. # ]
  235. # },
  236. # {
  237. # "bus": 0,
  238. # "qdev_id": "",
  239. # "slot": 2,
  240. # "class_info": {
  241. # "class": 768,
  242. # "desc": "VGA controller"
  243. # },
  244. # "id": {
  245. # "device": 4115,
  246. # "vendor": 184
  247. # },
  248. # "function": 0,
  249. # "regions": [
  250. # {
  251. # "prefetch": true,
  252. # "mem_type_64": false,
  253. # "bar": 0,
  254. # "size": 33554432,
  255. # "address": 4026531840,
  256. # "type": "memory"
  257. # },
  258. # {
  259. # "prefetch": false,
  260. # "mem_type_64": false,
  261. # "bar": 1,
  262. # "size": 4096,
  263. # "address": 4060086272,
  264. # "type": "memory"
  265. # },
  266. # {
  267. # "prefetch": false,
  268. # "mem_type_64": false,
  269. # "bar": 6,
  270. # "size": 65536,
  271. # "address": -1,
  272. # "type": "memory"
  273. # }
  274. # ]
  275. # },
  276. # {
  277. # "bus": 0,
  278. # "qdev_id": "",
  279. # "irq": 11,
  280. # "slot": 4,
  281. # "class_info": {
  282. # "class": 1280,
  283. # "desc": "RAM controller"
  284. # },
  285. # "id": {
  286. # "device": 6900,
  287. # "vendor": 4098
  288. # },
  289. # "function": 0,
  290. # "regions": [
  291. # {
  292. # "bar": 0,
  293. # "size": 32,
  294. # "address": 49280,
  295. # "type": "io"
  296. # }
  297. # ]
  298. # }
  299. # ]
  300. # }
  301. # ]
  302. # }
  303. #
  304. # This example has been shortened as the real response is too long.
  305. ##
  306. { 'command': 'query-pci', 'returns': ['PciInfo'] }