cpu.c 13 KB

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  1. /*
  2. * Target-specific parts of the CPU object
  3. *
  4. * Copyright (c) 2003 Fabrice Bellard
  5. *
  6. * This library is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU Lesser General Public
  8. * License as published by the Free Software Foundation; either
  9. * version 2 of the License, or (at your option) any later version.
  10. *
  11. * This library is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * Lesser General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU Lesser General Public
  17. * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "qemu/osdep.h"
  20. #include "qapi/error.h"
  21. #include "exec/target_page.h"
  22. #include "hw/qdev-core.h"
  23. #include "hw/qdev-properties.h"
  24. #include "qemu/error-report.h"
  25. #include "migration/vmstate.h"
  26. #ifdef CONFIG_USER_ONLY
  27. #include "qemu.h"
  28. #else
  29. #include "hw/core/sysemu-cpu-ops.h"
  30. #include "exec/address-spaces.h"
  31. #endif
  32. #include "sysemu/tcg.h"
  33. #include "sysemu/kvm.h"
  34. #include "sysemu/replay.h"
  35. #include "exec/cpu-common.h"
  36. #include "exec/exec-all.h"
  37. #include "exec/translate-all.h"
  38. #include "exec/log.h"
  39. #include "hw/core/accel-cpu.h"
  40. #include "trace/trace-root.h"
  41. #include "qemu/accel.h"
  42. uintptr_t qemu_host_page_size;
  43. intptr_t qemu_host_page_mask;
  44. #ifndef CONFIG_USER_ONLY
  45. static int cpu_common_post_load(void *opaque, int version_id)
  46. {
  47. CPUState *cpu = opaque;
  48. /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
  49. version_id is increased. */
  50. cpu->interrupt_request &= ~0x01;
  51. tlb_flush(cpu);
  52. /* loadvm has just updated the content of RAM, bypassing the
  53. * usual mechanisms that ensure we flush TBs for writes to
  54. * memory we've translated code from. So we must flush all TBs,
  55. * which will now be stale.
  56. */
  57. tb_flush(cpu);
  58. return 0;
  59. }
  60. static int cpu_common_pre_load(void *opaque)
  61. {
  62. CPUState *cpu = opaque;
  63. cpu->exception_index = -1;
  64. return 0;
  65. }
  66. static bool cpu_common_exception_index_needed(void *opaque)
  67. {
  68. CPUState *cpu = opaque;
  69. return tcg_enabled() && cpu->exception_index != -1;
  70. }
  71. static const VMStateDescription vmstate_cpu_common_exception_index = {
  72. .name = "cpu_common/exception_index",
  73. .version_id = 1,
  74. .minimum_version_id = 1,
  75. .needed = cpu_common_exception_index_needed,
  76. .fields = (VMStateField[]) {
  77. VMSTATE_INT32(exception_index, CPUState),
  78. VMSTATE_END_OF_LIST()
  79. }
  80. };
  81. static bool cpu_common_crash_occurred_needed(void *opaque)
  82. {
  83. CPUState *cpu = opaque;
  84. return cpu->crash_occurred;
  85. }
  86. static const VMStateDescription vmstate_cpu_common_crash_occurred = {
  87. .name = "cpu_common/crash_occurred",
  88. .version_id = 1,
  89. .minimum_version_id = 1,
  90. .needed = cpu_common_crash_occurred_needed,
  91. .fields = (VMStateField[]) {
  92. VMSTATE_BOOL(crash_occurred, CPUState),
  93. VMSTATE_END_OF_LIST()
  94. }
  95. };
  96. const VMStateDescription vmstate_cpu_common = {
  97. .name = "cpu_common",
  98. .version_id = 1,
  99. .minimum_version_id = 1,
  100. .pre_load = cpu_common_pre_load,
  101. .post_load = cpu_common_post_load,
  102. .fields = (VMStateField[]) {
  103. VMSTATE_UINT32(halted, CPUState),
  104. VMSTATE_UINT32(interrupt_request, CPUState),
  105. VMSTATE_END_OF_LIST()
  106. },
  107. .subsections = (const VMStateDescription*[]) {
  108. &vmstate_cpu_common_exception_index,
  109. &vmstate_cpu_common_crash_occurred,
  110. NULL
  111. }
  112. };
  113. #endif
  114. void cpu_exec_realizefn(CPUState *cpu, Error **errp)
  115. {
  116. #ifndef CONFIG_USER_ONLY
  117. CPUClass *cc = CPU_GET_CLASS(cpu);
  118. #endif
  119. cpu_list_add(cpu);
  120. if (!accel_cpu_realizefn(cpu, errp)) {
  121. return;
  122. }
  123. /* NB: errp parameter is unused currently */
  124. if (tcg_enabled()) {
  125. tcg_exec_realizefn(cpu, errp);
  126. }
  127. #ifdef CONFIG_USER_ONLY
  128. assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
  129. qdev_get_vmsd(DEVICE(cpu))->unmigratable);
  130. #else
  131. if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
  132. vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
  133. }
  134. if (cc->sysemu_ops->legacy_vmsd != NULL) {
  135. vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
  136. }
  137. #endif /* CONFIG_USER_ONLY */
  138. }
  139. void cpu_exec_unrealizefn(CPUState *cpu)
  140. {
  141. #ifndef CONFIG_USER_ONLY
  142. CPUClass *cc = CPU_GET_CLASS(cpu);
  143. if (cc->sysemu_ops->legacy_vmsd != NULL) {
  144. vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
  145. }
  146. if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
  147. vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
  148. }
  149. #endif
  150. if (tcg_enabled()) {
  151. tcg_exec_unrealizefn(cpu);
  152. }
  153. cpu_list_remove(cpu);
  154. }
  155. /*
  156. * This can't go in hw/core/cpu.c because that file is compiled only
  157. * once for both user-mode and system builds.
  158. */
  159. static Property cpu_common_props[] = {
  160. #ifdef CONFIG_USER_ONLY
  161. /*
  162. * Create a property for the user-only object, so users can
  163. * adjust prctl(PR_SET_UNALIGN) from the command-line.
  164. * Has no effect if the target does not support the feature.
  165. */
  166. DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
  167. prctl_unalign_sigbus, false),
  168. #else
  169. /*
  170. * Create a memory property for softmmu CPU object, so users can
  171. * wire up its memory. The default if no link is set up is to use
  172. * the system address space.
  173. */
  174. DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
  175. MemoryRegion *),
  176. #endif
  177. DEFINE_PROP_END_OF_LIST(),
  178. };
  179. static bool cpu_get_start_powered_off(Object *obj, Error **errp)
  180. {
  181. CPUState *cpu = CPU(obj);
  182. return cpu->start_powered_off;
  183. }
  184. static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
  185. {
  186. CPUState *cpu = CPU(obj);
  187. cpu->start_powered_off = value;
  188. }
  189. void cpu_class_init_props(DeviceClass *dc)
  190. {
  191. ObjectClass *oc = OBJECT_CLASS(dc);
  192. device_class_set_props(dc, cpu_common_props);
  193. /*
  194. * We can't use DEFINE_PROP_BOOL in the Property array for this
  195. * property, because we want this to be settable after realize.
  196. */
  197. object_class_property_add_bool(oc, "start-powered-off",
  198. cpu_get_start_powered_off,
  199. cpu_set_start_powered_off);
  200. }
  201. void cpu_exec_initfn(CPUState *cpu)
  202. {
  203. cpu->as = NULL;
  204. cpu->num_ases = 0;
  205. #ifndef CONFIG_USER_ONLY
  206. cpu->thread_id = qemu_get_thread_id();
  207. cpu->memory = get_system_memory();
  208. object_ref(OBJECT(cpu->memory));
  209. #endif
  210. }
  211. const char *parse_cpu_option(const char *cpu_option)
  212. {
  213. ObjectClass *oc;
  214. CPUClass *cc;
  215. gchar **model_pieces;
  216. const char *cpu_type;
  217. model_pieces = g_strsplit(cpu_option, ",", 2);
  218. if (!model_pieces[0]) {
  219. error_report("-cpu option cannot be empty");
  220. exit(1);
  221. }
  222. oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
  223. if (oc == NULL) {
  224. error_report("unable to find CPU model '%s'", model_pieces[0]);
  225. g_strfreev(model_pieces);
  226. exit(EXIT_FAILURE);
  227. }
  228. cpu_type = object_class_get_name(oc);
  229. cc = CPU_CLASS(oc);
  230. cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
  231. g_strfreev(model_pieces);
  232. return cpu_type;
  233. }
  234. void list_cpus(const char *optarg)
  235. {
  236. /* XXX: implement xxx_cpu_list for targets that still miss it */
  237. #if defined(cpu_list)
  238. cpu_list();
  239. #endif
  240. }
  241. #if defined(CONFIG_USER_ONLY)
  242. void tb_invalidate_phys_addr(target_ulong addr)
  243. {
  244. mmap_lock();
  245. tb_invalidate_phys_page_range(addr, addr + 1);
  246. mmap_unlock();
  247. }
  248. #else
  249. void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
  250. {
  251. ram_addr_t ram_addr;
  252. MemoryRegion *mr;
  253. hwaddr l = 1;
  254. if (!tcg_enabled()) {
  255. return;
  256. }
  257. RCU_READ_LOCK_GUARD();
  258. mr = address_space_translate(as, addr, &addr, &l, false, attrs);
  259. if (!(memory_region_is_ram(mr)
  260. || memory_region_is_romd(mr))) {
  261. return;
  262. }
  263. ram_addr = memory_region_get_ram_addr(mr) + addr;
  264. tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
  265. }
  266. #endif
  267. /* Add a breakpoint. */
  268. int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
  269. CPUBreakpoint **breakpoint)
  270. {
  271. CPUClass *cc = CPU_GET_CLASS(cpu);
  272. CPUBreakpoint *bp;
  273. if (cc->gdb_adjust_breakpoint) {
  274. pc = cc->gdb_adjust_breakpoint(cpu, pc);
  275. }
  276. bp = g_malloc(sizeof(*bp));
  277. bp->pc = pc;
  278. bp->flags = flags;
  279. /* keep all GDB-injected breakpoints in front */
  280. if (flags & BP_GDB) {
  281. QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
  282. } else {
  283. QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
  284. }
  285. if (breakpoint) {
  286. *breakpoint = bp;
  287. }
  288. trace_breakpoint_insert(cpu->cpu_index, pc, flags);
  289. return 0;
  290. }
  291. /* Remove a specific breakpoint. */
  292. int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
  293. {
  294. CPUClass *cc = CPU_GET_CLASS(cpu);
  295. CPUBreakpoint *bp;
  296. if (cc->gdb_adjust_breakpoint) {
  297. pc = cc->gdb_adjust_breakpoint(cpu, pc);
  298. }
  299. QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
  300. if (bp->pc == pc && bp->flags == flags) {
  301. cpu_breakpoint_remove_by_ref(cpu, bp);
  302. return 0;
  303. }
  304. }
  305. return -ENOENT;
  306. }
  307. /* Remove a specific breakpoint by reference. */
  308. void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
  309. {
  310. QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
  311. trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
  312. g_free(bp);
  313. }
  314. /* Remove all matching breakpoints. */
  315. void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
  316. {
  317. CPUBreakpoint *bp, *next;
  318. QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
  319. if (bp->flags & mask) {
  320. cpu_breakpoint_remove_by_ref(cpu, bp);
  321. }
  322. }
  323. }
  324. /* enable or disable single step mode. EXCP_DEBUG is returned by the
  325. CPU loop after each instruction */
  326. void cpu_single_step(CPUState *cpu, int enabled)
  327. {
  328. if (cpu->singlestep_enabled != enabled) {
  329. cpu->singlestep_enabled = enabled;
  330. if (kvm_enabled()) {
  331. kvm_update_guest_debug(cpu, 0);
  332. }
  333. trace_breakpoint_singlestep(cpu->cpu_index, enabled);
  334. }
  335. }
  336. void cpu_abort(CPUState *cpu, const char *fmt, ...)
  337. {
  338. va_list ap;
  339. va_list ap2;
  340. va_start(ap, fmt);
  341. va_copy(ap2, ap);
  342. fprintf(stderr, "qemu: fatal: ");
  343. vfprintf(stderr, fmt, ap);
  344. fprintf(stderr, "\n");
  345. cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
  346. if (qemu_log_separate()) {
  347. FILE *logfile = qemu_log_trylock();
  348. if (logfile) {
  349. fprintf(logfile, "qemu: fatal: ");
  350. vfprintf(logfile, fmt, ap2);
  351. fprintf(logfile, "\n");
  352. cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
  353. qemu_log_unlock(logfile);
  354. }
  355. }
  356. va_end(ap2);
  357. va_end(ap);
  358. replay_finish();
  359. #if defined(CONFIG_USER_ONLY)
  360. {
  361. struct sigaction act;
  362. sigfillset(&act.sa_mask);
  363. act.sa_handler = SIG_DFL;
  364. act.sa_flags = 0;
  365. sigaction(SIGABRT, &act, NULL);
  366. }
  367. #endif
  368. abort();
  369. }
  370. /* physical memory access (slow version, mainly for debug) */
  371. #if defined(CONFIG_USER_ONLY)
  372. int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
  373. void *ptr, size_t len, bool is_write)
  374. {
  375. int flags;
  376. vaddr l, page;
  377. void * p;
  378. uint8_t *buf = ptr;
  379. while (len > 0) {
  380. page = addr & TARGET_PAGE_MASK;
  381. l = (page + TARGET_PAGE_SIZE) - addr;
  382. if (l > len)
  383. l = len;
  384. flags = page_get_flags(page);
  385. if (!(flags & PAGE_VALID))
  386. return -1;
  387. if (is_write) {
  388. if (!(flags & PAGE_WRITE))
  389. return -1;
  390. /* XXX: this code should not depend on lock_user */
  391. if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
  392. return -1;
  393. memcpy(p, buf, l);
  394. unlock_user(p, addr, l);
  395. } else {
  396. if (!(flags & PAGE_READ))
  397. return -1;
  398. /* XXX: this code should not depend on lock_user */
  399. if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
  400. return -1;
  401. memcpy(buf, p, l);
  402. unlock_user(p, addr, 0);
  403. }
  404. len -= l;
  405. buf += l;
  406. addr += l;
  407. }
  408. return 0;
  409. }
  410. #endif
  411. bool target_words_bigendian(void)
  412. {
  413. #if TARGET_BIG_ENDIAN
  414. return true;
  415. #else
  416. return false;
  417. #endif
  418. }
  419. void page_size_init(void)
  420. {
  421. /* NOTE: we can always suppose that qemu_host_page_size >=
  422. TARGET_PAGE_SIZE */
  423. if (qemu_host_page_size == 0) {
  424. qemu_host_page_size = qemu_real_host_page_size();
  425. }
  426. if (qemu_host_page_size < TARGET_PAGE_SIZE) {
  427. qemu_host_page_size = TARGET_PAGE_SIZE;
  428. }
  429. qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
  430. }