xtensa-modules.c.inc 330 KB

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  1. /* Xtensa configuration-specific ISA information.
  2. Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
  3. This file is part of BFD, the Binary File Descriptor library.
  4. This program is free software; you can redistribute it and/or
  5. modify it under the terms of the GNU General Public License as
  6. published by the Free Software Foundation; either version 2 of the
  7. License, or (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  15. 02110-1301, USA. */
  16. #include "qemu/osdep.h"
  17. #include "xtensa-isa.h"
  18. #include "xtensa-isa-internal.h"
  19. /* Sysregs. */
  20. static xtensa_sysreg_internal sysregs[] = {
  21. { "LBEG", 0, 0 },
  22. { "LEND", 1, 0 },
  23. { "LCOUNT", 2, 0 },
  24. { "ACCLO", 16, 0 },
  25. { "ACCHI", 17, 0 },
  26. { "M0", 32, 0 },
  27. { "M1", 33, 0 },
  28. { "M2", 34, 0 },
  29. { "M3", 35, 0 },
  30. { "PTEVADDR", 83, 0 },
  31. { "MMID", 89, 0 },
  32. { "DDR", 104, 0 },
  33. { "176", 176, 0 },
  34. { "208", 208, 0 },
  35. { "INTERRUPT", 226, 0 },
  36. { "INTCLEAR", 227, 0 },
  37. { "CCOUNT", 234, 0 },
  38. { "PRID", 235, 0 },
  39. { "ICOUNT", 236, 0 },
  40. { "CCOMPARE0", 240, 0 },
  41. { "CCOMPARE1", 241, 0 },
  42. { "CCOMPARE2", 242, 0 },
  43. { "VECBASE", 231, 0 },
  44. { "EPC1", 177, 0 },
  45. { "EPC2", 178, 0 },
  46. { "EPC3", 179, 0 },
  47. { "EPC4", 180, 0 },
  48. { "EPC5", 181, 0 },
  49. { "EPC6", 182, 0 },
  50. { "EPC7", 183, 0 },
  51. { "EXCSAVE1", 209, 0 },
  52. { "EXCSAVE2", 210, 0 },
  53. { "EXCSAVE3", 211, 0 },
  54. { "EXCSAVE4", 212, 0 },
  55. { "EXCSAVE5", 213, 0 },
  56. { "EXCSAVE6", 214, 0 },
  57. { "EXCSAVE7", 215, 0 },
  58. { "EPS2", 194, 0 },
  59. { "EPS3", 195, 0 },
  60. { "EPS4", 196, 0 },
  61. { "EPS5", 197, 0 },
  62. { "EPS6", 198, 0 },
  63. { "EPS7", 199, 0 },
  64. { "EXCCAUSE", 232, 0 },
  65. { "DEPC", 192, 0 },
  66. { "EXCVADDR", 238, 0 },
  67. { "WINDOWBASE", 72, 0 },
  68. { "WINDOWSTART", 73, 0 },
  69. { "SAR", 3, 0 },
  70. { "LITBASE", 5, 0 },
  71. { "PS", 230, 0 },
  72. { "MISC0", 244, 0 },
  73. { "MISC1", 245, 0 },
  74. { "INTENABLE", 228, 0 },
  75. { "DBREAKA0", 144, 0 },
  76. { "DBREAKC0", 160, 0 },
  77. { "DBREAKA1", 145, 0 },
  78. { "DBREAKC1", 161, 0 },
  79. { "IBREAKA0", 128, 0 },
  80. { "IBREAKA1", 129, 0 },
  81. { "IBREAKENABLE", 96, 0 },
  82. { "ICOUNTLEVEL", 237, 0 },
  83. { "DEBUGCAUSE", 233, 0 },
  84. { "RASID", 90, 0 },
  85. { "ITLBCFG", 91, 0 },
  86. { "DTLBCFG", 92, 0 },
  87. { "CPENABLE", 224, 0 },
  88. { "SCOMPARE1", 12, 0 },
  89. { "THREADPTR", 231, 1 },
  90. { "EXPSTATE", 230, 1 }
  91. };
  92. #define NUM_SYSREGS 70
  93. #define MAX_SPECIAL_REG 245
  94. #define MAX_USER_REG 231
  95. /* Processor states. */
  96. static xtensa_state_internal states[] = {
  97. { "LCOUNT", 32, 0 },
  98. { "PC", 32, 0 },
  99. { "ICOUNT", 32, 0 },
  100. { "DDR", 32, 0 },
  101. { "INTERRUPT", 22, 0 },
  102. { "CCOUNT", 32, 0 },
  103. { "XTSYNC", 1, 0 },
  104. { "VECBASE", 22, 0 },
  105. { "EPC1", 32, 0 },
  106. { "EPC2", 32, 0 },
  107. { "EPC3", 32, 0 },
  108. { "EPC4", 32, 0 },
  109. { "EPC5", 32, 0 },
  110. { "EPC6", 32, 0 },
  111. { "EPC7", 32, 0 },
  112. { "EXCSAVE1", 32, 0 },
  113. { "EXCSAVE2", 32, 0 },
  114. { "EXCSAVE3", 32, 0 },
  115. { "EXCSAVE4", 32, 0 },
  116. { "EXCSAVE5", 32, 0 },
  117. { "EXCSAVE6", 32, 0 },
  118. { "EXCSAVE7", 32, 0 },
  119. { "EPS2", 15, 0 },
  120. { "EPS3", 15, 0 },
  121. { "EPS4", 15, 0 },
  122. { "EPS5", 15, 0 },
  123. { "EPS6", 15, 0 },
  124. { "EPS7", 15, 0 },
  125. { "EXCCAUSE", 6, 0 },
  126. { "PSINTLEVEL", 4, 0 },
  127. { "PSUM", 1, 0 },
  128. { "PSWOE", 1, 0 },
  129. { "PSRING", 2, 0 },
  130. { "PSEXCM", 1, 0 },
  131. { "DEPC", 32, 0 },
  132. { "EXCVADDR", 32, 0 },
  133. { "WindowBase", 3, 0 },
  134. { "WindowStart", 8, 0 },
  135. { "PSCALLINC", 2, 0 },
  136. { "PSOWB", 4, 0 },
  137. { "LBEG", 32, 0 },
  138. { "LEND", 32, 0 },
  139. { "SAR", 6, 0 },
  140. { "THREADPTR", 32, 0 },
  141. { "LITBADDR", 20, 0 },
  142. { "LITBEN", 1, 0 },
  143. { "MISC0", 32, 0 },
  144. { "MISC1", 32, 0 },
  145. { "ACC", 40, 0 },
  146. { "InOCDMode", 1, 0 },
  147. { "INTENABLE", 22, 0 },
  148. { "DBREAKA0", 32, 0 },
  149. { "DBREAKC0", 8, 0 },
  150. { "DBREAKA1", 32, 0 },
  151. { "DBREAKC1", 8, 0 },
  152. { "IBREAKA0", 32, 0 },
  153. { "IBREAKA1", 32, 0 },
  154. { "IBREAKENABLE", 2, 0 },
  155. { "ICOUNTLEVEL", 4, 0 },
  156. { "DEBUGCAUSE", 6, 0 },
  157. { "DBNUM", 4, 0 },
  158. { "CCOMPARE0", 32, 0 },
  159. { "CCOMPARE1", 32, 0 },
  160. { "CCOMPARE2", 32, 0 },
  161. { "ASID3", 8, 0 },
  162. { "ASID2", 8, 0 },
  163. { "ASID1", 8, 0 },
  164. { "INSTPGSZID4", 2, 0 },
  165. { "DATAPGSZID4", 2, 0 },
  166. { "PTBASE", 10, 0 },
  167. { "CPENABLE", 8, 0 },
  168. { "SCOMPARE1", 32, 0 },
  169. { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
  170. };
  171. #define NUM_STATES 73
  172. /* Macros for xtensa_state numbers (for use in iclasses because the
  173. state numbers are not available when the iclass table is generated). */
  174. #define STATE_LCOUNT 0
  175. #define STATE_PC 1
  176. #define STATE_ICOUNT 2
  177. #define STATE_DDR 3
  178. #define STATE_INTERRUPT 4
  179. #define STATE_CCOUNT 5
  180. #define STATE_XTSYNC 6
  181. #define STATE_VECBASE 7
  182. #define STATE_EPC1 8
  183. #define STATE_EPC2 9
  184. #define STATE_EPC3 10
  185. #define STATE_EPC4 11
  186. #define STATE_EPC5 12
  187. #define STATE_EPC6 13
  188. #define STATE_EPC7 14
  189. #define STATE_EXCSAVE1 15
  190. #define STATE_EXCSAVE2 16
  191. #define STATE_EXCSAVE3 17
  192. #define STATE_EXCSAVE4 18
  193. #define STATE_EXCSAVE5 19
  194. #define STATE_EXCSAVE6 20
  195. #define STATE_EXCSAVE7 21
  196. #define STATE_EPS2 22
  197. #define STATE_EPS3 23
  198. #define STATE_EPS4 24
  199. #define STATE_EPS5 25
  200. #define STATE_EPS6 26
  201. #define STATE_EPS7 27
  202. #define STATE_EXCCAUSE 28
  203. #define STATE_PSINTLEVEL 29
  204. #define STATE_PSUM 30
  205. #define STATE_PSWOE 31
  206. #define STATE_PSRING 32
  207. #define STATE_PSEXCM 33
  208. #define STATE_DEPC 34
  209. #define STATE_EXCVADDR 35
  210. #define STATE_WindowBase 36
  211. #define STATE_WindowStart 37
  212. #define STATE_PSCALLINC 38
  213. #define STATE_PSOWB 39
  214. #define STATE_LBEG 40
  215. #define STATE_LEND 41
  216. #define STATE_SAR 42
  217. #define STATE_THREADPTR 43
  218. #define STATE_LITBADDR 44
  219. #define STATE_LITBEN 45
  220. #define STATE_MISC0 46
  221. #define STATE_MISC1 47
  222. #define STATE_ACC 48
  223. #define STATE_InOCDMode 49
  224. #define STATE_INTENABLE 50
  225. #define STATE_DBREAKA0 51
  226. #define STATE_DBREAKC0 52
  227. #define STATE_DBREAKA1 53
  228. #define STATE_DBREAKC1 54
  229. #define STATE_IBREAKA0 55
  230. #define STATE_IBREAKA1 56
  231. #define STATE_IBREAKENABLE 57
  232. #define STATE_ICOUNTLEVEL 58
  233. #define STATE_DEBUGCAUSE 59
  234. #define STATE_DBNUM 60
  235. #define STATE_CCOMPARE0 61
  236. #define STATE_CCOMPARE1 62
  237. #define STATE_CCOMPARE2 63
  238. #define STATE_ASID3 64
  239. #define STATE_ASID2 65
  240. #define STATE_ASID1 66
  241. #define STATE_INSTPGSZID4 67
  242. #define STATE_DATAPGSZID4 68
  243. #define STATE_PTBASE 69
  244. #define STATE_CPENABLE 70
  245. #define STATE_SCOMPARE1 71
  246. #define STATE_EXPSTATE 72
  247. /* Field definitions. */
  248. static unsigned
  249. Field_t_Slot_inst_get (const xtensa_insnbuf insn)
  250. {
  251. unsigned tie_t = 0;
  252. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  253. return tie_t;
  254. }
  255. static void
  256. Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  257. {
  258. uint32 tie_t;
  259. tie_t = (val << 28) >> 28;
  260. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  261. }
  262. static unsigned
  263. Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
  264. {
  265. unsigned tie_t = 0;
  266. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  267. return tie_t;
  268. }
  269. static void
  270. Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  271. {
  272. uint32 tie_t;
  273. tie_t = (val << 28) >> 28;
  274. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  275. }
  276. static unsigned
  277. Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
  278. {
  279. unsigned tie_t = 0;
  280. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  281. return tie_t;
  282. }
  283. static void
  284. Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  285. {
  286. uint32 tie_t;
  287. tie_t = (val << 28) >> 28;
  288. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  289. }
  290. static unsigned
  291. Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
  292. {
  293. unsigned tie_t = 0;
  294. tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
  295. return tie_t;
  296. }
  297. static void
  298. Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  299. {
  300. uint32 tie_t;
  301. tie_t = (val << 31) >> 31;
  302. insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
  303. }
  304. static unsigned
  305. Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
  306. {
  307. unsigned tie_t = 0;
  308. tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
  309. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  310. return tie_t;
  311. }
  312. static void
  313. Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  314. {
  315. uint32 tie_t;
  316. tie_t = (val << 28) >> 28;
  317. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  318. tie_t = (val << 27) >> 31;
  319. insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
  320. }
  321. static unsigned
  322. Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
  323. {
  324. unsigned tie_t = 0;
  325. tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
  326. return tie_t;
  327. }
  328. static void
  329. Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  330. {
  331. uint32 tie_t;
  332. tie_t = (val << 20) >> 20;
  333. insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
  334. }
  335. static unsigned
  336. Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
  337. {
  338. unsigned tie_t = 0;
  339. tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
  340. return tie_t;
  341. }
  342. static void
  343. Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  344. {
  345. uint32 tie_t;
  346. tie_t = (val << 24) >> 24;
  347. insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
  348. }
  349. static unsigned
  350. Field_s_Slot_inst_get (const xtensa_insnbuf insn)
  351. {
  352. unsigned tie_t = 0;
  353. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  354. return tie_t;
  355. }
  356. static void
  357. Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  358. {
  359. uint32 tie_t;
  360. tie_t = (val << 28) >> 28;
  361. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  362. }
  363. static unsigned
  364. Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
  365. {
  366. unsigned tie_t = 0;
  367. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  368. return tie_t;
  369. }
  370. static void
  371. Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  372. {
  373. uint32 tie_t;
  374. tie_t = (val << 28) >> 28;
  375. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  376. }
  377. static unsigned
  378. Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
  379. {
  380. unsigned tie_t = 0;
  381. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  382. return tie_t;
  383. }
  384. static void
  385. Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  386. {
  387. uint32 tie_t;
  388. tie_t = (val << 28) >> 28;
  389. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  390. }
  391. static unsigned
  392. Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
  393. {
  394. unsigned tie_t = 0;
  395. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  396. tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
  397. return tie_t;
  398. }
  399. static void
  400. Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  401. {
  402. uint32 tie_t;
  403. tie_t = (val << 24) >> 24;
  404. insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
  405. tie_t = (val << 20) >> 28;
  406. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  407. }
  408. static unsigned
  409. Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
  410. {
  411. unsigned tie_t = 0;
  412. tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
  413. return tie_t;
  414. }
  415. static void
  416. Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  417. {
  418. uint32 tie_t;
  419. tie_t = (val << 16) >> 16;
  420. insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
  421. }
  422. static unsigned
  423. Field_m_Slot_inst_get (const xtensa_insnbuf insn)
  424. {
  425. unsigned tie_t = 0;
  426. tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
  427. return tie_t;
  428. }
  429. static void
  430. Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  431. {
  432. uint32 tie_t;
  433. tie_t = (val << 30) >> 30;
  434. insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
  435. }
  436. static unsigned
  437. Field_n_Slot_inst_get (const xtensa_insnbuf insn)
  438. {
  439. unsigned tie_t = 0;
  440. tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
  441. return tie_t;
  442. }
  443. static void
  444. Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  445. {
  446. uint32 tie_t;
  447. tie_t = (val << 30) >> 30;
  448. insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
  449. }
  450. static unsigned
  451. Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
  452. {
  453. unsigned tie_t = 0;
  454. tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
  455. return tie_t;
  456. }
  457. static void
  458. Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  459. {
  460. uint32 tie_t;
  461. tie_t = (val << 14) >> 14;
  462. insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
  463. }
  464. static unsigned
  465. Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
  466. {
  467. unsigned tie_t = 0;
  468. tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
  469. return tie_t;
  470. }
  471. static void
  472. Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  473. {
  474. uint32 tie_t;
  475. tie_t = (val << 28) >> 28;
  476. insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
  477. }
  478. static unsigned
  479. Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
  480. {
  481. unsigned tie_t = 0;
  482. tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
  483. return tie_t;
  484. }
  485. static void
  486. Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  487. {
  488. uint32 tie_t;
  489. tie_t = (val << 28) >> 28;
  490. insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
  491. }
  492. static unsigned
  493. Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
  494. {
  495. unsigned tie_t = 0;
  496. tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
  497. return tie_t;
  498. }
  499. static void
  500. Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  501. {
  502. uint32 tie_t;
  503. tie_t = (val << 28) >> 28;
  504. insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
  505. }
  506. static unsigned
  507. Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
  508. {
  509. unsigned tie_t = 0;
  510. tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
  511. return tie_t;
  512. }
  513. static void
  514. Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  515. {
  516. uint32 tie_t;
  517. tie_t = (val << 28) >> 28;
  518. insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
  519. }
  520. static unsigned
  521. Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
  522. {
  523. unsigned tie_t = 0;
  524. tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
  525. return tie_t;
  526. }
  527. static void
  528. Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  529. {
  530. uint32 tie_t;
  531. tie_t = (val << 28) >> 28;
  532. insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
  533. }
  534. static unsigned
  535. Field_r_Slot_inst_get (const xtensa_insnbuf insn)
  536. {
  537. unsigned tie_t = 0;
  538. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  539. return tie_t;
  540. }
  541. static void
  542. Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  543. {
  544. uint32 tie_t;
  545. tie_t = (val << 28) >> 28;
  546. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  547. }
  548. static unsigned
  549. Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
  550. {
  551. unsigned tie_t = 0;
  552. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  553. return tie_t;
  554. }
  555. static void
  556. Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  557. {
  558. uint32 tie_t;
  559. tie_t = (val << 28) >> 28;
  560. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  561. }
  562. static unsigned
  563. Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
  564. {
  565. unsigned tie_t = 0;
  566. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  567. return tie_t;
  568. }
  569. static void
  570. Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  571. {
  572. uint32 tie_t;
  573. tie_t = (val << 28) >> 28;
  574. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  575. }
  576. static unsigned
  577. Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
  578. {
  579. unsigned tie_t = 0;
  580. tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
  581. return tie_t;
  582. }
  583. static void
  584. Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  585. {
  586. uint32 tie_t;
  587. tie_t = (val << 31) >> 31;
  588. insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
  589. }
  590. static unsigned
  591. Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
  592. {
  593. unsigned tie_t = 0;
  594. tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
  595. return tie_t;
  596. }
  597. static void
  598. Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  599. {
  600. uint32 tie_t;
  601. tie_t = (val << 31) >> 31;
  602. insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
  603. }
  604. static unsigned
  605. Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
  606. {
  607. unsigned tie_t = 0;
  608. tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
  609. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  610. return tie_t;
  611. }
  612. static void
  613. Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  614. {
  615. uint32 tie_t;
  616. tie_t = (val << 28) >> 28;
  617. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  618. tie_t = (val << 27) >> 31;
  619. insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
  620. }
  621. static unsigned
  622. Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
  623. {
  624. unsigned tie_t = 0;
  625. tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
  626. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  627. return tie_t;
  628. }
  629. static void
  630. Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  631. {
  632. uint32 tie_t;
  633. tie_t = (val << 28) >> 28;
  634. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  635. tie_t = (val << 27) >> 31;
  636. insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
  637. }
  638. static unsigned
  639. Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
  640. {
  641. unsigned tie_t = 0;
  642. tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
  643. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  644. return tie_t;
  645. }
  646. static void
  647. Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  648. {
  649. uint32 tie_t;
  650. tie_t = (val << 28) >> 28;
  651. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  652. tie_t = (val << 27) >> 31;
  653. insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
  654. }
  655. static unsigned
  656. Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
  657. {
  658. unsigned tie_t = 0;
  659. tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
  660. return tie_t;
  661. }
  662. static void
  663. Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  664. {
  665. uint32 tie_t;
  666. tie_t = (val << 31) >> 31;
  667. insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
  668. }
  669. static unsigned
  670. Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
  671. {
  672. unsigned tie_t = 0;
  673. tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
  674. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  675. return tie_t;
  676. }
  677. static void
  678. Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  679. {
  680. uint32 tie_t;
  681. tie_t = (val << 28) >> 28;
  682. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  683. tie_t = (val << 27) >> 31;
  684. insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
  685. }
  686. static unsigned
  687. Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
  688. {
  689. unsigned tie_t = 0;
  690. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  691. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  692. return tie_t;
  693. }
  694. static void
  695. Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  696. {
  697. uint32 tie_t;
  698. tie_t = (val << 28) >> 28;
  699. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  700. tie_t = (val << 24) >> 28;
  701. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  702. }
  703. static unsigned
  704. Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
  705. {
  706. unsigned tie_t = 0;
  707. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  708. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  709. return tie_t;
  710. }
  711. static void
  712. Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  713. {
  714. uint32 tie_t;
  715. tie_t = (val << 28) >> 28;
  716. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  717. tie_t = (val << 24) >> 28;
  718. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  719. }
  720. static unsigned
  721. Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
  722. {
  723. unsigned tie_t = 0;
  724. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  725. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  726. return tie_t;
  727. }
  728. static void
  729. Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  730. {
  731. uint32 tie_t;
  732. tie_t = (val << 28) >> 28;
  733. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  734. tie_t = (val << 24) >> 28;
  735. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  736. }
  737. static unsigned
  738. Field_st_Slot_inst_get (const xtensa_insnbuf insn)
  739. {
  740. unsigned tie_t = 0;
  741. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  742. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  743. return tie_t;
  744. }
  745. static void
  746. Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  747. {
  748. uint32 tie_t;
  749. tie_t = (val << 28) >> 28;
  750. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  751. tie_t = (val << 24) >> 28;
  752. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  753. }
  754. static unsigned
  755. Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
  756. {
  757. unsigned tie_t = 0;
  758. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  759. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  760. return tie_t;
  761. }
  762. static void
  763. Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  764. {
  765. uint32 tie_t;
  766. tie_t = (val << 28) >> 28;
  767. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  768. tie_t = (val << 24) >> 28;
  769. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  770. }
  771. static unsigned
  772. Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
  773. {
  774. unsigned tie_t = 0;
  775. tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
  776. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  777. return tie_t;
  778. }
  779. static void
  780. Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  781. {
  782. uint32 tie_t;
  783. tie_t = (val << 28) >> 28;
  784. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  785. tie_t = (val << 24) >> 28;
  786. insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
  787. }
  788. static unsigned
  789. Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
  790. {
  791. unsigned tie_t = 0;
  792. tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
  793. return tie_t;
  794. }
  795. static void
  796. Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  797. {
  798. uint32 tie_t;
  799. tie_t = (val << 29) >> 29;
  800. insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
  801. }
  802. static unsigned
  803. Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
  804. {
  805. unsigned tie_t = 0;
  806. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  807. return tie_t;
  808. }
  809. static void
  810. Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  811. {
  812. uint32 tie_t;
  813. tie_t = (val << 28) >> 28;
  814. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  815. }
  816. static unsigned
  817. Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
  818. {
  819. unsigned tie_t = 0;
  820. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  821. return tie_t;
  822. }
  823. static void
  824. Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  825. {
  826. uint32 tie_t;
  827. tie_t = (val << 28) >> 28;
  828. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  829. }
  830. static unsigned
  831. Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
  832. {
  833. unsigned tie_t = 0;
  834. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  835. return tie_t;
  836. }
  837. static void
  838. Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  839. {
  840. uint32 tie_t;
  841. tie_t = (val << 28) >> 28;
  842. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  843. }
  844. static unsigned
  845. Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
  846. {
  847. unsigned tie_t = 0;
  848. tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
  849. tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
  850. return tie_t;
  851. }
  852. static void
  853. Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  854. {
  855. uint32 tie_t;
  856. tie_t = (val << 30) >> 30;
  857. insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
  858. tie_t = (val << 28) >> 30;
  859. insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
  860. }
  861. static unsigned
  862. Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
  863. {
  864. unsigned tie_t = 0;
  865. tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
  866. return tie_t;
  867. }
  868. static void
  869. Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  870. {
  871. uint32 tie_t;
  872. tie_t = (val << 31) >> 31;
  873. insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
  874. }
  875. static unsigned
  876. Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
  877. {
  878. unsigned tie_t = 0;
  879. tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
  880. return tie_t;
  881. }
  882. static void
  883. Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  884. {
  885. uint32 tie_t;
  886. tie_t = (val << 31) >> 31;
  887. insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
  888. }
  889. static unsigned
  890. Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
  891. {
  892. unsigned tie_t = 0;
  893. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  894. return tie_t;
  895. }
  896. static void
  897. Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  898. {
  899. uint32 tie_t;
  900. tie_t = (val << 28) >> 28;
  901. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  902. }
  903. static unsigned
  904. Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
  905. {
  906. unsigned tie_t = 0;
  907. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  908. return tie_t;
  909. }
  910. static void
  911. Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  912. {
  913. uint32 tie_t;
  914. tie_t = (val << 28) >> 28;
  915. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  916. }
  917. static unsigned
  918. Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
  919. {
  920. unsigned tie_t = 0;
  921. tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
  922. return tie_t;
  923. }
  924. static void
  925. Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  926. {
  927. uint32 tie_t;
  928. tie_t = (val << 30) >> 30;
  929. insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
  930. }
  931. static unsigned
  932. Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
  933. {
  934. unsigned tie_t = 0;
  935. tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
  936. return tie_t;
  937. }
  938. static void
  939. Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  940. {
  941. uint32 tie_t;
  942. tie_t = (val << 30) >> 30;
  943. insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
  944. }
  945. static unsigned
  946. Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
  947. {
  948. unsigned tie_t = 0;
  949. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  950. return tie_t;
  951. }
  952. static void
  953. Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  954. {
  955. uint32 tie_t;
  956. tie_t = (val << 28) >> 28;
  957. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  958. }
  959. static unsigned
  960. Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
  961. {
  962. unsigned tie_t = 0;
  963. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  964. return tie_t;
  965. }
  966. static void
  967. Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  968. {
  969. uint32 tie_t;
  970. tie_t = (val << 28) >> 28;
  971. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  972. }
  973. static unsigned
  974. Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
  975. {
  976. unsigned tie_t = 0;
  977. tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
  978. return tie_t;
  979. }
  980. static void
  981. Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  982. {
  983. uint32 tie_t;
  984. tie_t = (val << 29) >> 29;
  985. insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
  986. }
  987. static unsigned
  988. Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
  989. {
  990. unsigned tie_t = 0;
  991. tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
  992. return tie_t;
  993. }
  994. static void
  995. Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  996. {
  997. uint32 tie_t;
  998. tie_t = (val << 29) >> 29;
  999. insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
  1000. }
  1001. static unsigned
  1002. Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
  1003. {
  1004. unsigned tie_t = 0;
  1005. tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
  1006. return tie_t;
  1007. }
  1008. static void
  1009. Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  1010. {
  1011. uint32 tie_t;
  1012. tie_t = (val << 31) >> 31;
  1013. insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
  1014. }
  1015. static unsigned
  1016. Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
  1017. {
  1018. unsigned tie_t = 0;
  1019. tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
  1020. return tie_t;
  1021. }
  1022. static void
  1023. Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  1024. {
  1025. uint32 tie_t;
  1026. tie_t = (val << 31) >> 31;
  1027. insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
  1028. }
  1029. static unsigned
  1030. Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
  1031. {
  1032. unsigned tie_t = 0;
  1033. tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
  1034. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  1035. return tie_t;
  1036. }
  1037. static void
  1038. Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  1039. {
  1040. uint32 tie_t;
  1041. tie_t = (val << 28) >> 28;
  1042. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  1043. tie_t = (val << 26) >> 30;
  1044. insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
  1045. }
  1046. static unsigned
  1047. Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
  1048. {
  1049. unsigned tie_t = 0;
  1050. tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
  1051. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  1052. return tie_t;
  1053. }
  1054. static void
  1055. Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  1056. {
  1057. uint32 tie_t;
  1058. tie_t = (val << 28) >> 28;
  1059. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  1060. tie_t = (val << 26) >> 30;
  1061. insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
  1062. }
  1063. static unsigned
  1064. Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
  1065. {
  1066. unsigned tie_t = 0;
  1067. tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
  1068. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  1069. return tie_t;
  1070. }
  1071. static void
  1072. Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  1073. {
  1074. uint32 tie_t;
  1075. tie_t = (val << 28) >> 28;
  1076. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  1077. tie_t = (val << 25) >> 29;
  1078. insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
  1079. }
  1080. static unsigned
  1081. Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
  1082. {
  1083. unsigned tie_t = 0;
  1084. tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
  1085. tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
  1086. return tie_t;
  1087. }
  1088. static void
  1089. Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  1090. {
  1091. uint32 tie_t;
  1092. tie_t = (val << 28) >> 28;
  1093. insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
  1094. tie_t = (val << 25) >> 29;
  1095. insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
  1096. }
  1097. static unsigned
  1098. Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
  1099. {
  1100. unsigned tie_t = 0;
  1101. tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
  1102. return tie_t;
  1103. }
  1104. static void
  1105. Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1106. {
  1107. uint32 tie_t;
  1108. tie_t = (val << 31) >> 31;
  1109. insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
  1110. }
  1111. static unsigned
  1112. Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
  1113. {
  1114. unsigned tie_t = 0;
  1115. tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
  1116. return tie_t;
  1117. }
  1118. static void
  1119. Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1120. {
  1121. uint32 tie_t;
  1122. tie_t = (val << 31) >> 31;
  1123. insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
  1124. }
  1125. static unsigned
  1126. Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
  1127. {
  1128. unsigned tie_t = 0;
  1129. tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
  1130. return tie_t;
  1131. }
  1132. static void
  1133. Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1134. {
  1135. uint32 tie_t;
  1136. tie_t = (val << 30) >> 30;
  1137. insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
  1138. }
  1139. static unsigned
  1140. Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
  1141. {
  1142. unsigned tie_t = 0;
  1143. tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
  1144. return tie_t;
  1145. }
  1146. static void
  1147. Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1148. {
  1149. uint32 tie_t;
  1150. tie_t = (val << 31) >> 31;
  1151. insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
  1152. }
  1153. static unsigned
  1154. Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
  1155. {
  1156. unsigned tie_t = 0;
  1157. tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
  1158. return tie_t;
  1159. }
  1160. static void
  1161. Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1162. {
  1163. uint32 tie_t;
  1164. tie_t = (val << 31) >> 31;
  1165. insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
  1166. }
  1167. static unsigned
  1168. Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
  1169. {
  1170. unsigned tie_t = 0;
  1171. tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
  1172. return tie_t;
  1173. }
  1174. static void
  1175. Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1176. {
  1177. uint32 tie_t;
  1178. tie_t = (val << 30) >> 30;
  1179. insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
  1180. }
  1181. static unsigned
  1182. Field_w_Slot_inst_get (const xtensa_insnbuf insn)
  1183. {
  1184. unsigned tie_t = 0;
  1185. tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
  1186. return tie_t;
  1187. }
  1188. static void
  1189. Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1190. {
  1191. uint32 tie_t;
  1192. tie_t = (val << 30) >> 30;
  1193. insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
  1194. }
  1195. static unsigned
  1196. Field_y_Slot_inst_get (const xtensa_insnbuf insn)
  1197. {
  1198. unsigned tie_t = 0;
  1199. tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
  1200. return tie_t;
  1201. }
  1202. static void
  1203. Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1204. {
  1205. uint32 tie_t;
  1206. tie_t = (val << 31) >> 31;
  1207. insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
  1208. }
  1209. static unsigned
  1210. Field_x_Slot_inst_get (const xtensa_insnbuf insn)
  1211. {
  1212. unsigned tie_t = 0;
  1213. tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
  1214. return tie_t;
  1215. }
  1216. static void
  1217. Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1218. {
  1219. uint32 tie_t;
  1220. tie_t = (val << 31) >> 31;
  1221. insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
  1222. }
  1223. static unsigned
  1224. Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
  1225. {
  1226. unsigned tie_t = 0;
  1227. tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
  1228. return tie_t;
  1229. }
  1230. static void
  1231. Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1232. {
  1233. uint32 tie_t;
  1234. tie_t = (val << 17) >> 17;
  1235. insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
  1236. }
  1237. static unsigned
  1238. Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
  1239. {
  1240. unsigned tie_t = 0;
  1241. tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
  1242. return tie_t;
  1243. }
  1244. static void
  1245. Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1246. {
  1247. uint32 tie_t;
  1248. tie_t = (val << 14) >> 14;
  1249. insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
  1250. }
  1251. static unsigned
  1252. Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
  1253. {
  1254. unsigned tie_t = 0;
  1255. tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
  1256. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  1257. return tie_t;
  1258. }
  1259. static void
  1260. Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1261. {
  1262. uint32 tie_t;
  1263. tie_t = (val << 28) >> 28;
  1264. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  1265. tie_t = (val << 27) >> 31;
  1266. insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
  1267. }
  1268. static unsigned
  1269. Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
  1270. {
  1271. unsigned tie_t = 0;
  1272. tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
  1273. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  1274. return tie_t;
  1275. }
  1276. static void
  1277. Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  1278. {
  1279. uint32 tie_t;
  1280. tie_t = (val << 28) >> 28;
  1281. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  1282. tie_t = (val << 27) >> 31;
  1283. insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
  1284. }
  1285. static unsigned
  1286. Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
  1287. {
  1288. unsigned tie_t = 0;
  1289. tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
  1290. tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
  1291. return tie_t;
  1292. }
  1293. static void
  1294. Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  1295. {
  1296. uint32 tie_t;
  1297. tie_t = (val << 28) >> 28;
  1298. insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
  1299. tie_t = (val << 27) >> 31;
  1300. insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
  1301. }
  1302. static unsigned
  1303. Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
  1304. {
  1305. unsigned tie_t = 0;
  1306. tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
  1307. return tie_t;
  1308. }
  1309. static void
  1310. Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
  1311. {
  1312. uint32 tie_t;
  1313. tie_t = (val << 29) >> 29;
  1314. insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
  1315. }
  1316. static unsigned
  1317. Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
  1318. {
  1319. unsigned tie_t = 0;
  1320. tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
  1321. return tie_t;
  1322. }
  1323. static void
  1324. Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
  1325. {
  1326. uint32 tie_t;
  1327. tie_t = (val << 29) >> 29;
  1328. insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
  1329. }
  1330. static unsigned
  1331. Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
  1332. {
  1333. unsigned tie_t = 0;
  1334. tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
  1335. return tie_t;
  1336. }
  1337. static void
  1338. Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
  1339. {
  1340. uint32 tie_t;
  1341. tie_t = (val << 29) >> 29;
  1342. insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
  1343. }
  1344. static void
  1345. Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
  1346. uint32 val ATTRIBUTE_UNUSED)
  1347. {
  1348. /* Do nothing. */
  1349. }
  1350. static unsigned
  1351. Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
  1352. {
  1353. return 0;
  1354. }
  1355. static unsigned
  1356. Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
  1357. {
  1358. return 4;
  1359. }
  1360. static unsigned
  1361. Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
  1362. {
  1363. return 8;
  1364. }
  1365. static unsigned
  1366. Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
  1367. {
  1368. return 12;
  1369. }
  1370. static unsigned
  1371. Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
  1372. {
  1373. return 0;
  1374. }
  1375. static unsigned
  1376. Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
  1377. {
  1378. return 1;
  1379. }
  1380. static unsigned
  1381. Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
  1382. {
  1383. return 2;
  1384. }
  1385. static unsigned
  1386. Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
  1387. {
  1388. return 3;
  1389. }
  1390. /* Functional units. */
  1391. static xtensa_funcUnit_internal funcUnits[] = {
  1392. };
  1393. /* Register files. */
  1394. static xtensa_regfile_internal regfiles[] = {
  1395. { "AR", "a", 0, 32, 32 },
  1396. { "MR", "m", 1, 32, 4 }
  1397. };
  1398. /* Interfaces. */
  1399. static xtensa_interface_internal interfaces[] = {
  1400. { "IMPWIRE", 32, 0, 0, 'i' }
  1401. };
  1402. /* Constant tables. */
  1403. /* constant table ai4c */
  1404. static const unsigned CONST_TBL_ai4c_0[] = {
  1405. 0xffffffff,
  1406. 0x1,
  1407. 0x2,
  1408. 0x3,
  1409. 0x4,
  1410. 0x5,
  1411. 0x6,
  1412. 0x7,
  1413. 0x8,
  1414. 0x9,
  1415. 0xa,
  1416. 0xb,
  1417. 0xc,
  1418. 0xd,
  1419. 0xe,
  1420. 0xf,
  1421. 0
  1422. };
  1423. /* constant table b4c */
  1424. static const unsigned CONST_TBL_b4c_0[] = {
  1425. 0xffffffff,
  1426. 0x1,
  1427. 0x2,
  1428. 0x3,
  1429. 0x4,
  1430. 0x5,
  1431. 0x6,
  1432. 0x7,
  1433. 0x8,
  1434. 0xa,
  1435. 0xc,
  1436. 0x10,
  1437. 0x20,
  1438. 0x40,
  1439. 0x80,
  1440. 0x100,
  1441. 0
  1442. };
  1443. /* constant table b4cu */
  1444. static const unsigned CONST_TBL_b4cu_0[] = {
  1445. 0x8000,
  1446. 0x10000,
  1447. 0x2,
  1448. 0x3,
  1449. 0x4,
  1450. 0x5,
  1451. 0x6,
  1452. 0x7,
  1453. 0x8,
  1454. 0xa,
  1455. 0xc,
  1456. 0x10,
  1457. 0x20,
  1458. 0x40,
  1459. 0x80,
  1460. 0x100,
  1461. 0
  1462. };
  1463. /* Instruction operands. */
  1464. static int
  1465. Operand_soffsetx4_decode (uint32 *valp)
  1466. {
  1467. unsigned soffsetx4_0, offset_0;
  1468. offset_0 = *valp & 0x3ffff;
  1469. soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
  1470. *valp = soffsetx4_0;
  1471. return 0;
  1472. }
  1473. static int
  1474. Operand_soffsetx4_encode (uint32 *valp)
  1475. {
  1476. unsigned offset_0, soffsetx4_0;
  1477. soffsetx4_0 = *valp;
  1478. offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
  1479. *valp = offset_0;
  1480. return 0;
  1481. }
  1482. static int
  1483. Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
  1484. {
  1485. *valp -= (pc & ~0x3);
  1486. return 0;
  1487. }
  1488. static int
  1489. Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
  1490. {
  1491. *valp += (pc & ~0x3);
  1492. return 0;
  1493. }
  1494. static int
  1495. Operand_uimm12x8_decode (uint32 *valp)
  1496. {
  1497. unsigned uimm12x8_0, imm12_0;
  1498. imm12_0 = *valp & 0xfff;
  1499. uimm12x8_0 = imm12_0 << 3;
  1500. *valp = uimm12x8_0;
  1501. return 0;
  1502. }
  1503. static int
  1504. Operand_uimm12x8_encode (uint32 *valp)
  1505. {
  1506. unsigned imm12_0, uimm12x8_0;
  1507. uimm12x8_0 = *valp;
  1508. imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
  1509. *valp = imm12_0;
  1510. return 0;
  1511. }
  1512. static int
  1513. Operand_simm4_decode (uint32 *valp)
  1514. {
  1515. unsigned simm4_0, mn_0;
  1516. mn_0 = *valp & 0xf;
  1517. simm4_0 = ((int) mn_0 << 28) >> 28;
  1518. *valp = simm4_0;
  1519. return 0;
  1520. }
  1521. static int
  1522. Operand_simm4_encode (uint32 *valp)
  1523. {
  1524. unsigned mn_0, simm4_0;
  1525. simm4_0 = *valp;
  1526. mn_0 = (simm4_0 & 0xf);
  1527. *valp = mn_0;
  1528. return 0;
  1529. }
  1530. static int
  1531. Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
  1532. {
  1533. return 0;
  1534. }
  1535. static int
  1536. Operand_arr_encode (uint32 *valp)
  1537. {
  1538. return (*valp & ~0xf) != 0;
  1539. }
  1540. static int
  1541. Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
  1542. {
  1543. return 0;
  1544. }
  1545. static int
  1546. Operand_ars_encode (uint32 *valp)
  1547. {
  1548. return (*valp & ~0xf) != 0;
  1549. }
  1550. static int
  1551. Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
  1552. {
  1553. return 0;
  1554. }
  1555. static int
  1556. Operand_art_encode (uint32 *valp)
  1557. {
  1558. return (*valp & ~0xf) != 0;
  1559. }
  1560. static int
  1561. Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
  1562. {
  1563. return 0;
  1564. }
  1565. static int
  1566. Operand_ar0_encode (uint32 *valp)
  1567. {
  1568. return (*valp & ~0x1f) != 0;
  1569. }
  1570. static int
  1571. Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
  1572. {
  1573. return 0;
  1574. }
  1575. static int
  1576. Operand_ar4_encode (uint32 *valp)
  1577. {
  1578. return (*valp & ~0x1f) != 0;
  1579. }
  1580. static int
  1581. Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
  1582. {
  1583. return 0;
  1584. }
  1585. static int
  1586. Operand_ar8_encode (uint32 *valp)
  1587. {
  1588. return (*valp & ~0x1f) != 0;
  1589. }
  1590. static int
  1591. Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
  1592. {
  1593. return 0;
  1594. }
  1595. static int
  1596. Operand_ar12_encode (uint32 *valp)
  1597. {
  1598. return (*valp & ~0x1f) != 0;
  1599. }
  1600. static int
  1601. Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
  1602. {
  1603. return 0;
  1604. }
  1605. static int
  1606. Operand_ars_entry_encode (uint32 *valp)
  1607. {
  1608. return (*valp & ~0x1f) != 0;
  1609. }
  1610. static int
  1611. Operand_immrx4_decode (uint32 *valp)
  1612. {
  1613. unsigned immrx4_0, r_0;
  1614. r_0 = *valp & 0xf;
  1615. immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
  1616. *valp = immrx4_0;
  1617. return 0;
  1618. }
  1619. static int
  1620. Operand_immrx4_encode (uint32 *valp)
  1621. {
  1622. unsigned r_0, immrx4_0;
  1623. immrx4_0 = *valp;
  1624. r_0 = ((immrx4_0 >> 2) & 0xf);
  1625. *valp = r_0;
  1626. return 0;
  1627. }
  1628. static int
  1629. Operand_lsi4x4_decode (uint32 *valp)
  1630. {
  1631. unsigned lsi4x4_0, r_0;
  1632. r_0 = *valp & 0xf;
  1633. lsi4x4_0 = r_0 << 2;
  1634. *valp = lsi4x4_0;
  1635. return 0;
  1636. }
  1637. static int
  1638. Operand_lsi4x4_encode (uint32 *valp)
  1639. {
  1640. unsigned r_0, lsi4x4_0;
  1641. lsi4x4_0 = *valp;
  1642. r_0 = ((lsi4x4_0 >> 2) & 0xf);
  1643. *valp = r_0;
  1644. return 0;
  1645. }
  1646. static int
  1647. Operand_simm7_decode (uint32 *valp)
  1648. {
  1649. unsigned simm7_0, imm7_0;
  1650. imm7_0 = *valp & 0x7f;
  1651. simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
  1652. *valp = simm7_0;
  1653. return 0;
  1654. }
  1655. static int
  1656. Operand_simm7_encode (uint32 *valp)
  1657. {
  1658. unsigned imm7_0, simm7_0;
  1659. simm7_0 = *valp;
  1660. imm7_0 = (simm7_0 & 0x7f);
  1661. *valp = imm7_0;
  1662. return 0;
  1663. }
  1664. static int
  1665. Operand_uimm6_decode (uint32 *valp)
  1666. {
  1667. unsigned uimm6_0, imm6_0;
  1668. imm6_0 = *valp & 0x3f;
  1669. uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
  1670. *valp = uimm6_0;
  1671. return 0;
  1672. }
  1673. static int
  1674. Operand_uimm6_encode (uint32 *valp)
  1675. {
  1676. unsigned imm6_0, uimm6_0;
  1677. uimm6_0 = *valp;
  1678. imm6_0 = (uimm6_0 - 0x4) & 0x3f;
  1679. *valp = imm6_0;
  1680. return 0;
  1681. }
  1682. static int
  1683. Operand_uimm6_ator (uint32 *valp, uint32 pc)
  1684. {
  1685. *valp -= pc;
  1686. return 0;
  1687. }
  1688. static int
  1689. Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
  1690. {
  1691. *valp += pc;
  1692. return 0;
  1693. }
  1694. static int
  1695. Operand_ai4const_decode (uint32 *valp)
  1696. {
  1697. unsigned ai4const_0, t_0;
  1698. t_0 = *valp & 0xf;
  1699. ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
  1700. *valp = ai4const_0;
  1701. return 0;
  1702. }
  1703. static int
  1704. Operand_ai4const_encode (uint32 *valp)
  1705. {
  1706. unsigned t_0, ai4const_0;
  1707. ai4const_0 = *valp;
  1708. switch (ai4const_0)
  1709. {
  1710. case 0xffffffff: t_0 = 0; break;
  1711. case 0x1: t_0 = 0x1; break;
  1712. case 0x2: t_0 = 0x2; break;
  1713. case 0x3: t_0 = 0x3; break;
  1714. case 0x4: t_0 = 0x4; break;
  1715. case 0x5: t_0 = 0x5; break;
  1716. case 0x6: t_0 = 0x6; break;
  1717. case 0x7: t_0 = 0x7; break;
  1718. case 0x8: t_0 = 0x8; break;
  1719. case 0x9: t_0 = 0x9; break;
  1720. case 0xa: t_0 = 0xa; break;
  1721. case 0xb: t_0 = 0xb; break;
  1722. case 0xc: t_0 = 0xc; break;
  1723. case 0xd: t_0 = 0xd; break;
  1724. case 0xe: t_0 = 0xe; break;
  1725. default: t_0 = 0xf; break;
  1726. }
  1727. *valp = t_0;
  1728. return 0;
  1729. }
  1730. static int
  1731. Operand_b4const_decode (uint32 *valp)
  1732. {
  1733. unsigned b4const_0, r_0;
  1734. r_0 = *valp & 0xf;
  1735. b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
  1736. *valp = b4const_0;
  1737. return 0;
  1738. }
  1739. static int
  1740. Operand_b4const_encode (uint32 *valp)
  1741. {
  1742. unsigned r_0, b4const_0;
  1743. b4const_0 = *valp;
  1744. switch (b4const_0)
  1745. {
  1746. case 0xffffffff: r_0 = 0; break;
  1747. case 0x1: r_0 = 0x1; break;
  1748. case 0x2: r_0 = 0x2; break;
  1749. case 0x3: r_0 = 0x3; break;
  1750. case 0x4: r_0 = 0x4; break;
  1751. case 0x5: r_0 = 0x5; break;
  1752. case 0x6: r_0 = 0x6; break;
  1753. case 0x7: r_0 = 0x7; break;
  1754. case 0x8: r_0 = 0x8; break;
  1755. case 0xa: r_0 = 0x9; break;
  1756. case 0xc: r_0 = 0xa; break;
  1757. case 0x10: r_0 = 0xb; break;
  1758. case 0x20: r_0 = 0xc; break;
  1759. case 0x40: r_0 = 0xd; break;
  1760. case 0x80: r_0 = 0xe; break;
  1761. default: r_0 = 0xf; break;
  1762. }
  1763. *valp = r_0;
  1764. return 0;
  1765. }
  1766. static int
  1767. Operand_b4constu_decode (uint32 *valp)
  1768. {
  1769. unsigned b4constu_0, r_0;
  1770. r_0 = *valp & 0xf;
  1771. b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
  1772. *valp = b4constu_0;
  1773. return 0;
  1774. }
  1775. static int
  1776. Operand_b4constu_encode (uint32 *valp)
  1777. {
  1778. unsigned r_0, b4constu_0;
  1779. b4constu_0 = *valp;
  1780. switch (b4constu_0)
  1781. {
  1782. case 0x8000: r_0 = 0; break;
  1783. case 0x10000: r_0 = 0x1; break;
  1784. case 0x2: r_0 = 0x2; break;
  1785. case 0x3: r_0 = 0x3; break;
  1786. case 0x4: r_0 = 0x4; break;
  1787. case 0x5: r_0 = 0x5; break;
  1788. case 0x6: r_0 = 0x6; break;
  1789. case 0x7: r_0 = 0x7; break;
  1790. case 0x8: r_0 = 0x8; break;
  1791. case 0xa: r_0 = 0x9; break;
  1792. case 0xc: r_0 = 0xa; break;
  1793. case 0x10: r_0 = 0xb; break;
  1794. case 0x20: r_0 = 0xc; break;
  1795. case 0x40: r_0 = 0xd; break;
  1796. case 0x80: r_0 = 0xe; break;
  1797. default: r_0 = 0xf; break;
  1798. }
  1799. *valp = r_0;
  1800. return 0;
  1801. }
  1802. static int
  1803. Operand_uimm8_decode (uint32 *valp)
  1804. {
  1805. unsigned uimm8_0, imm8_0;
  1806. imm8_0 = *valp & 0xff;
  1807. uimm8_0 = imm8_0;
  1808. *valp = uimm8_0;
  1809. return 0;
  1810. }
  1811. static int
  1812. Operand_uimm8_encode (uint32 *valp)
  1813. {
  1814. unsigned imm8_0, uimm8_0;
  1815. uimm8_0 = *valp;
  1816. imm8_0 = (uimm8_0 & 0xff);
  1817. *valp = imm8_0;
  1818. return 0;
  1819. }
  1820. static int
  1821. Operand_uimm8x2_decode (uint32 *valp)
  1822. {
  1823. unsigned uimm8x2_0, imm8_0;
  1824. imm8_0 = *valp & 0xff;
  1825. uimm8x2_0 = imm8_0 << 1;
  1826. *valp = uimm8x2_0;
  1827. return 0;
  1828. }
  1829. static int
  1830. Operand_uimm8x2_encode (uint32 *valp)
  1831. {
  1832. unsigned imm8_0, uimm8x2_0;
  1833. uimm8x2_0 = *valp;
  1834. imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
  1835. *valp = imm8_0;
  1836. return 0;
  1837. }
  1838. static int
  1839. Operand_uimm8x4_decode (uint32 *valp)
  1840. {
  1841. unsigned uimm8x4_0, imm8_0;
  1842. imm8_0 = *valp & 0xff;
  1843. uimm8x4_0 = imm8_0 << 2;
  1844. *valp = uimm8x4_0;
  1845. return 0;
  1846. }
  1847. static int
  1848. Operand_uimm8x4_encode (uint32 *valp)
  1849. {
  1850. unsigned imm8_0, uimm8x4_0;
  1851. uimm8x4_0 = *valp;
  1852. imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
  1853. *valp = imm8_0;
  1854. return 0;
  1855. }
  1856. static int
  1857. Operand_uimm4x16_decode (uint32 *valp)
  1858. {
  1859. unsigned uimm4x16_0, op2_0;
  1860. op2_0 = *valp & 0xf;
  1861. uimm4x16_0 = op2_0 << 4;
  1862. *valp = uimm4x16_0;
  1863. return 0;
  1864. }
  1865. static int
  1866. Operand_uimm4x16_encode (uint32 *valp)
  1867. {
  1868. unsigned op2_0, uimm4x16_0;
  1869. uimm4x16_0 = *valp;
  1870. op2_0 = ((uimm4x16_0 >> 4) & 0xf);
  1871. *valp = op2_0;
  1872. return 0;
  1873. }
  1874. static int
  1875. Operand_simm8_decode (uint32 *valp)
  1876. {
  1877. unsigned simm8_0, imm8_0;
  1878. imm8_0 = *valp & 0xff;
  1879. simm8_0 = ((int) imm8_0 << 24) >> 24;
  1880. *valp = simm8_0;
  1881. return 0;
  1882. }
  1883. static int
  1884. Operand_simm8_encode (uint32 *valp)
  1885. {
  1886. unsigned imm8_0, simm8_0;
  1887. simm8_0 = *valp;
  1888. imm8_0 = (simm8_0 & 0xff);
  1889. *valp = imm8_0;
  1890. return 0;
  1891. }
  1892. static int
  1893. Operand_simm8x256_decode (uint32 *valp)
  1894. {
  1895. unsigned simm8x256_0, imm8_0;
  1896. imm8_0 = *valp & 0xff;
  1897. simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
  1898. *valp = simm8x256_0;
  1899. return 0;
  1900. }
  1901. static int
  1902. Operand_simm8x256_encode (uint32 *valp)
  1903. {
  1904. unsigned imm8_0, simm8x256_0;
  1905. simm8x256_0 = *valp;
  1906. imm8_0 = ((simm8x256_0 >> 8) & 0xff);
  1907. *valp = imm8_0;
  1908. return 0;
  1909. }
  1910. static int
  1911. Operand_simm12b_decode (uint32 *valp)
  1912. {
  1913. unsigned simm12b_0, imm12b_0;
  1914. imm12b_0 = *valp & 0xfff;
  1915. simm12b_0 = ((int) imm12b_0 << 20) >> 20;
  1916. *valp = simm12b_0;
  1917. return 0;
  1918. }
  1919. static int
  1920. Operand_simm12b_encode (uint32 *valp)
  1921. {
  1922. unsigned imm12b_0, simm12b_0;
  1923. simm12b_0 = *valp;
  1924. imm12b_0 = (simm12b_0 & 0xfff);
  1925. *valp = imm12b_0;
  1926. return 0;
  1927. }
  1928. static int
  1929. Operand_msalp32_decode (uint32 *valp)
  1930. {
  1931. unsigned msalp32_0, sal_0;
  1932. sal_0 = *valp & 0x1f;
  1933. msalp32_0 = 0x20 - sal_0;
  1934. *valp = msalp32_0;
  1935. return 0;
  1936. }
  1937. static int
  1938. Operand_msalp32_encode (uint32 *valp)
  1939. {
  1940. unsigned sal_0, msalp32_0;
  1941. msalp32_0 = *valp;
  1942. sal_0 = (0x20 - msalp32_0) & 0x1f;
  1943. *valp = sal_0;
  1944. return 0;
  1945. }
  1946. static int
  1947. Operand_op2p1_decode (uint32 *valp)
  1948. {
  1949. unsigned op2p1_0, op2_0;
  1950. op2_0 = *valp & 0xf;
  1951. op2p1_0 = op2_0 + 0x1;
  1952. *valp = op2p1_0;
  1953. return 0;
  1954. }
  1955. static int
  1956. Operand_op2p1_encode (uint32 *valp)
  1957. {
  1958. unsigned op2_0, op2p1_0;
  1959. op2p1_0 = *valp;
  1960. op2_0 = (op2p1_0 - 0x1) & 0xf;
  1961. *valp = op2_0;
  1962. return 0;
  1963. }
  1964. static int
  1965. Operand_label8_decode (uint32 *valp)
  1966. {
  1967. unsigned label8_0, imm8_0;
  1968. imm8_0 = *valp & 0xff;
  1969. label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
  1970. *valp = label8_0;
  1971. return 0;
  1972. }
  1973. static int
  1974. Operand_label8_encode (uint32 *valp)
  1975. {
  1976. unsigned imm8_0, label8_0;
  1977. label8_0 = *valp;
  1978. imm8_0 = (label8_0 - 0x4) & 0xff;
  1979. *valp = imm8_0;
  1980. return 0;
  1981. }
  1982. static int
  1983. Operand_label8_ator (uint32 *valp, uint32 pc)
  1984. {
  1985. *valp -= pc;
  1986. return 0;
  1987. }
  1988. static int
  1989. Operand_label8_rtoa (uint32 *valp, uint32 pc)
  1990. {
  1991. *valp += pc;
  1992. return 0;
  1993. }
  1994. static int
  1995. Operand_ulabel8_decode (uint32 *valp)
  1996. {
  1997. unsigned ulabel8_0, imm8_0;
  1998. imm8_0 = *valp & 0xff;
  1999. ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
  2000. *valp = ulabel8_0;
  2001. return 0;
  2002. }
  2003. static int
  2004. Operand_ulabel8_encode (uint32 *valp)
  2005. {
  2006. unsigned imm8_0, ulabel8_0;
  2007. ulabel8_0 = *valp;
  2008. imm8_0 = (ulabel8_0 - 0x4) & 0xff;
  2009. *valp = imm8_0;
  2010. return 0;
  2011. }
  2012. static int
  2013. Operand_ulabel8_ator (uint32 *valp, uint32 pc)
  2014. {
  2015. *valp -= pc;
  2016. return 0;
  2017. }
  2018. static int
  2019. Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
  2020. {
  2021. *valp += pc;
  2022. return 0;
  2023. }
  2024. static int
  2025. Operand_label12_decode (uint32 *valp)
  2026. {
  2027. unsigned label12_0, imm12_0;
  2028. imm12_0 = *valp & 0xfff;
  2029. label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
  2030. *valp = label12_0;
  2031. return 0;
  2032. }
  2033. static int
  2034. Operand_label12_encode (uint32 *valp)
  2035. {
  2036. unsigned imm12_0, label12_0;
  2037. label12_0 = *valp;
  2038. imm12_0 = (label12_0 - 0x4) & 0xfff;
  2039. *valp = imm12_0;
  2040. return 0;
  2041. }
  2042. static int
  2043. Operand_label12_ator (uint32 *valp, uint32 pc)
  2044. {
  2045. *valp -= pc;
  2046. return 0;
  2047. }
  2048. static int
  2049. Operand_label12_rtoa (uint32 *valp, uint32 pc)
  2050. {
  2051. *valp += pc;
  2052. return 0;
  2053. }
  2054. static int
  2055. Operand_soffset_decode (uint32 *valp)
  2056. {
  2057. unsigned soffset_0, offset_0;
  2058. offset_0 = *valp & 0x3ffff;
  2059. soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
  2060. *valp = soffset_0;
  2061. return 0;
  2062. }
  2063. static int
  2064. Operand_soffset_encode (uint32 *valp)
  2065. {
  2066. unsigned offset_0, soffset_0;
  2067. soffset_0 = *valp;
  2068. offset_0 = (soffset_0 - 0x4) & 0x3ffff;
  2069. *valp = offset_0;
  2070. return 0;
  2071. }
  2072. static int
  2073. Operand_soffset_ator (uint32 *valp, uint32 pc)
  2074. {
  2075. *valp -= pc;
  2076. return 0;
  2077. }
  2078. static int
  2079. Operand_soffset_rtoa (uint32 *valp, uint32 pc)
  2080. {
  2081. *valp += pc;
  2082. return 0;
  2083. }
  2084. static int
  2085. Operand_uimm16x4_decode (uint32 *valp)
  2086. {
  2087. unsigned uimm16x4_0, imm16_0;
  2088. imm16_0 = *valp & 0xffff;
  2089. uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
  2090. *valp = uimm16x4_0;
  2091. return 0;
  2092. }
  2093. static int
  2094. Operand_uimm16x4_encode (uint32 *valp)
  2095. {
  2096. unsigned imm16_0, uimm16x4_0;
  2097. uimm16x4_0 = *valp;
  2098. imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
  2099. *valp = imm16_0;
  2100. return 0;
  2101. }
  2102. static int
  2103. Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
  2104. {
  2105. *valp -= ((pc + 3) & ~0x3);
  2106. return 0;
  2107. }
  2108. static int
  2109. Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
  2110. {
  2111. *valp += ((pc + 3) & ~0x3);
  2112. return 0;
  2113. }
  2114. static int
  2115. Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
  2116. {
  2117. return 0;
  2118. }
  2119. static int
  2120. Operand_mx_encode (uint32 *valp)
  2121. {
  2122. return (*valp & ~0x3) != 0;
  2123. }
  2124. static int
  2125. Operand_my_decode (uint32 *valp)
  2126. {
  2127. *valp += 2;
  2128. return 0;
  2129. }
  2130. static int
  2131. Operand_my_encode (uint32 *valp)
  2132. {
  2133. int error;
  2134. error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
  2135. *valp = *valp & 1;
  2136. return error;
  2137. }
  2138. static int
  2139. Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
  2140. {
  2141. return 0;
  2142. }
  2143. static int
  2144. Operand_mw_encode (uint32 *valp)
  2145. {
  2146. return (*valp & ~0x3) != 0;
  2147. }
  2148. static int
  2149. Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
  2150. {
  2151. return 0;
  2152. }
  2153. static int
  2154. Operand_mr0_encode (uint32 *valp)
  2155. {
  2156. return (*valp & ~0x3) != 0;
  2157. }
  2158. static int
  2159. Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
  2160. {
  2161. return 0;
  2162. }
  2163. static int
  2164. Operand_mr1_encode (uint32 *valp)
  2165. {
  2166. return (*valp & ~0x3) != 0;
  2167. }
  2168. static int
  2169. Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
  2170. {
  2171. return 0;
  2172. }
  2173. static int
  2174. Operand_mr2_encode (uint32 *valp)
  2175. {
  2176. return (*valp & ~0x3) != 0;
  2177. }
  2178. static int
  2179. Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
  2180. {
  2181. return 0;
  2182. }
  2183. static int
  2184. Operand_mr3_encode (uint32 *valp)
  2185. {
  2186. return (*valp & ~0x3) != 0;
  2187. }
  2188. static int
  2189. Operand_immt_decode (uint32 *valp)
  2190. {
  2191. unsigned immt_0, t_0;
  2192. t_0 = *valp & 0xf;
  2193. immt_0 = t_0;
  2194. *valp = immt_0;
  2195. return 0;
  2196. }
  2197. static int
  2198. Operand_immt_encode (uint32 *valp)
  2199. {
  2200. unsigned t_0, immt_0;
  2201. immt_0 = *valp;
  2202. t_0 = immt_0 & 0xf;
  2203. *valp = t_0;
  2204. return 0;
  2205. }
  2206. static int
  2207. Operand_imms_decode (uint32 *valp)
  2208. {
  2209. unsigned imms_0, s_0;
  2210. s_0 = *valp & 0xf;
  2211. imms_0 = s_0;
  2212. *valp = imms_0;
  2213. return 0;
  2214. }
  2215. static int
  2216. Operand_imms_encode (uint32 *valp)
  2217. {
  2218. unsigned s_0, imms_0;
  2219. imms_0 = *valp;
  2220. s_0 = imms_0 & 0xf;
  2221. *valp = s_0;
  2222. return 0;
  2223. }
  2224. static int
  2225. Operand_tp7_decode (uint32 *valp)
  2226. {
  2227. unsigned tp7_0, t_0;
  2228. t_0 = *valp & 0xf;
  2229. tp7_0 = t_0 + 0x7;
  2230. *valp = tp7_0;
  2231. return 0;
  2232. }
  2233. static int
  2234. Operand_tp7_encode (uint32 *valp)
  2235. {
  2236. unsigned t_0, tp7_0;
  2237. tp7_0 = *valp;
  2238. t_0 = (tp7_0 - 0x7) & 0xf;
  2239. *valp = t_0;
  2240. return 0;
  2241. }
  2242. static int
  2243. Operand_xt_wbr15_label_decode (uint32 *valp)
  2244. {
  2245. unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
  2246. xt_wbr15_imm_0 = *valp & 0x7fff;
  2247. xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
  2248. *valp = xt_wbr15_label_0;
  2249. return 0;
  2250. }
  2251. static int
  2252. Operand_xt_wbr15_label_encode (uint32 *valp)
  2253. {
  2254. unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
  2255. xt_wbr15_label_0 = *valp;
  2256. xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
  2257. *valp = xt_wbr15_imm_0;
  2258. return 0;
  2259. }
  2260. static int
  2261. Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
  2262. {
  2263. *valp -= pc;
  2264. return 0;
  2265. }
  2266. static int
  2267. Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
  2268. {
  2269. *valp += pc;
  2270. return 0;
  2271. }
  2272. static int
  2273. Operand_xt_wbr18_label_decode (uint32 *valp)
  2274. {
  2275. unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
  2276. xt_wbr18_imm_0 = *valp & 0x3ffff;
  2277. xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
  2278. *valp = xt_wbr18_label_0;
  2279. return 0;
  2280. }
  2281. static int
  2282. Operand_xt_wbr18_label_encode (uint32 *valp)
  2283. {
  2284. unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
  2285. xt_wbr18_label_0 = *valp;
  2286. xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
  2287. *valp = xt_wbr18_imm_0;
  2288. return 0;
  2289. }
  2290. static int
  2291. Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
  2292. {
  2293. *valp -= pc;
  2294. return 0;
  2295. }
  2296. static int
  2297. Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
  2298. {
  2299. *valp += pc;
  2300. return 0;
  2301. }
  2302. static xtensa_operand_internal operands[] = {
  2303. { "soffsetx4", 10, -1, 0,
  2304. XTENSA_OPERAND_IS_PCRELATIVE,
  2305. Operand_soffsetx4_encode, Operand_soffsetx4_decode,
  2306. Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
  2307. { "uimm12x8", 3, -1, 0,
  2308. 0,
  2309. Operand_uimm12x8_encode, Operand_uimm12x8_decode,
  2310. 0, 0 },
  2311. { "simm4", 26, -1, 0,
  2312. 0,
  2313. Operand_simm4_encode, Operand_simm4_decode,
  2314. 0, 0 },
  2315. { "arr", 14, 0, 1,
  2316. XTENSA_OPERAND_IS_REGISTER,
  2317. Operand_arr_encode, Operand_arr_decode,
  2318. 0, 0 },
  2319. { "ars", 5, 0, 1,
  2320. XTENSA_OPERAND_IS_REGISTER,
  2321. Operand_ars_encode, Operand_ars_decode,
  2322. 0, 0 },
  2323. { "*ars_invisible", 5, 0, 1,
  2324. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
  2325. Operand_ars_encode, Operand_ars_decode,
  2326. 0, 0 },
  2327. { "art", 0, 0, 1,
  2328. XTENSA_OPERAND_IS_REGISTER,
  2329. Operand_art_encode, Operand_art_decode,
  2330. 0, 0 },
  2331. { "ar0", 48, 0, 1,
  2332. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
  2333. Operand_ar0_encode, Operand_ar0_decode,
  2334. 0, 0 },
  2335. { "ar4", 49, 0, 1,
  2336. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
  2337. Operand_ar4_encode, Operand_ar4_decode,
  2338. 0, 0 },
  2339. { "ar8", 50, 0, 1,
  2340. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
  2341. Operand_ar8_encode, Operand_ar8_decode,
  2342. 0, 0 },
  2343. { "ar12", 51, 0, 1,
  2344. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
  2345. Operand_ar12_encode, Operand_ar12_decode,
  2346. 0, 0 },
  2347. { "ars_entry", 5, 0, 1,
  2348. XTENSA_OPERAND_IS_REGISTER,
  2349. Operand_ars_entry_encode, Operand_ars_entry_decode,
  2350. 0, 0 },
  2351. { "immrx4", 14, -1, 0,
  2352. 0,
  2353. Operand_immrx4_encode, Operand_immrx4_decode,
  2354. 0, 0 },
  2355. { "lsi4x4", 14, -1, 0,
  2356. 0,
  2357. Operand_lsi4x4_encode, Operand_lsi4x4_decode,
  2358. 0, 0 },
  2359. { "simm7", 34, -1, 0,
  2360. 0,
  2361. Operand_simm7_encode, Operand_simm7_decode,
  2362. 0, 0 },
  2363. { "uimm6", 33, -1, 0,
  2364. XTENSA_OPERAND_IS_PCRELATIVE,
  2365. Operand_uimm6_encode, Operand_uimm6_decode,
  2366. Operand_uimm6_ator, Operand_uimm6_rtoa },
  2367. { "ai4const", 0, -1, 0,
  2368. 0,
  2369. Operand_ai4const_encode, Operand_ai4const_decode,
  2370. 0, 0 },
  2371. { "b4const", 14, -1, 0,
  2372. 0,
  2373. Operand_b4const_encode, Operand_b4const_decode,
  2374. 0, 0 },
  2375. { "b4constu", 14, -1, 0,
  2376. 0,
  2377. Operand_b4constu_encode, Operand_b4constu_decode,
  2378. 0, 0 },
  2379. { "uimm8", 4, -1, 0,
  2380. 0,
  2381. Operand_uimm8_encode, Operand_uimm8_decode,
  2382. 0, 0 },
  2383. { "uimm8x2", 4, -1, 0,
  2384. 0,
  2385. Operand_uimm8x2_encode, Operand_uimm8x2_decode,
  2386. 0, 0 },
  2387. { "uimm8x4", 4, -1, 0,
  2388. 0,
  2389. Operand_uimm8x4_encode, Operand_uimm8x4_decode,
  2390. 0, 0 },
  2391. { "uimm4x16", 13, -1, 0,
  2392. 0,
  2393. Operand_uimm4x16_encode, Operand_uimm4x16_decode,
  2394. 0, 0 },
  2395. { "simm8", 4, -1, 0,
  2396. 0,
  2397. Operand_simm8_encode, Operand_simm8_decode,
  2398. 0, 0 },
  2399. { "simm8x256", 4, -1, 0,
  2400. 0,
  2401. Operand_simm8x256_encode, Operand_simm8x256_decode,
  2402. 0, 0 },
  2403. { "simm12b", 6, -1, 0,
  2404. 0,
  2405. Operand_simm12b_encode, Operand_simm12b_decode,
  2406. 0, 0 },
  2407. { "msalp32", 18, -1, 0,
  2408. 0,
  2409. Operand_msalp32_encode, Operand_msalp32_decode,
  2410. 0, 0 },
  2411. { "op2p1", 13, -1, 0,
  2412. 0,
  2413. Operand_op2p1_encode, Operand_op2p1_decode,
  2414. 0, 0 },
  2415. { "label8", 4, -1, 0,
  2416. XTENSA_OPERAND_IS_PCRELATIVE,
  2417. Operand_label8_encode, Operand_label8_decode,
  2418. Operand_label8_ator, Operand_label8_rtoa },
  2419. { "ulabel8", 4, -1, 0,
  2420. XTENSA_OPERAND_IS_PCRELATIVE,
  2421. Operand_ulabel8_encode, Operand_ulabel8_decode,
  2422. Operand_ulabel8_ator, Operand_ulabel8_rtoa },
  2423. { "label12", 3, -1, 0,
  2424. XTENSA_OPERAND_IS_PCRELATIVE,
  2425. Operand_label12_encode, Operand_label12_decode,
  2426. Operand_label12_ator, Operand_label12_rtoa },
  2427. { "soffset", 10, -1, 0,
  2428. XTENSA_OPERAND_IS_PCRELATIVE,
  2429. Operand_soffset_encode, Operand_soffset_decode,
  2430. Operand_soffset_ator, Operand_soffset_rtoa },
  2431. { "uimm16x4", 7, -1, 0,
  2432. XTENSA_OPERAND_IS_PCRELATIVE,
  2433. Operand_uimm16x4_encode, Operand_uimm16x4_decode,
  2434. Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
  2435. { "mx", 43, 1, 1,
  2436. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
  2437. Operand_mx_encode, Operand_mx_decode,
  2438. 0, 0 },
  2439. { "my", 42, 1, 1,
  2440. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
  2441. Operand_my_encode, Operand_my_decode,
  2442. 0, 0 },
  2443. { "mw", 41, 1, 1,
  2444. XTENSA_OPERAND_IS_REGISTER,
  2445. Operand_mw_encode, Operand_mw_decode,
  2446. 0, 0 },
  2447. { "mr0", 52, 1, 1,
  2448. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
  2449. Operand_mr0_encode, Operand_mr0_decode,
  2450. 0, 0 },
  2451. { "mr1", 53, 1, 1,
  2452. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
  2453. Operand_mr1_encode, Operand_mr1_decode,
  2454. 0, 0 },
  2455. { "mr2", 54, 1, 1,
  2456. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
  2457. Operand_mr2_encode, Operand_mr2_decode,
  2458. 0, 0 },
  2459. { "mr3", 55, 1, 1,
  2460. XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
  2461. Operand_mr3_encode, Operand_mr3_decode,
  2462. 0, 0 },
  2463. { "immt", 0, -1, 0,
  2464. 0,
  2465. Operand_immt_encode, Operand_immt_decode,
  2466. 0, 0 },
  2467. { "imms", 5, -1, 0,
  2468. 0,
  2469. Operand_imms_encode, Operand_imms_decode,
  2470. 0, 0 },
  2471. { "tp7", 0, -1, 0,
  2472. 0,
  2473. Operand_tp7_encode, Operand_tp7_decode,
  2474. 0, 0 },
  2475. { "xt_wbr15_label", 44, -1, 0,
  2476. XTENSA_OPERAND_IS_PCRELATIVE,
  2477. Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
  2478. Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
  2479. { "xt_wbr18_label", 45, -1, 0,
  2480. XTENSA_OPERAND_IS_PCRELATIVE,
  2481. Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
  2482. Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
  2483. { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
  2484. { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
  2485. { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
  2486. { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
  2487. { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
  2488. { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
  2489. { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
  2490. { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
  2491. { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
  2492. { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
  2493. { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
  2494. { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
  2495. { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
  2496. { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
  2497. { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
  2498. { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
  2499. { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
  2500. { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
  2501. { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
  2502. { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
  2503. { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
  2504. { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
  2505. { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
  2506. { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
  2507. { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
  2508. { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
  2509. { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
  2510. { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
  2511. { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
  2512. { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
  2513. { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
  2514. { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
  2515. { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
  2516. { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
  2517. { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
  2518. { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
  2519. { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
  2520. { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
  2521. { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
  2522. { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
  2523. { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
  2524. { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
  2525. { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
  2526. { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
  2527. { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 },
  2528. { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 },
  2529. { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 },
  2530. { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 }
  2531. };
  2532. /* Iclass table. */
  2533. static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
  2534. { { STATE_PSRING }, 'i' },
  2535. { { STATE_PSEXCM }, 'm' },
  2536. { { STATE_EPC1 }, 'i' }
  2537. };
  2538. static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
  2539. { { STATE_PSEXCM }, 'i' },
  2540. { { STATE_PSRING }, 'i' },
  2541. { { STATE_DEPC }, 'i' }
  2542. };
  2543. static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
  2544. { { 0 /* soffsetx4 */ }, 'i' },
  2545. { { 10 /* ar12 */ }, 'o' }
  2546. };
  2547. static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
  2548. { { STATE_PSCALLINC }, 'o' }
  2549. };
  2550. static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
  2551. { { 0 /* soffsetx4 */ }, 'i' },
  2552. { { 9 /* ar8 */ }, 'o' }
  2553. };
  2554. static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
  2555. { { STATE_PSCALLINC }, 'o' }
  2556. };
  2557. static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
  2558. { { 0 /* soffsetx4 */ }, 'i' },
  2559. { { 8 /* ar4 */ }, 'o' }
  2560. };
  2561. static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
  2562. { { STATE_PSCALLINC }, 'o' }
  2563. };
  2564. static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
  2565. { { 4 /* ars */ }, 'i' },
  2566. { { 10 /* ar12 */ }, 'o' }
  2567. };
  2568. static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
  2569. { { STATE_PSCALLINC }, 'o' }
  2570. };
  2571. static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
  2572. { { 4 /* ars */ }, 'i' },
  2573. { { 9 /* ar8 */ }, 'o' }
  2574. };
  2575. static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
  2576. { { STATE_PSCALLINC }, 'o' }
  2577. };
  2578. static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
  2579. { { 4 /* ars */ }, 'i' },
  2580. { { 8 /* ar4 */ }, 'o' }
  2581. };
  2582. static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
  2583. { { STATE_PSCALLINC }, 'o' }
  2584. };
  2585. static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
  2586. { { 11 /* ars_entry */ }, 's' },
  2587. { { 4 /* ars */ }, 'i' },
  2588. { { 1 /* uimm12x8 */ }, 'i' }
  2589. };
  2590. static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
  2591. { { STATE_PSCALLINC }, 'i' },
  2592. { { STATE_PSEXCM }, 'i' },
  2593. { { STATE_PSWOE }, 'i' },
  2594. { { STATE_WindowBase }, 'm' },
  2595. { { STATE_WindowStart }, 'm' }
  2596. };
  2597. static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
  2598. { { 6 /* art */ }, 'o' },
  2599. { { 4 /* ars */ }, 'i' }
  2600. };
  2601. static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
  2602. { { STATE_WindowBase }, 'i' },
  2603. { { STATE_WindowStart }, 'i' }
  2604. };
  2605. static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
  2606. { { 2 /* simm4 */ }, 'i' }
  2607. };
  2608. static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
  2609. { { STATE_PSEXCM }, 'i' },
  2610. { { STATE_PSRING }, 'i' },
  2611. { { STATE_WindowBase }, 'm' }
  2612. };
  2613. static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
  2614. { { 5 /* *ars_invisible */ }, 'i' }
  2615. };
  2616. static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
  2617. { { STATE_WindowBase }, 'm' },
  2618. { { STATE_WindowStart }, 'm' },
  2619. { { STATE_PSEXCM }, 'i' },
  2620. { { STATE_PSWOE }, 'i' }
  2621. };
  2622. static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
  2623. { { STATE_EPC1 }, 'i' },
  2624. { { STATE_PSEXCM }, 'm' },
  2625. { { STATE_PSRING }, 'i' },
  2626. { { STATE_WindowBase }, 'm' },
  2627. { { STATE_WindowStart }, 'm' },
  2628. { { STATE_PSOWB }, 'i' }
  2629. };
  2630. static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
  2631. { { 6 /* art */ }, 'o' },
  2632. { { 4 /* ars */ }, 'i' },
  2633. { { 12 /* immrx4 */ }, 'i' }
  2634. };
  2635. static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
  2636. { { STATE_PSEXCM }, 'i' },
  2637. { { STATE_PSRING }, 'i' }
  2638. };
  2639. static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
  2640. { { 6 /* art */ }, 'i' },
  2641. { { 4 /* ars */ }, 'i' },
  2642. { { 12 /* immrx4 */ }, 'i' }
  2643. };
  2644. static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
  2645. { { STATE_PSEXCM }, 'i' },
  2646. { { STATE_PSRING }, 'i' }
  2647. };
  2648. static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
  2649. { { 6 /* art */ }, 'o' }
  2650. };
  2651. static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
  2652. { { STATE_PSEXCM }, 'i' },
  2653. { { STATE_PSRING }, 'i' },
  2654. { { STATE_WindowBase }, 'i' }
  2655. };
  2656. static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
  2657. { { 6 /* art */ }, 'i' }
  2658. };
  2659. static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
  2660. { { STATE_PSEXCM }, 'i' },
  2661. { { STATE_PSRING }, 'i' },
  2662. { { STATE_WindowBase }, 'o' }
  2663. };
  2664. static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
  2665. { { 6 /* art */ }, 'm' }
  2666. };
  2667. static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
  2668. { { STATE_PSEXCM }, 'i' },
  2669. { { STATE_PSRING }, 'i' },
  2670. { { STATE_WindowBase }, 'm' }
  2671. };
  2672. static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
  2673. { { 6 /* art */ }, 'o' }
  2674. };
  2675. static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
  2676. { { STATE_PSEXCM }, 'i' },
  2677. { { STATE_PSRING }, 'i' },
  2678. { { STATE_WindowStart }, 'i' }
  2679. };
  2680. static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
  2681. { { 6 /* art */ }, 'i' }
  2682. };
  2683. static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
  2684. { { STATE_PSEXCM }, 'i' },
  2685. { { STATE_PSRING }, 'i' },
  2686. { { STATE_WindowStart }, 'o' }
  2687. };
  2688. static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
  2689. { { 6 /* art */ }, 'm' }
  2690. };
  2691. static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
  2692. { { STATE_PSEXCM }, 'i' },
  2693. { { STATE_PSRING }, 'i' },
  2694. { { STATE_WindowStart }, 'm' }
  2695. };
  2696. static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
  2697. { { 3 /* arr */ }, 'o' },
  2698. { { 4 /* ars */ }, 'i' },
  2699. { { 6 /* art */ }, 'i' }
  2700. };
  2701. static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
  2702. { { 3 /* arr */ }, 'o' },
  2703. { { 4 /* ars */ }, 'i' },
  2704. { { 16 /* ai4const */ }, 'i' }
  2705. };
  2706. static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
  2707. { { 4 /* ars */ }, 'i' },
  2708. { { 15 /* uimm6 */ }, 'i' }
  2709. };
  2710. static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
  2711. { { 6 /* art */ }, 'o' },
  2712. { { 4 /* ars */ }, 'i' },
  2713. { { 13 /* lsi4x4 */ }, 'i' }
  2714. };
  2715. static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
  2716. { { 6 /* art */ }, 'o' },
  2717. { { 4 /* ars */ }, 'i' }
  2718. };
  2719. static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
  2720. { { 4 /* ars */ }, 'o' },
  2721. { { 14 /* simm7 */ }, 'i' }
  2722. };
  2723. static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
  2724. { { 5 /* *ars_invisible */ }, 'i' }
  2725. };
  2726. static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
  2727. { { 6 /* art */ }, 'i' },
  2728. { { 4 /* ars */ }, 'i' },
  2729. { { 13 /* lsi4x4 */ }, 'i' }
  2730. };
  2731. static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
  2732. { { 3 /* arr */ }, 'o' }
  2733. };
  2734. static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
  2735. { { STATE_THREADPTR }, 'i' }
  2736. };
  2737. static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
  2738. { { 6 /* art */ }, 'i' }
  2739. };
  2740. static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
  2741. { { STATE_THREADPTR }, 'o' }
  2742. };
  2743. static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
  2744. { { 6 /* art */ }, 'o' },
  2745. { { 4 /* ars */ }, 'i' },
  2746. { { 23 /* simm8 */ }, 'i' }
  2747. };
  2748. static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
  2749. { { 6 /* art */ }, 'o' },
  2750. { { 4 /* ars */ }, 'i' },
  2751. { { 24 /* simm8x256 */ }, 'i' }
  2752. };
  2753. static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
  2754. { { 3 /* arr */ }, 'o' },
  2755. { { 4 /* ars */ }, 'i' },
  2756. { { 6 /* art */ }, 'i' }
  2757. };
  2758. static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
  2759. { { 3 /* arr */ }, 'o' },
  2760. { { 4 /* ars */ }, 'i' },
  2761. { { 6 /* art */ }, 'i' }
  2762. };
  2763. static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
  2764. { { 4 /* ars */ }, 'i' },
  2765. { { 17 /* b4const */ }, 'i' },
  2766. { { 28 /* label8 */ }, 'i' }
  2767. };
  2768. static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
  2769. { { 4 /* ars */ }, 'i' },
  2770. { { 47 /* bbi */ }, 'i' },
  2771. { { 28 /* label8 */ }, 'i' }
  2772. };
  2773. static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
  2774. { { 4 /* ars */ }, 'i' },
  2775. { { 18 /* b4constu */ }, 'i' },
  2776. { { 28 /* label8 */ }, 'i' }
  2777. };
  2778. static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
  2779. { { 4 /* ars */ }, 'i' },
  2780. { { 6 /* art */ }, 'i' },
  2781. { { 28 /* label8 */ }, 'i' }
  2782. };
  2783. static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
  2784. { { 4 /* ars */ }, 'i' },
  2785. { { 30 /* label12 */ }, 'i' }
  2786. };
  2787. static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
  2788. { { 0 /* soffsetx4 */ }, 'i' },
  2789. { { 7 /* ar0 */ }, 'o' }
  2790. };
  2791. static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
  2792. { { 4 /* ars */ }, 'i' },
  2793. { { 7 /* ar0 */ }, 'o' }
  2794. };
  2795. static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
  2796. { { 3 /* arr */ }, 'o' },
  2797. { { 6 /* art */ }, 'i' },
  2798. { { 62 /* sae */ }, 'i' },
  2799. { { 27 /* op2p1 */ }, 'i' }
  2800. };
  2801. static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
  2802. { { 31 /* soffset */ }, 'i' }
  2803. };
  2804. static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
  2805. { { 4 /* ars */ }, 'i' }
  2806. };
  2807. static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
  2808. { { 6 /* art */ }, 'o' },
  2809. { { 4 /* ars */ }, 'i' },
  2810. { { 20 /* uimm8x2 */ }, 'i' }
  2811. };
  2812. static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
  2813. { { 6 /* art */ }, 'o' },
  2814. { { 4 /* ars */ }, 'i' },
  2815. { { 20 /* uimm8x2 */ }, 'i' }
  2816. };
  2817. static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
  2818. { { 6 /* art */ }, 'o' },
  2819. { { 4 /* ars */ }, 'i' },
  2820. { { 21 /* uimm8x4 */ }, 'i' }
  2821. };
  2822. static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
  2823. { { 6 /* art */ }, 'o' },
  2824. { { 32 /* uimm16x4 */ }, 'i' }
  2825. };
  2826. static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
  2827. { { STATE_LITBADDR }, 'i' },
  2828. { { STATE_LITBEN }, 'i' }
  2829. };
  2830. static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
  2831. { { 6 /* art */ }, 'o' },
  2832. { { 4 /* ars */ }, 'i' },
  2833. { { 19 /* uimm8 */ }, 'i' }
  2834. };
  2835. static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
  2836. { { 4 /* ars */ }, 'i' },
  2837. { { 29 /* ulabel8 */ }, 'i' }
  2838. };
  2839. static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
  2840. { { STATE_LBEG }, 'o' },
  2841. { { STATE_LEND }, 'o' },
  2842. { { STATE_LCOUNT }, 'o' }
  2843. };
  2844. static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
  2845. { { 4 /* ars */ }, 'i' },
  2846. { { 29 /* ulabel8 */ }, 'i' }
  2847. };
  2848. static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
  2849. { { STATE_LBEG }, 'o' },
  2850. { { STATE_LEND }, 'o' },
  2851. { { STATE_LCOUNT }, 'o' }
  2852. };
  2853. static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
  2854. { { 6 /* art */ }, 'o' },
  2855. { { 25 /* simm12b */ }, 'i' }
  2856. };
  2857. static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
  2858. { { 3 /* arr */ }, 'm' },
  2859. { { 4 /* ars */ }, 'i' },
  2860. { { 6 /* art */ }, 'i' }
  2861. };
  2862. static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
  2863. { { 3 /* arr */ }, 'o' },
  2864. { { 6 /* art */ }, 'i' }
  2865. };
  2866. static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
  2867. { { 5 /* *ars_invisible */ }, 'i' }
  2868. };
  2869. static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
  2870. { { 6 /* art */ }, 'i' },
  2871. { { 4 /* ars */ }, 'i' },
  2872. { { 20 /* uimm8x2 */ }, 'i' }
  2873. };
  2874. static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
  2875. { { 6 /* art */ }, 'i' },
  2876. { { 4 /* ars */ }, 'i' },
  2877. { { 21 /* uimm8x4 */ }, 'i' }
  2878. };
  2879. static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
  2880. { { 6 /* art */ }, 'i' },
  2881. { { 4 /* ars */ }, 'i' },
  2882. { { 19 /* uimm8 */ }, 'i' }
  2883. };
  2884. static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
  2885. { { 4 /* ars */ }, 'i' }
  2886. };
  2887. static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
  2888. { { STATE_SAR }, 'o' }
  2889. };
  2890. static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
  2891. { { 66 /* sas */ }, 'i' }
  2892. };
  2893. static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
  2894. { { STATE_SAR }, 'o' }
  2895. };
  2896. static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
  2897. { { 3 /* arr */ }, 'o' },
  2898. { { 4 /* ars */ }, 'i' }
  2899. };
  2900. static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
  2901. { { STATE_SAR }, 'i' }
  2902. };
  2903. static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
  2904. { { 3 /* arr */ }, 'o' },
  2905. { { 4 /* ars */ }, 'i' },
  2906. { { 6 /* art */ }, 'i' }
  2907. };
  2908. static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
  2909. { { STATE_SAR }, 'i' }
  2910. };
  2911. static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
  2912. { { 3 /* arr */ }, 'o' },
  2913. { { 6 /* art */ }, 'i' }
  2914. };
  2915. static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
  2916. { { STATE_SAR }, 'i' }
  2917. };
  2918. static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
  2919. { { 3 /* arr */ }, 'o' },
  2920. { { 4 /* ars */ }, 'i' },
  2921. { { 26 /* msalp32 */ }, 'i' }
  2922. };
  2923. static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
  2924. { { 3 /* arr */ }, 'o' },
  2925. { { 6 /* art */ }, 'i' },
  2926. { { 64 /* sargt */ }, 'i' }
  2927. };
  2928. static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
  2929. { { 3 /* arr */ }, 'o' },
  2930. { { 6 /* art */ }, 'i' },
  2931. { { 50 /* s */ }, 'i' }
  2932. };
  2933. static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
  2934. { { STATE_XTSYNC }, 'i' }
  2935. };
  2936. static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
  2937. { { 6 /* art */ }, 'o' },
  2938. { { 50 /* s */ }, 'i' }
  2939. };
  2940. static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
  2941. { { STATE_PSWOE }, 'i' },
  2942. { { STATE_PSCALLINC }, 'i' },
  2943. { { STATE_PSOWB }, 'i' },
  2944. { { STATE_PSRING }, 'i' },
  2945. { { STATE_PSUM }, 'i' },
  2946. { { STATE_PSEXCM }, 'i' },
  2947. { { STATE_PSINTLEVEL }, 'm' }
  2948. };
  2949. static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
  2950. { { 6 /* art */ }, 'o' }
  2951. };
  2952. static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
  2953. { { STATE_LEND }, 'i' }
  2954. };
  2955. static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
  2956. { { 6 /* art */ }, 'i' }
  2957. };
  2958. static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
  2959. { { STATE_LEND }, 'o' }
  2960. };
  2961. static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
  2962. { { 6 /* art */ }, 'm' }
  2963. };
  2964. static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
  2965. { { STATE_LEND }, 'm' }
  2966. };
  2967. static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
  2968. { { 6 /* art */ }, 'o' }
  2969. };
  2970. static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
  2971. { { STATE_LCOUNT }, 'i' }
  2972. };
  2973. static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
  2974. { { 6 /* art */ }, 'i' }
  2975. };
  2976. static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
  2977. { { STATE_XTSYNC }, 'o' },
  2978. { { STATE_LCOUNT }, 'o' }
  2979. };
  2980. static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
  2981. { { 6 /* art */ }, 'm' }
  2982. };
  2983. static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
  2984. { { STATE_XTSYNC }, 'o' },
  2985. { { STATE_LCOUNT }, 'm' }
  2986. };
  2987. static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
  2988. { { 6 /* art */ }, 'o' }
  2989. };
  2990. static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
  2991. { { STATE_LBEG }, 'i' }
  2992. };
  2993. static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
  2994. { { 6 /* art */ }, 'i' }
  2995. };
  2996. static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
  2997. { { STATE_LBEG }, 'o' }
  2998. };
  2999. static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
  3000. { { 6 /* art */ }, 'm' }
  3001. };
  3002. static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
  3003. { { STATE_LBEG }, 'm' }
  3004. };
  3005. static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
  3006. { { 6 /* art */ }, 'o' }
  3007. };
  3008. static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
  3009. { { STATE_SAR }, 'i' }
  3010. };
  3011. static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
  3012. { { 6 /* art */ }, 'i' }
  3013. };
  3014. static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
  3015. { { STATE_SAR }, 'o' },
  3016. { { STATE_XTSYNC }, 'o' }
  3017. };
  3018. static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
  3019. { { 6 /* art */ }, 'm' }
  3020. };
  3021. static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
  3022. { { STATE_SAR }, 'm' }
  3023. };
  3024. static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
  3025. { { 6 /* art */ }, 'o' }
  3026. };
  3027. static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
  3028. { { STATE_LITBADDR }, 'i' },
  3029. { { STATE_LITBEN }, 'i' }
  3030. };
  3031. static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
  3032. { { 6 /* art */ }, 'i' }
  3033. };
  3034. static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
  3035. { { STATE_LITBADDR }, 'o' },
  3036. { { STATE_LITBEN }, 'o' }
  3037. };
  3038. static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
  3039. { { 6 /* art */ }, 'm' }
  3040. };
  3041. static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
  3042. { { STATE_LITBADDR }, 'm' },
  3043. { { STATE_LITBEN }, 'm' }
  3044. };
  3045. static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
  3046. { { 6 /* art */ }, 'o' }
  3047. };
  3048. static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
  3049. { { STATE_PSEXCM }, 'i' },
  3050. { { STATE_PSRING }, 'i' }
  3051. };
  3052. static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
  3053. { { 6 /* art */ }, 'o' }
  3054. };
  3055. static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
  3056. { { STATE_PSEXCM }, 'i' },
  3057. { { STATE_PSRING }, 'i' }
  3058. };
  3059. static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
  3060. { { 6 /* art */ }, 'o' }
  3061. };
  3062. static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
  3063. { { STATE_PSWOE }, 'i' },
  3064. { { STATE_PSCALLINC }, 'i' },
  3065. { { STATE_PSOWB }, 'i' },
  3066. { { STATE_PSRING }, 'i' },
  3067. { { STATE_PSUM }, 'i' },
  3068. { { STATE_PSEXCM }, 'i' },
  3069. { { STATE_PSINTLEVEL }, 'i' }
  3070. };
  3071. static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
  3072. { { 6 /* art */ }, 'i' }
  3073. };
  3074. static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
  3075. { { STATE_PSWOE }, 'o' },
  3076. { { STATE_PSCALLINC }, 'o' },
  3077. { { STATE_PSOWB }, 'o' },
  3078. { { STATE_PSRING }, 'm' },
  3079. { { STATE_PSUM }, 'o' },
  3080. { { STATE_PSEXCM }, 'm' },
  3081. { { STATE_PSINTLEVEL }, 'o' }
  3082. };
  3083. static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
  3084. { { 6 /* art */ }, 'm' }
  3085. };
  3086. static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
  3087. { { STATE_PSWOE }, 'm' },
  3088. { { STATE_PSCALLINC }, 'm' },
  3089. { { STATE_PSOWB }, 'm' },
  3090. { { STATE_PSRING }, 'm' },
  3091. { { STATE_PSUM }, 'm' },
  3092. { { STATE_PSEXCM }, 'm' },
  3093. { { STATE_PSINTLEVEL }, 'm' }
  3094. };
  3095. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
  3096. { { 6 /* art */ }, 'o' }
  3097. };
  3098. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
  3099. { { STATE_PSEXCM }, 'i' },
  3100. { { STATE_PSRING }, 'i' },
  3101. { { STATE_EPC1 }, 'i' }
  3102. };
  3103. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
  3104. { { 6 /* art */ }, 'i' }
  3105. };
  3106. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
  3107. { { STATE_PSEXCM }, 'i' },
  3108. { { STATE_PSRING }, 'i' },
  3109. { { STATE_EPC1 }, 'o' }
  3110. };
  3111. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
  3112. { { 6 /* art */ }, 'm' }
  3113. };
  3114. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
  3115. { { STATE_PSEXCM }, 'i' },
  3116. { { STATE_PSRING }, 'i' },
  3117. { { STATE_EPC1 }, 'm' }
  3118. };
  3119. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
  3120. { { 6 /* art */ }, 'o' }
  3121. };
  3122. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
  3123. { { STATE_PSEXCM }, 'i' },
  3124. { { STATE_PSRING }, 'i' },
  3125. { { STATE_EXCSAVE1 }, 'i' }
  3126. };
  3127. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
  3128. { { 6 /* art */ }, 'i' }
  3129. };
  3130. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
  3131. { { STATE_PSEXCM }, 'i' },
  3132. { { STATE_PSRING }, 'i' },
  3133. { { STATE_EXCSAVE1 }, 'o' }
  3134. };
  3135. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
  3136. { { 6 /* art */ }, 'm' }
  3137. };
  3138. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
  3139. { { STATE_PSEXCM }, 'i' },
  3140. { { STATE_PSRING }, 'i' },
  3141. { { STATE_EXCSAVE1 }, 'm' }
  3142. };
  3143. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
  3144. { { 6 /* art */ }, 'o' }
  3145. };
  3146. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
  3147. { { STATE_PSEXCM }, 'i' },
  3148. { { STATE_PSRING }, 'i' },
  3149. { { STATE_EPC2 }, 'i' }
  3150. };
  3151. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
  3152. { { 6 /* art */ }, 'i' }
  3153. };
  3154. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
  3155. { { STATE_PSEXCM }, 'i' },
  3156. { { STATE_PSRING }, 'i' },
  3157. { { STATE_EPC2 }, 'o' }
  3158. };
  3159. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
  3160. { { 6 /* art */ }, 'm' }
  3161. };
  3162. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
  3163. { { STATE_PSEXCM }, 'i' },
  3164. { { STATE_PSRING }, 'i' },
  3165. { { STATE_EPC2 }, 'm' }
  3166. };
  3167. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
  3168. { { 6 /* art */ }, 'o' }
  3169. };
  3170. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
  3171. { { STATE_PSEXCM }, 'i' },
  3172. { { STATE_PSRING }, 'i' },
  3173. { { STATE_EXCSAVE2 }, 'i' }
  3174. };
  3175. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
  3176. { { 6 /* art */ }, 'i' }
  3177. };
  3178. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
  3179. { { STATE_PSEXCM }, 'i' },
  3180. { { STATE_PSRING }, 'i' },
  3181. { { STATE_EXCSAVE2 }, 'o' }
  3182. };
  3183. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
  3184. { { 6 /* art */ }, 'm' }
  3185. };
  3186. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
  3187. { { STATE_PSEXCM }, 'i' },
  3188. { { STATE_PSRING }, 'i' },
  3189. { { STATE_EXCSAVE2 }, 'm' }
  3190. };
  3191. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
  3192. { { 6 /* art */ }, 'o' }
  3193. };
  3194. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
  3195. { { STATE_PSEXCM }, 'i' },
  3196. { { STATE_PSRING }, 'i' },
  3197. { { STATE_EPC3 }, 'i' }
  3198. };
  3199. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
  3200. { { 6 /* art */ }, 'i' }
  3201. };
  3202. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
  3203. { { STATE_PSEXCM }, 'i' },
  3204. { { STATE_PSRING }, 'i' },
  3205. { { STATE_EPC3 }, 'o' }
  3206. };
  3207. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
  3208. { { 6 /* art */ }, 'm' }
  3209. };
  3210. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
  3211. { { STATE_PSEXCM }, 'i' },
  3212. { { STATE_PSRING }, 'i' },
  3213. { { STATE_EPC3 }, 'm' }
  3214. };
  3215. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
  3216. { { 6 /* art */ }, 'o' }
  3217. };
  3218. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
  3219. { { STATE_PSEXCM }, 'i' },
  3220. { { STATE_PSRING }, 'i' },
  3221. { { STATE_EXCSAVE3 }, 'i' }
  3222. };
  3223. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
  3224. { { 6 /* art */ }, 'i' }
  3225. };
  3226. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
  3227. { { STATE_PSEXCM }, 'i' },
  3228. { { STATE_PSRING }, 'i' },
  3229. { { STATE_EXCSAVE3 }, 'o' }
  3230. };
  3231. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
  3232. { { 6 /* art */ }, 'm' }
  3233. };
  3234. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
  3235. { { STATE_PSEXCM }, 'i' },
  3236. { { STATE_PSRING }, 'i' },
  3237. { { STATE_EXCSAVE3 }, 'm' }
  3238. };
  3239. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
  3240. { { 6 /* art */ }, 'o' }
  3241. };
  3242. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
  3243. { { STATE_PSEXCM }, 'i' },
  3244. { { STATE_PSRING }, 'i' },
  3245. { { STATE_EPC4 }, 'i' }
  3246. };
  3247. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
  3248. { { 6 /* art */ }, 'i' }
  3249. };
  3250. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
  3251. { { STATE_PSEXCM }, 'i' },
  3252. { { STATE_PSRING }, 'i' },
  3253. { { STATE_EPC4 }, 'o' }
  3254. };
  3255. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
  3256. { { 6 /* art */ }, 'm' }
  3257. };
  3258. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
  3259. { { STATE_PSEXCM }, 'i' },
  3260. { { STATE_PSRING }, 'i' },
  3261. { { STATE_EPC4 }, 'm' }
  3262. };
  3263. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
  3264. { { 6 /* art */ }, 'o' }
  3265. };
  3266. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
  3267. { { STATE_PSEXCM }, 'i' },
  3268. { { STATE_PSRING }, 'i' },
  3269. { { STATE_EXCSAVE4 }, 'i' }
  3270. };
  3271. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
  3272. { { 6 /* art */ }, 'i' }
  3273. };
  3274. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
  3275. { { STATE_PSEXCM }, 'i' },
  3276. { { STATE_PSRING }, 'i' },
  3277. { { STATE_EXCSAVE4 }, 'o' }
  3278. };
  3279. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
  3280. { { 6 /* art */ }, 'm' }
  3281. };
  3282. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
  3283. { { STATE_PSEXCM }, 'i' },
  3284. { { STATE_PSRING }, 'i' },
  3285. { { STATE_EXCSAVE4 }, 'm' }
  3286. };
  3287. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
  3288. { { 6 /* art */ }, 'o' }
  3289. };
  3290. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
  3291. { { STATE_PSEXCM }, 'i' },
  3292. { { STATE_PSRING }, 'i' },
  3293. { { STATE_EPC5 }, 'i' }
  3294. };
  3295. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
  3296. { { 6 /* art */ }, 'i' }
  3297. };
  3298. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
  3299. { { STATE_PSEXCM }, 'i' },
  3300. { { STATE_PSRING }, 'i' },
  3301. { { STATE_EPC5 }, 'o' }
  3302. };
  3303. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
  3304. { { 6 /* art */ }, 'm' }
  3305. };
  3306. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
  3307. { { STATE_PSEXCM }, 'i' },
  3308. { { STATE_PSRING }, 'i' },
  3309. { { STATE_EPC5 }, 'm' }
  3310. };
  3311. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
  3312. { { 6 /* art */ }, 'o' }
  3313. };
  3314. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
  3315. { { STATE_PSEXCM }, 'i' },
  3316. { { STATE_PSRING }, 'i' },
  3317. { { STATE_EXCSAVE5 }, 'i' }
  3318. };
  3319. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
  3320. { { 6 /* art */ }, 'i' }
  3321. };
  3322. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
  3323. { { STATE_PSEXCM }, 'i' },
  3324. { { STATE_PSRING }, 'i' },
  3325. { { STATE_EXCSAVE5 }, 'o' }
  3326. };
  3327. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
  3328. { { 6 /* art */ }, 'm' }
  3329. };
  3330. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
  3331. { { STATE_PSEXCM }, 'i' },
  3332. { { STATE_PSRING }, 'i' },
  3333. { { STATE_EXCSAVE5 }, 'm' }
  3334. };
  3335. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
  3336. { { 6 /* art */ }, 'o' }
  3337. };
  3338. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
  3339. { { STATE_PSEXCM }, 'i' },
  3340. { { STATE_PSRING }, 'i' },
  3341. { { STATE_EPC6 }, 'i' }
  3342. };
  3343. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
  3344. { { 6 /* art */ }, 'i' }
  3345. };
  3346. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
  3347. { { STATE_PSEXCM }, 'i' },
  3348. { { STATE_PSRING }, 'i' },
  3349. { { STATE_EPC6 }, 'o' }
  3350. };
  3351. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
  3352. { { 6 /* art */ }, 'm' }
  3353. };
  3354. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
  3355. { { STATE_PSEXCM }, 'i' },
  3356. { { STATE_PSRING }, 'i' },
  3357. { { STATE_EPC6 }, 'm' }
  3358. };
  3359. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
  3360. { { 6 /* art */ }, 'o' }
  3361. };
  3362. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
  3363. { { STATE_PSEXCM }, 'i' },
  3364. { { STATE_PSRING }, 'i' },
  3365. { { STATE_EXCSAVE6 }, 'i' }
  3366. };
  3367. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
  3368. { { 6 /* art */ }, 'i' }
  3369. };
  3370. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
  3371. { { STATE_PSEXCM }, 'i' },
  3372. { { STATE_PSRING }, 'i' },
  3373. { { STATE_EXCSAVE6 }, 'o' }
  3374. };
  3375. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
  3376. { { 6 /* art */ }, 'm' }
  3377. };
  3378. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
  3379. { { STATE_PSEXCM }, 'i' },
  3380. { { STATE_PSRING }, 'i' },
  3381. { { STATE_EXCSAVE6 }, 'm' }
  3382. };
  3383. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
  3384. { { 6 /* art */ }, 'o' }
  3385. };
  3386. static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
  3387. { { STATE_PSEXCM }, 'i' },
  3388. { { STATE_PSRING }, 'i' },
  3389. { { STATE_EPC7 }, 'i' }
  3390. };
  3391. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
  3392. { { 6 /* art */ }, 'i' }
  3393. };
  3394. static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
  3395. { { STATE_PSEXCM }, 'i' },
  3396. { { STATE_PSRING }, 'i' },
  3397. { { STATE_EPC7 }, 'o' }
  3398. };
  3399. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
  3400. { { 6 /* art */ }, 'm' }
  3401. };
  3402. static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
  3403. { { STATE_PSEXCM }, 'i' },
  3404. { { STATE_PSRING }, 'i' },
  3405. { { STATE_EPC7 }, 'm' }
  3406. };
  3407. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
  3408. { { 6 /* art */ }, 'o' }
  3409. };
  3410. static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
  3411. { { STATE_PSEXCM }, 'i' },
  3412. { { STATE_PSRING }, 'i' },
  3413. { { STATE_EXCSAVE7 }, 'i' }
  3414. };
  3415. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
  3416. { { 6 /* art */ }, 'i' }
  3417. };
  3418. static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
  3419. { { STATE_PSEXCM }, 'i' },
  3420. { { STATE_PSRING }, 'i' },
  3421. { { STATE_EXCSAVE7 }, 'o' }
  3422. };
  3423. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
  3424. { { 6 /* art */ }, 'm' }
  3425. };
  3426. static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
  3427. { { STATE_PSEXCM }, 'i' },
  3428. { { STATE_PSRING }, 'i' },
  3429. { { STATE_EXCSAVE7 }, 'm' }
  3430. };
  3431. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
  3432. { { 6 /* art */ }, 'o' }
  3433. };
  3434. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
  3435. { { STATE_PSEXCM }, 'i' },
  3436. { { STATE_PSRING }, 'i' },
  3437. { { STATE_EPS2 }, 'i' }
  3438. };
  3439. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
  3440. { { 6 /* art */ }, 'i' }
  3441. };
  3442. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
  3443. { { STATE_PSEXCM }, 'i' },
  3444. { { STATE_PSRING }, 'i' },
  3445. { { STATE_EPS2 }, 'o' }
  3446. };
  3447. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
  3448. { { 6 /* art */ }, 'm' }
  3449. };
  3450. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
  3451. { { STATE_PSEXCM }, 'i' },
  3452. { { STATE_PSRING }, 'i' },
  3453. { { STATE_EPS2 }, 'm' }
  3454. };
  3455. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
  3456. { { 6 /* art */ }, 'o' }
  3457. };
  3458. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
  3459. { { STATE_PSEXCM }, 'i' },
  3460. { { STATE_PSRING }, 'i' },
  3461. { { STATE_EPS3 }, 'i' }
  3462. };
  3463. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
  3464. { { 6 /* art */ }, 'i' }
  3465. };
  3466. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
  3467. { { STATE_PSEXCM }, 'i' },
  3468. { { STATE_PSRING }, 'i' },
  3469. { { STATE_EPS3 }, 'o' }
  3470. };
  3471. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
  3472. { { 6 /* art */ }, 'm' }
  3473. };
  3474. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
  3475. { { STATE_PSEXCM }, 'i' },
  3476. { { STATE_PSRING }, 'i' },
  3477. { { STATE_EPS3 }, 'm' }
  3478. };
  3479. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
  3480. { { 6 /* art */ }, 'o' }
  3481. };
  3482. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
  3483. { { STATE_PSEXCM }, 'i' },
  3484. { { STATE_PSRING }, 'i' },
  3485. { { STATE_EPS4 }, 'i' }
  3486. };
  3487. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
  3488. { { 6 /* art */ }, 'i' }
  3489. };
  3490. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
  3491. { { STATE_PSEXCM }, 'i' },
  3492. { { STATE_PSRING }, 'i' },
  3493. { { STATE_EPS4 }, 'o' }
  3494. };
  3495. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
  3496. { { 6 /* art */ }, 'm' }
  3497. };
  3498. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
  3499. { { STATE_PSEXCM }, 'i' },
  3500. { { STATE_PSRING }, 'i' },
  3501. { { STATE_EPS4 }, 'm' }
  3502. };
  3503. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
  3504. { { 6 /* art */ }, 'o' }
  3505. };
  3506. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
  3507. { { STATE_PSEXCM }, 'i' },
  3508. { { STATE_PSRING }, 'i' },
  3509. { { STATE_EPS5 }, 'i' }
  3510. };
  3511. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
  3512. { { 6 /* art */ }, 'i' }
  3513. };
  3514. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
  3515. { { STATE_PSEXCM }, 'i' },
  3516. { { STATE_PSRING }, 'i' },
  3517. { { STATE_EPS5 }, 'o' }
  3518. };
  3519. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
  3520. { { 6 /* art */ }, 'm' }
  3521. };
  3522. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
  3523. { { STATE_PSEXCM }, 'i' },
  3524. { { STATE_PSRING }, 'i' },
  3525. { { STATE_EPS5 }, 'm' }
  3526. };
  3527. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
  3528. { { 6 /* art */ }, 'o' }
  3529. };
  3530. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
  3531. { { STATE_PSEXCM }, 'i' },
  3532. { { STATE_PSRING }, 'i' },
  3533. { { STATE_EPS6 }, 'i' }
  3534. };
  3535. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
  3536. { { 6 /* art */ }, 'i' }
  3537. };
  3538. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
  3539. { { STATE_PSEXCM }, 'i' },
  3540. { { STATE_PSRING }, 'i' },
  3541. { { STATE_EPS6 }, 'o' }
  3542. };
  3543. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
  3544. { { 6 /* art */ }, 'm' }
  3545. };
  3546. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
  3547. { { STATE_PSEXCM }, 'i' },
  3548. { { STATE_PSRING }, 'i' },
  3549. { { STATE_EPS6 }, 'm' }
  3550. };
  3551. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
  3552. { { 6 /* art */ }, 'o' }
  3553. };
  3554. static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
  3555. { { STATE_PSEXCM }, 'i' },
  3556. { { STATE_PSRING }, 'i' },
  3557. { { STATE_EPS7 }, 'i' }
  3558. };
  3559. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
  3560. { { 6 /* art */ }, 'i' }
  3561. };
  3562. static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
  3563. { { STATE_PSEXCM }, 'i' },
  3564. { { STATE_PSRING }, 'i' },
  3565. { { STATE_EPS7 }, 'o' }
  3566. };
  3567. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
  3568. { { 6 /* art */ }, 'm' }
  3569. };
  3570. static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
  3571. { { STATE_PSEXCM }, 'i' },
  3572. { { STATE_PSRING }, 'i' },
  3573. { { STATE_EPS7 }, 'm' }
  3574. };
  3575. static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
  3576. { { 6 /* art */ }, 'o' }
  3577. };
  3578. static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
  3579. { { STATE_PSEXCM }, 'i' },
  3580. { { STATE_PSRING }, 'i' },
  3581. { { STATE_EXCVADDR }, 'i' }
  3582. };
  3583. static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
  3584. { { 6 /* art */ }, 'i' }
  3585. };
  3586. static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
  3587. { { STATE_PSEXCM }, 'i' },
  3588. { { STATE_PSRING }, 'i' },
  3589. { { STATE_EXCVADDR }, 'o' }
  3590. };
  3591. static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
  3592. { { 6 /* art */ }, 'm' }
  3593. };
  3594. static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
  3595. { { STATE_PSEXCM }, 'i' },
  3596. { { STATE_PSRING }, 'i' },
  3597. { { STATE_EXCVADDR }, 'm' }
  3598. };
  3599. static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
  3600. { { 6 /* art */ }, 'o' }
  3601. };
  3602. static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
  3603. { { STATE_PSEXCM }, 'i' },
  3604. { { STATE_PSRING }, 'i' },
  3605. { { STATE_DEPC }, 'i' }
  3606. };
  3607. static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
  3608. { { 6 /* art */ }, 'i' }
  3609. };
  3610. static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
  3611. { { STATE_PSEXCM }, 'i' },
  3612. { { STATE_PSRING }, 'i' },
  3613. { { STATE_DEPC }, 'o' }
  3614. };
  3615. static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
  3616. { { 6 /* art */ }, 'm' }
  3617. };
  3618. static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
  3619. { { STATE_PSEXCM }, 'i' },
  3620. { { STATE_PSRING }, 'i' },
  3621. { { STATE_DEPC }, 'm' }
  3622. };
  3623. static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
  3624. { { 6 /* art */ }, 'o' }
  3625. };
  3626. static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
  3627. { { STATE_PSEXCM }, 'i' },
  3628. { { STATE_PSRING }, 'i' },
  3629. { { STATE_EXCCAUSE }, 'i' },
  3630. { { STATE_XTSYNC }, 'i' }
  3631. };
  3632. static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
  3633. { { 6 /* art */ }, 'i' }
  3634. };
  3635. static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
  3636. { { STATE_PSEXCM }, 'i' },
  3637. { { STATE_PSRING }, 'i' },
  3638. { { STATE_EXCCAUSE }, 'o' }
  3639. };
  3640. static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
  3641. { { 6 /* art */ }, 'm' }
  3642. };
  3643. static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
  3644. { { STATE_PSEXCM }, 'i' },
  3645. { { STATE_PSRING }, 'i' },
  3646. { { STATE_EXCCAUSE }, 'm' }
  3647. };
  3648. static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
  3649. { { 6 /* art */ }, 'o' }
  3650. };
  3651. static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
  3652. { { STATE_PSEXCM }, 'i' },
  3653. { { STATE_PSRING }, 'i' },
  3654. { { STATE_MISC0 }, 'i' }
  3655. };
  3656. static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
  3657. { { 6 /* art */ }, 'i' }
  3658. };
  3659. static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
  3660. { { STATE_PSEXCM }, 'i' },
  3661. { { STATE_PSRING }, 'i' },
  3662. { { STATE_MISC0 }, 'o' }
  3663. };
  3664. static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
  3665. { { 6 /* art */ }, 'm' }
  3666. };
  3667. static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
  3668. { { STATE_PSEXCM }, 'i' },
  3669. { { STATE_PSRING }, 'i' },
  3670. { { STATE_MISC0 }, 'm' }
  3671. };
  3672. static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
  3673. { { 6 /* art */ }, 'o' }
  3674. };
  3675. static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
  3676. { { STATE_PSEXCM }, 'i' },
  3677. { { STATE_PSRING }, 'i' },
  3678. { { STATE_MISC1 }, 'i' }
  3679. };
  3680. static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
  3681. { { 6 /* art */ }, 'i' }
  3682. };
  3683. static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
  3684. { { STATE_PSEXCM }, 'i' },
  3685. { { STATE_PSRING }, 'i' },
  3686. { { STATE_MISC1 }, 'o' }
  3687. };
  3688. static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
  3689. { { 6 /* art */ }, 'm' }
  3690. };
  3691. static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
  3692. { { STATE_PSEXCM }, 'i' },
  3693. { { STATE_PSRING }, 'i' },
  3694. { { STATE_MISC1 }, 'm' }
  3695. };
  3696. static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
  3697. { { 6 /* art */ }, 'o' }
  3698. };
  3699. static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
  3700. { { STATE_PSEXCM }, 'i' },
  3701. { { STATE_PSRING }, 'i' }
  3702. };
  3703. static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
  3704. { { 6 /* art */ }, 'o' }
  3705. };
  3706. static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
  3707. { { STATE_PSEXCM }, 'i' },
  3708. { { STATE_PSRING }, 'i' },
  3709. { { STATE_VECBASE }, 'i' }
  3710. };
  3711. static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
  3712. { { 6 /* art */ }, 'i' }
  3713. };
  3714. static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
  3715. { { STATE_PSEXCM }, 'i' },
  3716. { { STATE_PSRING }, 'i' },
  3717. { { STATE_VECBASE }, 'o' }
  3718. };
  3719. static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
  3720. { { 6 /* art */ }, 'm' }
  3721. };
  3722. static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
  3723. { { STATE_PSEXCM }, 'i' },
  3724. { { STATE_PSRING }, 'i' },
  3725. { { STATE_VECBASE }, 'm' }
  3726. };
  3727. static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
  3728. { { 4 /* ars */ }, 'i' },
  3729. { { 6 /* art */ }, 'i' }
  3730. };
  3731. static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
  3732. { { STATE_ACC }, 'o' }
  3733. };
  3734. static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
  3735. { { 4 /* ars */ }, 'i' },
  3736. { { 34 /* my */ }, 'i' }
  3737. };
  3738. static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
  3739. { { STATE_ACC }, 'o' }
  3740. };
  3741. static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
  3742. { { 33 /* mx */ }, 'i' },
  3743. { { 6 /* art */ }, 'i' }
  3744. };
  3745. static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
  3746. { { STATE_ACC }, 'o' }
  3747. };
  3748. static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
  3749. { { 33 /* mx */ }, 'i' },
  3750. { { 34 /* my */ }, 'i' }
  3751. };
  3752. static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
  3753. { { STATE_ACC }, 'o' }
  3754. };
  3755. static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
  3756. { { 4 /* ars */ }, 'i' },
  3757. { { 6 /* art */ }, 'i' }
  3758. };
  3759. static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
  3760. { { STATE_ACC }, 'm' }
  3761. };
  3762. static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
  3763. { { 4 /* ars */ }, 'i' },
  3764. { { 34 /* my */ }, 'i' }
  3765. };
  3766. static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
  3767. { { STATE_ACC }, 'm' }
  3768. };
  3769. static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
  3770. { { 33 /* mx */ }, 'i' },
  3771. { { 6 /* art */ }, 'i' }
  3772. };
  3773. static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
  3774. { { STATE_ACC }, 'm' }
  3775. };
  3776. static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
  3777. { { 33 /* mx */ }, 'i' },
  3778. { { 34 /* my */ }, 'i' }
  3779. };
  3780. static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
  3781. { { STATE_ACC }, 'm' }
  3782. };
  3783. static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
  3784. { { 35 /* mw */ }, 'o' },
  3785. { { 4 /* ars */ }, 'm' },
  3786. { { 33 /* mx */ }, 'i' },
  3787. { { 6 /* art */ }, 'i' }
  3788. };
  3789. static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
  3790. { { STATE_ACC }, 'm' }
  3791. };
  3792. static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
  3793. { { 35 /* mw */ }, 'o' },
  3794. { { 4 /* ars */ }, 'm' },
  3795. { { 33 /* mx */ }, 'i' },
  3796. { { 34 /* my */ }, 'i' }
  3797. };
  3798. static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
  3799. { { STATE_ACC }, 'm' }
  3800. };
  3801. static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
  3802. { { 35 /* mw */ }, 'o' },
  3803. { { 4 /* ars */ }, 'm' }
  3804. };
  3805. static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
  3806. { { 3 /* arr */ }, 'o' },
  3807. { { 4 /* ars */ }, 'i' },
  3808. { { 6 /* art */ }, 'i' }
  3809. };
  3810. static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
  3811. { { 6 /* art */ }, 'o' },
  3812. { { 36 /* mr0 */ }, 'i' }
  3813. };
  3814. static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
  3815. { { 6 /* art */ }, 'i' },
  3816. { { 36 /* mr0 */ }, 'o' }
  3817. };
  3818. static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
  3819. { { 6 /* art */ }, 'm' },
  3820. { { 36 /* mr0 */ }, 'm' }
  3821. };
  3822. static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
  3823. { { 6 /* art */ }, 'o' },
  3824. { { 37 /* mr1 */ }, 'i' }
  3825. };
  3826. static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
  3827. { { 6 /* art */ }, 'i' },
  3828. { { 37 /* mr1 */ }, 'o' }
  3829. };
  3830. static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
  3831. { { 6 /* art */ }, 'm' },
  3832. { { 37 /* mr1 */ }, 'm' }
  3833. };
  3834. static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
  3835. { { 6 /* art */ }, 'o' },
  3836. { { 38 /* mr2 */ }, 'i' }
  3837. };
  3838. static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
  3839. { { 6 /* art */ }, 'i' },
  3840. { { 38 /* mr2 */ }, 'o' }
  3841. };
  3842. static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
  3843. { { 6 /* art */ }, 'm' },
  3844. { { 38 /* mr2 */ }, 'm' }
  3845. };
  3846. static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
  3847. { { 6 /* art */ }, 'o' },
  3848. { { 39 /* mr3 */ }, 'i' }
  3849. };
  3850. static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
  3851. { { 6 /* art */ }, 'i' },
  3852. { { 39 /* mr3 */ }, 'o' }
  3853. };
  3854. static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
  3855. { { 6 /* art */ }, 'm' },
  3856. { { 39 /* mr3 */ }, 'm' }
  3857. };
  3858. static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
  3859. { { 6 /* art */ }, 'o' }
  3860. };
  3861. static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
  3862. { { STATE_ACC }, 'i' }
  3863. };
  3864. static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
  3865. { { 6 /* art */ }, 'i' }
  3866. };
  3867. static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
  3868. { { STATE_ACC }, 'm' }
  3869. };
  3870. static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
  3871. { { 6 /* art */ }, 'm' }
  3872. };
  3873. static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
  3874. { { STATE_ACC }, 'm' }
  3875. };
  3876. static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
  3877. { { 6 /* art */ }, 'o' }
  3878. };
  3879. static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
  3880. { { STATE_ACC }, 'i' }
  3881. };
  3882. static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
  3883. { { 6 /* art */ }, 'i' }
  3884. };
  3885. static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
  3886. { { STATE_ACC }, 'm' }
  3887. };
  3888. static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
  3889. { { 6 /* art */ }, 'm' }
  3890. };
  3891. static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
  3892. { { STATE_ACC }, 'm' }
  3893. };
  3894. static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
  3895. { { 50 /* s */ }, 'i' }
  3896. };
  3897. static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
  3898. { { STATE_PSWOE }, 'o' },
  3899. { { STATE_PSCALLINC }, 'o' },
  3900. { { STATE_PSOWB }, 'o' },
  3901. { { STATE_PSRING }, 'm' },
  3902. { { STATE_PSUM }, 'o' },
  3903. { { STATE_PSEXCM }, 'm' },
  3904. { { STATE_PSINTLEVEL }, 'o' },
  3905. { { STATE_EPC1 }, 'i' },
  3906. { { STATE_EPC2 }, 'i' },
  3907. { { STATE_EPC3 }, 'i' },
  3908. { { STATE_EPC4 }, 'i' },
  3909. { { STATE_EPC5 }, 'i' },
  3910. { { STATE_EPC6 }, 'i' },
  3911. { { STATE_EPC7 }, 'i' },
  3912. { { STATE_EPS2 }, 'i' },
  3913. { { STATE_EPS3 }, 'i' },
  3914. { { STATE_EPS4 }, 'i' },
  3915. { { STATE_EPS5 }, 'i' },
  3916. { { STATE_EPS6 }, 'i' },
  3917. { { STATE_EPS7 }, 'i' },
  3918. { { STATE_InOCDMode }, 'm' }
  3919. };
  3920. static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
  3921. { { 50 /* s */ }, 'i' }
  3922. };
  3923. static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
  3924. { { STATE_PSEXCM }, 'i' },
  3925. { { STATE_PSRING }, 'i' },
  3926. { { STATE_PSINTLEVEL }, 'o' }
  3927. };
  3928. static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
  3929. { { 6 /* art */ }, 'o' }
  3930. };
  3931. static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
  3932. { { STATE_PSEXCM }, 'i' },
  3933. { { STATE_PSRING }, 'i' },
  3934. { { STATE_INTERRUPT }, 'i' }
  3935. };
  3936. static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
  3937. { { 6 /* art */ }, 'i' }
  3938. };
  3939. static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
  3940. { { STATE_PSEXCM }, 'i' },
  3941. { { STATE_PSRING }, 'i' },
  3942. { { STATE_XTSYNC }, 'o' },
  3943. { { STATE_INTERRUPT }, 'm' }
  3944. };
  3945. static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
  3946. { { 6 /* art */ }, 'i' }
  3947. };
  3948. static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
  3949. { { STATE_PSEXCM }, 'i' },
  3950. { { STATE_PSRING }, 'i' },
  3951. { { STATE_XTSYNC }, 'o' },
  3952. { { STATE_INTERRUPT }, 'm' }
  3953. };
  3954. static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
  3955. { { 6 /* art */ }, 'o' }
  3956. };
  3957. static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
  3958. { { STATE_PSEXCM }, 'i' },
  3959. { { STATE_PSRING }, 'i' },
  3960. { { STATE_INTENABLE }, 'i' }
  3961. };
  3962. static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
  3963. { { 6 /* art */ }, 'i' }
  3964. };
  3965. static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
  3966. { { STATE_PSEXCM }, 'i' },
  3967. { { STATE_PSRING }, 'i' },
  3968. { { STATE_INTENABLE }, 'o' }
  3969. };
  3970. static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
  3971. { { 6 /* art */ }, 'm' }
  3972. };
  3973. static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
  3974. { { STATE_PSEXCM }, 'i' },
  3975. { { STATE_PSRING }, 'i' },
  3976. { { STATE_INTENABLE }, 'm' }
  3977. };
  3978. static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
  3979. { { 41 /* imms */ }, 'i' },
  3980. { { 40 /* immt */ }, 'i' }
  3981. };
  3982. static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
  3983. { { STATE_PSEXCM }, 'i' },
  3984. { { STATE_PSINTLEVEL }, 'i' }
  3985. };
  3986. static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
  3987. { { 41 /* imms */ }, 'i' }
  3988. };
  3989. static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
  3990. { { STATE_PSEXCM }, 'i' },
  3991. { { STATE_PSINTLEVEL }, 'i' }
  3992. };
  3993. static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
  3994. { { 6 /* art */ }, 'o' }
  3995. };
  3996. static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
  3997. { { STATE_PSEXCM }, 'i' },
  3998. { { STATE_PSRING }, 'i' },
  3999. { { STATE_DBREAKA0 }, 'i' }
  4000. };
  4001. static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
  4002. { { 6 /* art */ }, 'i' }
  4003. };
  4004. static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
  4005. { { STATE_PSEXCM }, 'i' },
  4006. { { STATE_PSRING }, 'i' },
  4007. { { STATE_DBREAKA0 }, 'o' },
  4008. { { STATE_XTSYNC }, 'o' }
  4009. };
  4010. static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
  4011. { { 6 /* art */ }, 'm' }
  4012. };
  4013. static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
  4014. { { STATE_PSEXCM }, 'i' },
  4015. { { STATE_PSRING }, 'i' },
  4016. { { STATE_DBREAKA0 }, 'm' },
  4017. { { STATE_XTSYNC }, 'o' }
  4018. };
  4019. static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
  4020. { { 6 /* art */ }, 'o' }
  4021. };
  4022. static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
  4023. { { STATE_PSEXCM }, 'i' },
  4024. { { STATE_PSRING }, 'i' },
  4025. { { STATE_DBREAKC0 }, 'i' }
  4026. };
  4027. static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
  4028. { { 6 /* art */ }, 'i' }
  4029. };
  4030. static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
  4031. { { STATE_PSEXCM }, 'i' },
  4032. { { STATE_PSRING }, 'i' },
  4033. { { STATE_DBREAKC0 }, 'o' },
  4034. { { STATE_XTSYNC }, 'o' }
  4035. };
  4036. static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
  4037. { { 6 /* art */ }, 'm' }
  4038. };
  4039. static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
  4040. { { STATE_PSEXCM }, 'i' },
  4041. { { STATE_PSRING }, 'i' },
  4042. { { STATE_DBREAKC0 }, 'm' },
  4043. { { STATE_XTSYNC }, 'o' }
  4044. };
  4045. static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
  4046. { { 6 /* art */ }, 'o' }
  4047. };
  4048. static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
  4049. { { STATE_PSEXCM }, 'i' },
  4050. { { STATE_PSRING }, 'i' },
  4051. { { STATE_DBREAKA1 }, 'i' }
  4052. };
  4053. static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
  4054. { { 6 /* art */ }, 'i' }
  4055. };
  4056. static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
  4057. { { STATE_PSEXCM }, 'i' },
  4058. { { STATE_PSRING }, 'i' },
  4059. { { STATE_DBREAKA1 }, 'o' },
  4060. { { STATE_XTSYNC }, 'o' }
  4061. };
  4062. static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
  4063. { { 6 /* art */ }, 'm' }
  4064. };
  4065. static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
  4066. { { STATE_PSEXCM }, 'i' },
  4067. { { STATE_PSRING }, 'i' },
  4068. { { STATE_DBREAKA1 }, 'm' },
  4069. { { STATE_XTSYNC }, 'o' }
  4070. };
  4071. static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
  4072. { { 6 /* art */ }, 'o' }
  4073. };
  4074. static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
  4075. { { STATE_PSEXCM }, 'i' },
  4076. { { STATE_PSRING }, 'i' },
  4077. { { STATE_DBREAKC1 }, 'i' }
  4078. };
  4079. static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
  4080. { { 6 /* art */ }, 'i' }
  4081. };
  4082. static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
  4083. { { STATE_PSEXCM }, 'i' },
  4084. { { STATE_PSRING }, 'i' },
  4085. { { STATE_DBREAKC1 }, 'o' },
  4086. { { STATE_XTSYNC }, 'o' }
  4087. };
  4088. static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
  4089. { { 6 /* art */ }, 'm' }
  4090. };
  4091. static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
  4092. { { STATE_PSEXCM }, 'i' },
  4093. { { STATE_PSRING }, 'i' },
  4094. { { STATE_DBREAKC1 }, 'm' },
  4095. { { STATE_XTSYNC }, 'o' }
  4096. };
  4097. static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
  4098. { { 6 /* art */ }, 'o' }
  4099. };
  4100. static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
  4101. { { STATE_PSEXCM }, 'i' },
  4102. { { STATE_PSRING }, 'i' },
  4103. { { STATE_IBREAKA0 }, 'i' }
  4104. };
  4105. static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
  4106. { { 6 /* art */ }, 'i' }
  4107. };
  4108. static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
  4109. { { STATE_PSEXCM }, 'i' },
  4110. { { STATE_PSRING }, 'i' },
  4111. { { STATE_IBREAKA0 }, 'o' }
  4112. };
  4113. static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
  4114. { { 6 /* art */ }, 'm' }
  4115. };
  4116. static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
  4117. { { STATE_PSEXCM }, 'i' },
  4118. { { STATE_PSRING }, 'i' },
  4119. { { STATE_IBREAKA0 }, 'm' }
  4120. };
  4121. static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
  4122. { { 6 /* art */ }, 'o' }
  4123. };
  4124. static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
  4125. { { STATE_PSEXCM }, 'i' },
  4126. { { STATE_PSRING }, 'i' },
  4127. { { STATE_IBREAKA1 }, 'i' }
  4128. };
  4129. static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
  4130. { { 6 /* art */ }, 'i' }
  4131. };
  4132. static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
  4133. { { STATE_PSEXCM }, 'i' },
  4134. { { STATE_PSRING }, 'i' },
  4135. { { STATE_IBREAKA1 }, 'o' }
  4136. };
  4137. static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
  4138. { { 6 /* art */ }, 'm' }
  4139. };
  4140. static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
  4141. { { STATE_PSEXCM }, 'i' },
  4142. { { STATE_PSRING }, 'i' },
  4143. { { STATE_IBREAKA1 }, 'm' }
  4144. };
  4145. static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
  4146. { { 6 /* art */ }, 'o' }
  4147. };
  4148. static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
  4149. { { STATE_PSEXCM }, 'i' },
  4150. { { STATE_PSRING }, 'i' },
  4151. { { STATE_IBREAKENABLE }, 'i' }
  4152. };
  4153. static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
  4154. { { 6 /* art */ }, 'i' }
  4155. };
  4156. static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
  4157. { { STATE_PSEXCM }, 'i' },
  4158. { { STATE_PSRING }, 'i' },
  4159. { { STATE_IBREAKENABLE }, 'o' }
  4160. };
  4161. static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
  4162. { { 6 /* art */ }, 'm' }
  4163. };
  4164. static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
  4165. { { STATE_PSEXCM }, 'i' },
  4166. { { STATE_PSRING }, 'i' },
  4167. { { STATE_IBREAKENABLE }, 'm' }
  4168. };
  4169. static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
  4170. { { 6 /* art */ }, 'o' }
  4171. };
  4172. static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
  4173. { { STATE_PSEXCM }, 'i' },
  4174. { { STATE_PSRING }, 'i' },
  4175. { { STATE_DEBUGCAUSE }, 'i' },
  4176. { { STATE_DBNUM }, 'i' }
  4177. };
  4178. static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
  4179. { { 6 /* art */ }, 'i' }
  4180. };
  4181. static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
  4182. { { STATE_PSEXCM }, 'i' },
  4183. { { STATE_PSRING }, 'i' },
  4184. { { STATE_DEBUGCAUSE }, 'o' },
  4185. { { STATE_DBNUM }, 'o' }
  4186. };
  4187. static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
  4188. { { 6 /* art */ }, 'm' }
  4189. };
  4190. static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
  4191. { { STATE_PSEXCM }, 'i' },
  4192. { { STATE_PSRING }, 'i' },
  4193. { { STATE_DEBUGCAUSE }, 'm' },
  4194. { { STATE_DBNUM }, 'm' }
  4195. };
  4196. static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
  4197. { { 6 /* art */ }, 'o' }
  4198. };
  4199. static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
  4200. { { STATE_PSEXCM }, 'i' },
  4201. { { STATE_PSRING }, 'i' },
  4202. { { STATE_ICOUNT }, 'i' }
  4203. };
  4204. static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
  4205. { { 6 /* art */ }, 'i' }
  4206. };
  4207. static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
  4208. { { STATE_PSEXCM }, 'i' },
  4209. { { STATE_PSRING }, 'i' },
  4210. { { STATE_XTSYNC }, 'o' },
  4211. { { STATE_ICOUNT }, 'o' }
  4212. };
  4213. static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
  4214. { { 6 /* art */ }, 'm' }
  4215. };
  4216. static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
  4217. { { STATE_PSEXCM }, 'i' },
  4218. { { STATE_PSRING }, 'i' },
  4219. { { STATE_XTSYNC }, 'o' },
  4220. { { STATE_ICOUNT }, 'm' }
  4221. };
  4222. static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
  4223. { { 6 /* art */ }, 'o' }
  4224. };
  4225. static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
  4226. { { STATE_PSEXCM }, 'i' },
  4227. { { STATE_PSRING }, 'i' },
  4228. { { STATE_ICOUNTLEVEL }, 'i' }
  4229. };
  4230. static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
  4231. { { 6 /* art */ }, 'i' }
  4232. };
  4233. static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
  4234. { { STATE_PSEXCM }, 'i' },
  4235. { { STATE_PSRING }, 'i' },
  4236. { { STATE_ICOUNTLEVEL }, 'o' }
  4237. };
  4238. static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
  4239. { { 6 /* art */ }, 'm' }
  4240. };
  4241. static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
  4242. { { STATE_PSEXCM }, 'i' },
  4243. { { STATE_PSRING }, 'i' },
  4244. { { STATE_ICOUNTLEVEL }, 'm' }
  4245. };
  4246. static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
  4247. { { 6 /* art */ }, 'o' }
  4248. };
  4249. static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
  4250. { { STATE_PSEXCM }, 'i' },
  4251. { { STATE_PSRING }, 'i' },
  4252. { { STATE_DDR }, 'i' }
  4253. };
  4254. static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
  4255. { { 6 /* art */ }, 'i' }
  4256. };
  4257. static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
  4258. { { STATE_PSEXCM }, 'i' },
  4259. { { STATE_PSRING }, 'i' },
  4260. { { STATE_XTSYNC }, 'o' },
  4261. { { STATE_DDR }, 'o' }
  4262. };
  4263. static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
  4264. { { 6 /* art */ }, 'm' }
  4265. };
  4266. static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
  4267. { { STATE_PSEXCM }, 'i' },
  4268. { { STATE_PSRING }, 'i' },
  4269. { { STATE_XTSYNC }, 'o' },
  4270. { { STATE_DDR }, 'm' }
  4271. };
  4272. static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
  4273. { { 41 /* imms */ }, 'i' }
  4274. };
  4275. static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
  4276. { { STATE_InOCDMode }, 'm' },
  4277. { { STATE_EPC6 }, 'i' },
  4278. { { STATE_PSWOE }, 'o' },
  4279. { { STATE_PSCALLINC }, 'o' },
  4280. { { STATE_PSOWB }, 'o' },
  4281. { { STATE_PSRING }, 'o' },
  4282. { { STATE_PSUM }, 'o' },
  4283. { { STATE_PSEXCM }, 'o' },
  4284. { { STATE_PSINTLEVEL }, 'o' },
  4285. { { STATE_EPS6 }, 'i' }
  4286. };
  4287. static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
  4288. { { STATE_InOCDMode }, 'm' }
  4289. };
  4290. static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
  4291. { { 6 /* art */ }, 'i' }
  4292. };
  4293. static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
  4294. { { STATE_PSEXCM }, 'i' },
  4295. { { STATE_PSRING }, 'i' },
  4296. { { STATE_XTSYNC }, 'o' }
  4297. };
  4298. static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
  4299. { { 6 /* art */ }, 'o' }
  4300. };
  4301. static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
  4302. { { STATE_PSEXCM }, 'i' },
  4303. { { STATE_PSRING }, 'i' },
  4304. { { STATE_CCOUNT }, 'i' }
  4305. };
  4306. static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
  4307. { { 6 /* art */ }, 'i' }
  4308. };
  4309. static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
  4310. { { STATE_PSEXCM }, 'i' },
  4311. { { STATE_PSRING }, 'i' },
  4312. { { STATE_XTSYNC }, 'o' },
  4313. { { STATE_CCOUNT }, 'o' }
  4314. };
  4315. static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
  4316. { { 6 /* art */ }, 'm' }
  4317. };
  4318. static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
  4319. { { STATE_PSEXCM }, 'i' },
  4320. { { STATE_PSRING }, 'i' },
  4321. { { STATE_XTSYNC }, 'o' },
  4322. { { STATE_CCOUNT }, 'm' }
  4323. };
  4324. static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
  4325. { { 6 /* art */ }, 'o' }
  4326. };
  4327. static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
  4328. { { STATE_PSEXCM }, 'i' },
  4329. { { STATE_PSRING }, 'i' },
  4330. { { STATE_CCOMPARE0 }, 'i' }
  4331. };
  4332. static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
  4333. { { 6 /* art */ }, 'i' }
  4334. };
  4335. static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
  4336. { { STATE_PSEXCM }, 'i' },
  4337. { { STATE_PSRING }, 'i' },
  4338. { { STATE_CCOMPARE0 }, 'o' },
  4339. { { STATE_INTERRUPT }, 'm' }
  4340. };
  4341. static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
  4342. { { 6 /* art */ }, 'm' }
  4343. };
  4344. static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
  4345. { { STATE_PSEXCM }, 'i' },
  4346. { { STATE_PSRING }, 'i' },
  4347. { { STATE_CCOMPARE0 }, 'm' },
  4348. { { STATE_INTERRUPT }, 'm' }
  4349. };
  4350. static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
  4351. { { 6 /* art */ }, 'o' }
  4352. };
  4353. static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
  4354. { { STATE_PSEXCM }, 'i' },
  4355. { { STATE_PSRING }, 'i' },
  4356. { { STATE_CCOMPARE1 }, 'i' }
  4357. };
  4358. static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
  4359. { { 6 /* art */ }, 'i' }
  4360. };
  4361. static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
  4362. { { STATE_PSEXCM }, 'i' },
  4363. { { STATE_PSRING }, 'i' },
  4364. { { STATE_CCOMPARE1 }, 'o' },
  4365. { { STATE_INTERRUPT }, 'm' }
  4366. };
  4367. static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
  4368. { { 6 /* art */ }, 'm' }
  4369. };
  4370. static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
  4371. { { STATE_PSEXCM }, 'i' },
  4372. { { STATE_PSRING }, 'i' },
  4373. { { STATE_CCOMPARE1 }, 'm' },
  4374. { { STATE_INTERRUPT }, 'm' }
  4375. };
  4376. static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
  4377. { { 6 /* art */ }, 'o' }
  4378. };
  4379. static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
  4380. { { STATE_PSEXCM }, 'i' },
  4381. { { STATE_PSRING }, 'i' },
  4382. { { STATE_CCOMPARE2 }, 'i' }
  4383. };
  4384. static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
  4385. { { 6 /* art */ }, 'i' }
  4386. };
  4387. static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
  4388. { { STATE_PSEXCM }, 'i' },
  4389. { { STATE_PSRING }, 'i' },
  4390. { { STATE_CCOMPARE2 }, 'o' },
  4391. { { STATE_INTERRUPT }, 'm' }
  4392. };
  4393. static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
  4394. { { 6 /* art */ }, 'm' }
  4395. };
  4396. static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
  4397. { { STATE_PSEXCM }, 'i' },
  4398. { { STATE_PSRING }, 'i' },
  4399. { { STATE_CCOMPARE2 }, 'm' },
  4400. { { STATE_INTERRUPT }, 'm' }
  4401. };
  4402. static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
  4403. { { 4 /* ars */ }, 'i' },
  4404. { { 21 /* uimm8x4 */ }, 'i' }
  4405. };
  4406. static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
  4407. { { 4 /* ars */ }, 'i' },
  4408. { { 22 /* uimm4x16 */ }, 'i' }
  4409. };
  4410. static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
  4411. { { STATE_PSEXCM }, 'i' },
  4412. { { STATE_PSRING }, 'i' }
  4413. };
  4414. static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
  4415. { { 4 /* ars */ }, 'i' },
  4416. { { 21 /* uimm8x4 */ }, 'i' }
  4417. };
  4418. static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
  4419. { { STATE_PSEXCM }, 'i' },
  4420. { { STATE_PSRING }, 'i' }
  4421. };
  4422. static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
  4423. { { 6 /* art */ }, 'o' },
  4424. { { 4 /* ars */ }, 'i' }
  4425. };
  4426. static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
  4427. { { STATE_PSEXCM }, 'i' },
  4428. { { STATE_PSRING }, 'i' }
  4429. };
  4430. static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
  4431. { { 6 /* art */ }, 'i' },
  4432. { { 4 /* ars */ }, 'i' }
  4433. };
  4434. static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
  4435. { { STATE_PSEXCM }, 'i' },
  4436. { { STATE_PSRING }, 'i' }
  4437. };
  4438. static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
  4439. { { 4 /* ars */ }, 'i' },
  4440. { { 21 /* uimm8x4 */ }, 'i' }
  4441. };
  4442. static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
  4443. { { 4 /* ars */ }, 'i' },
  4444. { { 22 /* uimm4x16 */ }, 'i' }
  4445. };
  4446. static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
  4447. { { STATE_PSEXCM }, 'i' },
  4448. { { STATE_PSRING }, 'i' }
  4449. };
  4450. static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
  4451. { { 4 /* ars */ }, 'i' },
  4452. { { 21 /* uimm8x4 */ }, 'i' }
  4453. };
  4454. static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
  4455. { { STATE_PSEXCM }, 'i' },
  4456. { { STATE_PSRING }, 'i' }
  4457. };
  4458. static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
  4459. { { 4 /* ars */ }, 'i' },
  4460. { { 21 /* uimm8x4 */ }, 'i' }
  4461. };
  4462. static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
  4463. { { 4 /* ars */ }, 'i' },
  4464. { { 22 /* uimm4x16 */ }, 'i' }
  4465. };
  4466. static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
  4467. { { STATE_PSEXCM }, 'i' },
  4468. { { STATE_PSRING }, 'i' }
  4469. };
  4470. static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
  4471. { { 6 /* art */ }, 'i' },
  4472. { { 4 /* ars */ }, 'i' }
  4473. };
  4474. static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
  4475. { { STATE_PSEXCM }, 'i' },
  4476. { { STATE_PSRING }, 'i' }
  4477. };
  4478. static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
  4479. { { 6 /* art */ }, 'o' },
  4480. { { 4 /* ars */ }, 'i' }
  4481. };
  4482. static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
  4483. { { STATE_PSEXCM }, 'i' },
  4484. { { STATE_PSRING }, 'i' }
  4485. };
  4486. static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
  4487. { { 6 /* art */ }, 'i' }
  4488. };
  4489. static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
  4490. { { STATE_PSEXCM }, 'i' },
  4491. { { STATE_PSRING }, 'i' },
  4492. { { STATE_PTBASE }, 'o' },
  4493. { { STATE_XTSYNC }, 'o' }
  4494. };
  4495. static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
  4496. { { 6 /* art */ }, 'o' }
  4497. };
  4498. static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
  4499. { { STATE_PSEXCM }, 'i' },
  4500. { { STATE_PSRING }, 'i' },
  4501. { { STATE_PTBASE }, 'i' },
  4502. { { STATE_EXCVADDR }, 'i' }
  4503. };
  4504. static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
  4505. { { 6 /* art */ }, 'm' }
  4506. };
  4507. static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
  4508. { { STATE_PSEXCM }, 'i' },
  4509. { { STATE_PSRING }, 'i' },
  4510. { { STATE_PTBASE }, 'm' },
  4511. { { STATE_EXCVADDR }, 'i' },
  4512. { { STATE_XTSYNC }, 'o' }
  4513. };
  4514. static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
  4515. { { 6 /* art */ }, 'o' }
  4516. };
  4517. static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
  4518. { { STATE_PSEXCM }, 'i' },
  4519. { { STATE_PSRING }, 'i' },
  4520. { { STATE_ASID3 }, 'i' },
  4521. { { STATE_ASID2 }, 'i' },
  4522. { { STATE_ASID1 }, 'i' }
  4523. };
  4524. static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
  4525. { { 6 /* art */ }, 'i' }
  4526. };
  4527. static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
  4528. { { STATE_XTSYNC }, 'o' },
  4529. { { STATE_PSEXCM }, 'i' },
  4530. { { STATE_PSRING }, 'i' },
  4531. { { STATE_ASID3 }, 'o' },
  4532. { { STATE_ASID2 }, 'o' },
  4533. { { STATE_ASID1 }, 'o' }
  4534. };
  4535. static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
  4536. { { 6 /* art */ }, 'm' }
  4537. };
  4538. static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
  4539. { { STATE_XTSYNC }, 'o' },
  4540. { { STATE_PSEXCM }, 'i' },
  4541. { { STATE_PSRING }, 'i' },
  4542. { { STATE_ASID3 }, 'm' },
  4543. { { STATE_ASID2 }, 'm' },
  4544. { { STATE_ASID1 }, 'm' }
  4545. };
  4546. static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
  4547. { { 6 /* art */ }, 'o' }
  4548. };
  4549. static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
  4550. { { STATE_PSEXCM }, 'i' },
  4551. { { STATE_PSRING }, 'i' },
  4552. { { STATE_INSTPGSZID4 }, 'i' }
  4553. };
  4554. static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
  4555. { { 6 /* art */ }, 'i' }
  4556. };
  4557. static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
  4558. { { STATE_XTSYNC }, 'o' },
  4559. { { STATE_PSEXCM }, 'i' },
  4560. { { STATE_PSRING }, 'i' },
  4561. { { STATE_INSTPGSZID4 }, 'o' }
  4562. };
  4563. static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
  4564. { { 6 /* art */ }, 'm' }
  4565. };
  4566. static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
  4567. { { STATE_XTSYNC }, 'o' },
  4568. { { STATE_PSEXCM }, 'i' },
  4569. { { STATE_PSRING }, 'i' },
  4570. { { STATE_INSTPGSZID4 }, 'm' }
  4571. };
  4572. static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
  4573. { { 6 /* art */ }, 'o' }
  4574. };
  4575. static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
  4576. { { STATE_PSEXCM }, 'i' },
  4577. { { STATE_PSRING }, 'i' },
  4578. { { STATE_DATAPGSZID4 }, 'i' }
  4579. };
  4580. static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
  4581. { { 6 /* art */ }, 'i' }
  4582. };
  4583. static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
  4584. { { STATE_XTSYNC }, 'o' },
  4585. { { STATE_PSEXCM }, 'i' },
  4586. { { STATE_PSRING }, 'i' },
  4587. { { STATE_DATAPGSZID4 }, 'o' }
  4588. };
  4589. static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
  4590. { { 6 /* art */ }, 'm' }
  4591. };
  4592. static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
  4593. { { STATE_XTSYNC }, 'o' },
  4594. { { STATE_PSEXCM }, 'i' },
  4595. { { STATE_PSRING }, 'i' },
  4596. { { STATE_DATAPGSZID4 }, 'm' }
  4597. };
  4598. static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
  4599. { { 4 /* ars */ }, 'i' }
  4600. };
  4601. static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
  4602. { { STATE_PSEXCM }, 'i' },
  4603. { { STATE_PSRING }, 'i' },
  4604. { { STATE_XTSYNC }, 'o' }
  4605. };
  4606. static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
  4607. { { 6 /* art */ }, 'o' },
  4608. { { 4 /* ars */ }, 'i' }
  4609. };
  4610. static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
  4611. { { STATE_PSEXCM }, 'i' },
  4612. { { STATE_PSRING }, 'i' }
  4613. };
  4614. static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
  4615. { { 6 /* art */ }, 'i' },
  4616. { { 4 /* ars */ }, 'i' }
  4617. };
  4618. static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
  4619. { { STATE_PSEXCM }, 'i' },
  4620. { { STATE_PSRING }, 'i' },
  4621. { { STATE_XTSYNC }, 'o' }
  4622. };
  4623. static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
  4624. { { 4 /* ars */ }, 'i' }
  4625. };
  4626. static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
  4627. { { STATE_PSEXCM }, 'i' },
  4628. { { STATE_PSRING }, 'i' }
  4629. };
  4630. static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
  4631. { { 6 /* art */ }, 'o' },
  4632. { { 4 /* ars */ }, 'i' }
  4633. };
  4634. static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
  4635. { { STATE_PSEXCM }, 'i' },
  4636. { { STATE_PSRING }, 'i' }
  4637. };
  4638. static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
  4639. { { 6 /* art */ }, 'i' },
  4640. { { 4 /* ars */ }, 'i' }
  4641. };
  4642. static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
  4643. { { STATE_PSEXCM }, 'i' },
  4644. { { STATE_PSRING }, 'i' }
  4645. };
  4646. static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
  4647. { { STATE_PTBASE }, 'i' },
  4648. { { STATE_EXCVADDR }, 'i' }
  4649. };
  4650. static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
  4651. { { STATE_EXCVADDR }, 'i' }
  4652. };
  4653. static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
  4654. { { STATE_EXCVADDR }, 'i' }
  4655. };
  4656. static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
  4657. { { 6 /* art */ }, 'o' }
  4658. };
  4659. static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
  4660. { { STATE_PSEXCM }, 'i' },
  4661. { { STATE_PSRING }, 'i' },
  4662. { { STATE_CPENABLE }, 'i' }
  4663. };
  4664. static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
  4665. { { 6 /* art */ }, 'i' }
  4666. };
  4667. static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
  4668. { { STATE_PSEXCM }, 'i' },
  4669. { { STATE_PSRING }, 'i' },
  4670. { { STATE_CPENABLE }, 'o' }
  4671. };
  4672. static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
  4673. { { 6 /* art */ }, 'm' }
  4674. };
  4675. static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
  4676. { { STATE_PSEXCM }, 'i' },
  4677. { { STATE_PSRING }, 'i' },
  4678. { { STATE_CPENABLE }, 'm' }
  4679. };
  4680. static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
  4681. { { 3 /* arr */ }, 'o' },
  4682. { { 4 /* ars */ }, 'i' },
  4683. { { 42 /* tp7 */ }, 'i' }
  4684. };
  4685. static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
  4686. { { 3 /* arr */ }, 'o' },
  4687. { { 4 /* ars */ }, 'i' },
  4688. { { 6 /* art */ }, 'i' }
  4689. };
  4690. static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
  4691. { { 6 /* art */ }, 'o' },
  4692. { { 4 /* ars */ }, 'i' }
  4693. };
  4694. static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
  4695. { { 3 /* arr */ }, 'o' },
  4696. { { 4 /* ars */ }, 'i' },
  4697. { { 42 /* tp7 */ }, 'i' }
  4698. };
  4699. static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
  4700. { { 6 /* art */ }, 'o' },
  4701. { { 4 /* ars */ }, 'i' },
  4702. { { 21 /* uimm8x4 */ }, 'i' }
  4703. };
  4704. static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
  4705. { { 6 /* art */ }, 'i' },
  4706. { { 4 /* ars */ }, 'i' },
  4707. { { 21 /* uimm8x4 */ }, 'i' }
  4708. };
  4709. static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
  4710. { { 6 /* art */ }, 'm' },
  4711. { { 4 /* ars */ }, 'i' },
  4712. { { 21 /* uimm8x4 */ }, 'i' }
  4713. };
  4714. static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
  4715. { { STATE_SCOMPARE1 }, 'i' },
  4716. { { STATE_SCOMPARE1 }, 'i' }
  4717. };
  4718. static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
  4719. { { 6 /* art */ }, 'o' }
  4720. };
  4721. static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
  4722. { { STATE_SCOMPARE1 }, 'i' }
  4723. };
  4724. static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
  4725. { { 6 /* art */ }, 'i' }
  4726. };
  4727. static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
  4728. { { STATE_SCOMPARE1 }, 'o' }
  4729. };
  4730. static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
  4731. { { 6 /* art */ }, 'm' }
  4732. };
  4733. static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
  4734. { { STATE_SCOMPARE1 }, 'm' }
  4735. };
  4736. static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
  4737. { { 3 /* arr */ }, 'o' },
  4738. { { 4 /* ars */ }, 'i' },
  4739. { { 6 /* art */ }, 'i' }
  4740. };
  4741. static xtensa_arg_internal Iclass_xt_mul32_args[] = {
  4742. { { 3 /* arr */ }, 'o' },
  4743. { { 4 /* ars */ }, 'i' },
  4744. { { 6 /* art */ }, 'i' }
  4745. };
  4746. static xtensa_arg_internal Iclass_rur_expstate_args[] = {
  4747. { { 3 /* arr */ }, 'o' }
  4748. };
  4749. static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
  4750. { { STATE_EXPSTATE }, 'i' },
  4751. { { STATE_CPENABLE }, 'i' }
  4752. };
  4753. static xtensa_arg_internal Iclass_wur_expstate_args[] = {
  4754. { { 6 /* art */ }, 'i' }
  4755. };
  4756. static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
  4757. { { STATE_EXPSTATE }, 'o' },
  4758. { { STATE_CPENABLE }, 'i' }
  4759. };
  4760. static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
  4761. { { 6 /* art */ }, 'o' }
  4762. };
  4763. static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
  4764. { { STATE_CPENABLE }, 'i' }
  4765. };
  4766. static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
  4767. 0 /* IMPWIRE */
  4768. };
  4769. static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
  4770. { { 91 /* bitindex */ }, 'i' }
  4771. };
  4772. static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
  4773. { { STATE_EXPSTATE }, 'm' },
  4774. { { STATE_CPENABLE }, 'i' }
  4775. };
  4776. static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
  4777. { { 91 /* bitindex */ }, 'i' }
  4778. };
  4779. static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
  4780. { { STATE_EXPSTATE }, 'm' },
  4781. { { STATE_CPENABLE }, 'i' }
  4782. };
  4783. static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
  4784. { { 6 /* art */ }, 'i' },
  4785. { { 4 /* ars */ }, 'i' }
  4786. };
  4787. static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
  4788. { { STATE_EXPSTATE }, 'm' },
  4789. { { STATE_CPENABLE }, 'i' }
  4790. };
  4791. static xtensa_iclass_internal iclasses[] = {
  4792. { 0, 0 /* xt_iclass_excw */,
  4793. 0, 0, 0, 0 },
  4794. { 0, 0 /* xt_iclass_rfe */,
  4795. 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
  4796. { 0, 0 /* xt_iclass_rfde */,
  4797. 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
  4798. { 0, 0 /* xt_iclass_syscall */,
  4799. 0, 0, 0, 0 },
  4800. { 0, 0 /* xt_iclass_simcall */,
  4801. 0, 0, 0, 0 },
  4802. { 2, Iclass_xt_iclass_call12_args,
  4803. 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
  4804. { 2, Iclass_xt_iclass_call8_args,
  4805. 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
  4806. { 2, Iclass_xt_iclass_call4_args,
  4807. 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
  4808. { 2, Iclass_xt_iclass_callx12_args,
  4809. 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
  4810. { 2, Iclass_xt_iclass_callx8_args,
  4811. 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
  4812. { 2, Iclass_xt_iclass_callx4_args,
  4813. 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
  4814. { 3, Iclass_xt_iclass_entry_args,
  4815. 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
  4816. { 2, Iclass_xt_iclass_movsp_args,
  4817. 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
  4818. { 1, Iclass_xt_iclass_rotw_args,
  4819. 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
  4820. { 1, Iclass_xt_iclass_retw_args,
  4821. 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
  4822. { 0, 0 /* xt_iclass_rfwou */,
  4823. 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
  4824. { 3, Iclass_xt_iclass_l32e_args,
  4825. 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
  4826. { 3, Iclass_xt_iclass_s32e_args,
  4827. 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
  4828. { 1, Iclass_xt_iclass_rsr_windowbase_args,
  4829. 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
  4830. { 1, Iclass_xt_iclass_wsr_windowbase_args,
  4831. 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
  4832. { 1, Iclass_xt_iclass_xsr_windowbase_args,
  4833. 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
  4834. { 1, Iclass_xt_iclass_rsr_windowstart_args,
  4835. 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
  4836. { 1, Iclass_xt_iclass_wsr_windowstart_args,
  4837. 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
  4838. { 1, Iclass_xt_iclass_xsr_windowstart_args,
  4839. 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
  4840. { 3, Iclass_xt_iclass_add_n_args,
  4841. 0, 0, 0, 0 },
  4842. { 3, Iclass_xt_iclass_addi_n_args,
  4843. 0, 0, 0, 0 },
  4844. { 2, Iclass_xt_iclass_bz6_args,
  4845. 0, 0, 0, 0 },
  4846. { 0, 0 /* xt_iclass_ill_n */,
  4847. 0, 0, 0, 0 },
  4848. { 3, Iclass_xt_iclass_loadi4_args,
  4849. 0, 0, 0, 0 },
  4850. { 2, Iclass_xt_iclass_mov_n_args,
  4851. 0, 0, 0, 0 },
  4852. { 2, Iclass_xt_iclass_movi_n_args,
  4853. 0, 0, 0, 0 },
  4854. { 0, 0 /* xt_iclass_nopn */,
  4855. 0, 0, 0, 0 },
  4856. { 1, Iclass_xt_iclass_retn_args,
  4857. 0, 0, 0, 0 },
  4858. { 3, Iclass_xt_iclass_storei4_args,
  4859. 0, 0, 0, 0 },
  4860. { 1, Iclass_rur_threadptr_args,
  4861. 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
  4862. { 1, Iclass_wur_threadptr_args,
  4863. 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
  4864. { 3, Iclass_xt_iclass_addi_args,
  4865. 0, 0, 0, 0 },
  4866. { 3, Iclass_xt_iclass_addmi_args,
  4867. 0, 0, 0, 0 },
  4868. { 3, Iclass_xt_iclass_addsub_args,
  4869. 0, 0, 0, 0 },
  4870. { 3, Iclass_xt_iclass_bit_args,
  4871. 0, 0, 0, 0 },
  4872. { 3, Iclass_xt_iclass_bsi8_args,
  4873. 0, 0, 0, 0 },
  4874. { 3, Iclass_xt_iclass_bsi8b_args,
  4875. 0, 0, 0, 0 },
  4876. { 3, Iclass_xt_iclass_bsi8u_args,
  4877. 0, 0, 0, 0 },
  4878. { 3, Iclass_xt_iclass_bst8_args,
  4879. 0, 0, 0, 0 },
  4880. { 2, Iclass_xt_iclass_bsz12_args,
  4881. 0, 0, 0, 0 },
  4882. { 2, Iclass_xt_iclass_call0_args,
  4883. 0, 0, 0, 0 },
  4884. { 2, Iclass_xt_iclass_callx0_args,
  4885. 0, 0, 0, 0 },
  4886. { 4, Iclass_xt_iclass_exti_args,
  4887. 0, 0, 0, 0 },
  4888. { 0, 0 /* xt_iclass_ill */,
  4889. 0, 0, 0, 0 },
  4890. { 1, Iclass_xt_iclass_jump_args,
  4891. 0, 0, 0, 0 },
  4892. { 1, Iclass_xt_iclass_jumpx_args,
  4893. 0, 0, 0, 0 },
  4894. { 3, Iclass_xt_iclass_l16ui_args,
  4895. 0, 0, 0, 0 },
  4896. { 3, Iclass_xt_iclass_l16si_args,
  4897. 0, 0, 0, 0 },
  4898. { 3, Iclass_xt_iclass_l32i_args,
  4899. 0, 0, 0, 0 },
  4900. { 2, Iclass_xt_iclass_l32r_args,
  4901. 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
  4902. { 3, Iclass_xt_iclass_l8i_args,
  4903. 0, 0, 0, 0 },
  4904. { 2, Iclass_xt_iclass_loop_args,
  4905. 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
  4906. { 2, Iclass_xt_iclass_loopz_args,
  4907. 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
  4908. { 2, Iclass_xt_iclass_movi_args,
  4909. 0, 0, 0, 0 },
  4910. { 3, Iclass_xt_iclass_movz_args,
  4911. 0, 0, 0, 0 },
  4912. { 2, Iclass_xt_iclass_neg_args,
  4913. 0, 0, 0, 0 },
  4914. { 0, 0 /* xt_iclass_nop */,
  4915. 0, 0, 0, 0 },
  4916. { 1, Iclass_xt_iclass_return_args,
  4917. 0, 0, 0, 0 },
  4918. { 3, Iclass_xt_iclass_s16i_args,
  4919. 0, 0, 0, 0 },
  4920. { 3, Iclass_xt_iclass_s32i_args,
  4921. 0, 0, 0, 0 },
  4922. { 3, Iclass_xt_iclass_s8i_args,
  4923. 0, 0, 0, 0 },
  4924. { 1, Iclass_xt_iclass_sar_args,
  4925. 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
  4926. { 1, Iclass_xt_iclass_sari_args,
  4927. 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
  4928. { 2, Iclass_xt_iclass_shifts_args,
  4929. 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
  4930. { 3, Iclass_xt_iclass_shiftst_args,
  4931. 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
  4932. { 2, Iclass_xt_iclass_shiftt_args,
  4933. 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
  4934. { 3, Iclass_xt_iclass_slli_args,
  4935. 0, 0, 0, 0 },
  4936. { 3, Iclass_xt_iclass_srai_args,
  4937. 0, 0, 0, 0 },
  4938. { 3, Iclass_xt_iclass_srli_args,
  4939. 0, 0, 0, 0 },
  4940. { 0, 0 /* xt_iclass_memw */,
  4941. 0, 0, 0, 0 },
  4942. { 0, 0 /* xt_iclass_extw */,
  4943. 0, 0, 0, 0 },
  4944. { 0, 0 /* xt_iclass_isync */,
  4945. 0, 0, 0, 0 },
  4946. { 0, 0 /* xt_iclass_sync */,
  4947. 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
  4948. { 2, Iclass_xt_iclass_rsil_args,
  4949. 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
  4950. { 1, Iclass_xt_iclass_rsr_lend_args,
  4951. 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
  4952. { 1, Iclass_xt_iclass_wsr_lend_args,
  4953. 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
  4954. { 1, Iclass_xt_iclass_xsr_lend_args,
  4955. 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
  4956. { 1, Iclass_xt_iclass_rsr_lcount_args,
  4957. 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
  4958. { 1, Iclass_xt_iclass_wsr_lcount_args,
  4959. 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
  4960. { 1, Iclass_xt_iclass_xsr_lcount_args,
  4961. 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
  4962. { 1, Iclass_xt_iclass_rsr_lbeg_args,
  4963. 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
  4964. { 1, Iclass_xt_iclass_wsr_lbeg_args,
  4965. 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
  4966. { 1, Iclass_xt_iclass_xsr_lbeg_args,
  4967. 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
  4968. { 1, Iclass_xt_iclass_rsr_sar_args,
  4969. 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
  4970. { 1, Iclass_xt_iclass_wsr_sar_args,
  4971. 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
  4972. { 1, Iclass_xt_iclass_xsr_sar_args,
  4973. 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
  4974. { 1, Iclass_xt_iclass_rsr_litbase_args,
  4975. 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
  4976. { 1, Iclass_xt_iclass_wsr_litbase_args,
  4977. 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
  4978. { 1, Iclass_xt_iclass_xsr_litbase_args,
  4979. 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
  4980. { 1, Iclass_xt_iclass_rsr_176_args,
  4981. 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
  4982. { 1, Iclass_xt_iclass_rsr_208_args,
  4983. 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
  4984. { 1, Iclass_xt_iclass_rsr_ps_args,
  4985. 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
  4986. { 1, Iclass_xt_iclass_wsr_ps_args,
  4987. 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
  4988. { 1, Iclass_xt_iclass_xsr_ps_args,
  4989. 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
  4990. { 1, Iclass_xt_iclass_rsr_epc1_args,
  4991. 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
  4992. { 1, Iclass_xt_iclass_wsr_epc1_args,
  4993. 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
  4994. { 1, Iclass_xt_iclass_xsr_epc1_args,
  4995. 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
  4996. { 1, Iclass_xt_iclass_rsr_excsave1_args,
  4997. 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
  4998. { 1, Iclass_xt_iclass_wsr_excsave1_args,
  4999. 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
  5000. { 1, Iclass_xt_iclass_xsr_excsave1_args,
  5001. 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
  5002. { 1, Iclass_xt_iclass_rsr_epc2_args,
  5003. 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
  5004. { 1, Iclass_xt_iclass_wsr_epc2_args,
  5005. 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
  5006. { 1, Iclass_xt_iclass_xsr_epc2_args,
  5007. 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
  5008. { 1, Iclass_xt_iclass_rsr_excsave2_args,
  5009. 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
  5010. { 1, Iclass_xt_iclass_wsr_excsave2_args,
  5011. 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
  5012. { 1, Iclass_xt_iclass_xsr_excsave2_args,
  5013. 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
  5014. { 1, Iclass_xt_iclass_rsr_epc3_args,
  5015. 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
  5016. { 1, Iclass_xt_iclass_wsr_epc3_args,
  5017. 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
  5018. { 1, Iclass_xt_iclass_xsr_epc3_args,
  5019. 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
  5020. { 1, Iclass_xt_iclass_rsr_excsave3_args,
  5021. 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
  5022. { 1, Iclass_xt_iclass_wsr_excsave3_args,
  5023. 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
  5024. { 1, Iclass_xt_iclass_xsr_excsave3_args,
  5025. 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
  5026. { 1, Iclass_xt_iclass_rsr_epc4_args,
  5027. 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
  5028. { 1, Iclass_xt_iclass_wsr_epc4_args,
  5029. 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
  5030. { 1, Iclass_xt_iclass_xsr_epc4_args,
  5031. 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
  5032. { 1, Iclass_xt_iclass_rsr_excsave4_args,
  5033. 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
  5034. { 1, Iclass_xt_iclass_wsr_excsave4_args,
  5035. 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
  5036. { 1, Iclass_xt_iclass_xsr_excsave4_args,
  5037. 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
  5038. { 1, Iclass_xt_iclass_rsr_epc5_args,
  5039. 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
  5040. { 1, Iclass_xt_iclass_wsr_epc5_args,
  5041. 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
  5042. { 1, Iclass_xt_iclass_xsr_epc5_args,
  5043. 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
  5044. { 1, Iclass_xt_iclass_rsr_excsave5_args,
  5045. 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
  5046. { 1, Iclass_xt_iclass_wsr_excsave5_args,
  5047. 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
  5048. { 1, Iclass_xt_iclass_xsr_excsave5_args,
  5049. 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
  5050. { 1, Iclass_xt_iclass_rsr_epc6_args,
  5051. 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
  5052. { 1, Iclass_xt_iclass_wsr_epc6_args,
  5053. 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
  5054. { 1, Iclass_xt_iclass_xsr_epc6_args,
  5055. 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
  5056. { 1, Iclass_xt_iclass_rsr_excsave6_args,
  5057. 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
  5058. { 1, Iclass_xt_iclass_wsr_excsave6_args,
  5059. 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
  5060. { 1, Iclass_xt_iclass_xsr_excsave6_args,
  5061. 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
  5062. { 1, Iclass_xt_iclass_rsr_epc7_args,
  5063. 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
  5064. { 1, Iclass_xt_iclass_wsr_epc7_args,
  5065. 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
  5066. { 1, Iclass_xt_iclass_xsr_epc7_args,
  5067. 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
  5068. { 1, Iclass_xt_iclass_rsr_excsave7_args,
  5069. 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
  5070. { 1, Iclass_xt_iclass_wsr_excsave7_args,
  5071. 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
  5072. { 1, Iclass_xt_iclass_xsr_excsave7_args,
  5073. 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
  5074. { 1, Iclass_xt_iclass_rsr_eps2_args,
  5075. 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
  5076. { 1, Iclass_xt_iclass_wsr_eps2_args,
  5077. 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
  5078. { 1, Iclass_xt_iclass_xsr_eps2_args,
  5079. 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
  5080. { 1, Iclass_xt_iclass_rsr_eps3_args,
  5081. 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
  5082. { 1, Iclass_xt_iclass_wsr_eps3_args,
  5083. 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
  5084. { 1, Iclass_xt_iclass_xsr_eps3_args,
  5085. 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
  5086. { 1, Iclass_xt_iclass_rsr_eps4_args,
  5087. 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
  5088. { 1, Iclass_xt_iclass_wsr_eps4_args,
  5089. 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
  5090. { 1, Iclass_xt_iclass_xsr_eps4_args,
  5091. 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
  5092. { 1, Iclass_xt_iclass_rsr_eps5_args,
  5093. 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
  5094. { 1, Iclass_xt_iclass_wsr_eps5_args,
  5095. 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
  5096. { 1, Iclass_xt_iclass_xsr_eps5_args,
  5097. 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
  5098. { 1, Iclass_xt_iclass_rsr_eps6_args,
  5099. 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
  5100. { 1, Iclass_xt_iclass_wsr_eps6_args,
  5101. 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
  5102. { 1, Iclass_xt_iclass_xsr_eps6_args,
  5103. 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
  5104. { 1, Iclass_xt_iclass_rsr_eps7_args,
  5105. 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
  5106. { 1, Iclass_xt_iclass_wsr_eps7_args,
  5107. 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
  5108. { 1, Iclass_xt_iclass_xsr_eps7_args,
  5109. 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
  5110. { 1, Iclass_xt_iclass_rsr_excvaddr_args,
  5111. 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
  5112. { 1, Iclass_xt_iclass_wsr_excvaddr_args,
  5113. 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
  5114. { 1, Iclass_xt_iclass_xsr_excvaddr_args,
  5115. 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
  5116. { 1, Iclass_xt_iclass_rsr_depc_args,
  5117. 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
  5118. { 1, Iclass_xt_iclass_wsr_depc_args,
  5119. 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
  5120. { 1, Iclass_xt_iclass_xsr_depc_args,
  5121. 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
  5122. { 1, Iclass_xt_iclass_rsr_exccause_args,
  5123. 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
  5124. { 1, Iclass_xt_iclass_wsr_exccause_args,
  5125. 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
  5126. { 1, Iclass_xt_iclass_xsr_exccause_args,
  5127. 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
  5128. { 1, Iclass_xt_iclass_rsr_misc0_args,
  5129. 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
  5130. { 1, Iclass_xt_iclass_wsr_misc0_args,
  5131. 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
  5132. { 1, Iclass_xt_iclass_xsr_misc0_args,
  5133. 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
  5134. { 1, Iclass_xt_iclass_rsr_misc1_args,
  5135. 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
  5136. { 1, Iclass_xt_iclass_wsr_misc1_args,
  5137. 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
  5138. { 1, Iclass_xt_iclass_xsr_misc1_args,
  5139. 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
  5140. { 1, Iclass_xt_iclass_rsr_prid_args,
  5141. 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
  5142. { 1, Iclass_xt_iclass_rsr_vecbase_args,
  5143. 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
  5144. { 1, Iclass_xt_iclass_wsr_vecbase_args,
  5145. 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
  5146. { 1, Iclass_xt_iclass_xsr_vecbase_args,
  5147. 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
  5148. { 2, Iclass_xt_iclass_mac16_aa_args,
  5149. 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
  5150. { 2, Iclass_xt_iclass_mac16_ad_args,
  5151. 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
  5152. { 2, Iclass_xt_iclass_mac16_da_args,
  5153. 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
  5154. { 2, Iclass_xt_iclass_mac16_dd_args,
  5155. 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
  5156. { 2, Iclass_xt_iclass_mac16a_aa_args,
  5157. 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
  5158. { 2, Iclass_xt_iclass_mac16a_ad_args,
  5159. 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
  5160. { 2, Iclass_xt_iclass_mac16a_da_args,
  5161. 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
  5162. { 2, Iclass_xt_iclass_mac16a_dd_args,
  5163. 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
  5164. { 4, Iclass_xt_iclass_mac16al_da_args,
  5165. 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
  5166. { 4, Iclass_xt_iclass_mac16al_dd_args,
  5167. 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
  5168. { 2, Iclass_xt_iclass_mac16_l_args,
  5169. 0, 0, 0, 0 },
  5170. { 3, Iclass_xt_iclass_mul16_args,
  5171. 0, 0, 0, 0 },
  5172. { 2, Iclass_xt_iclass_rsr_m0_args,
  5173. 0, 0, 0, 0 },
  5174. { 2, Iclass_xt_iclass_wsr_m0_args,
  5175. 0, 0, 0, 0 },
  5176. { 2, Iclass_xt_iclass_xsr_m0_args,
  5177. 0, 0, 0, 0 },
  5178. { 2, Iclass_xt_iclass_rsr_m1_args,
  5179. 0, 0, 0, 0 },
  5180. { 2, Iclass_xt_iclass_wsr_m1_args,
  5181. 0, 0, 0, 0 },
  5182. { 2, Iclass_xt_iclass_xsr_m1_args,
  5183. 0, 0, 0, 0 },
  5184. { 2, Iclass_xt_iclass_rsr_m2_args,
  5185. 0, 0, 0, 0 },
  5186. { 2, Iclass_xt_iclass_wsr_m2_args,
  5187. 0, 0, 0, 0 },
  5188. { 2, Iclass_xt_iclass_xsr_m2_args,
  5189. 0, 0, 0, 0 },
  5190. { 2, Iclass_xt_iclass_rsr_m3_args,
  5191. 0, 0, 0, 0 },
  5192. { 2, Iclass_xt_iclass_wsr_m3_args,
  5193. 0, 0, 0, 0 },
  5194. { 2, Iclass_xt_iclass_xsr_m3_args,
  5195. 0, 0, 0, 0 },
  5196. { 1, Iclass_xt_iclass_rsr_acclo_args,
  5197. 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
  5198. { 1, Iclass_xt_iclass_wsr_acclo_args,
  5199. 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
  5200. { 1, Iclass_xt_iclass_xsr_acclo_args,
  5201. 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
  5202. { 1, Iclass_xt_iclass_rsr_acchi_args,
  5203. 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
  5204. { 1, Iclass_xt_iclass_wsr_acchi_args,
  5205. 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
  5206. { 1, Iclass_xt_iclass_xsr_acchi_args,
  5207. 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
  5208. { 1, Iclass_xt_iclass_rfi_args,
  5209. 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
  5210. { 1, Iclass_xt_iclass_wait_args,
  5211. 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
  5212. { 1, Iclass_xt_iclass_rsr_interrupt_args,
  5213. 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
  5214. { 1, Iclass_xt_iclass_wsr_intset_args,
  5215. 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
  5216. { 1, Iclass_xt_iclass_wsr_intclear_args,
  5217. 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
  5218. { 1, Iclass_xt_iclass_rsr_intenable_args,
  5219. 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
  5220. { 1, Iclass_xt_iclass_wsr_intenable_args,
  5221. 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
  5222. { 1, Iclass_xt_iclass_xsr_intenable_args,
  5223. 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
  5224. { 2, Iclass_xt_iclass_break_args,
  5225. 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
  5226. { 1, Iclass_xt_iclass_break_n_args,
  5227. 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
  5228. { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
  5229. 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
  5230. { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
  5231. 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
  5232. { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
  5233. 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
  5234. { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
  5235. 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
  5236. { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
  5237. 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
  5238. { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
  5239. 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
  5240. { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
  5241. 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
  5242. { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
  5243. 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
  5244. { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
  5245. 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
  5246. { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
  5247. 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
  5248. { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
  5249. 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
  5250. { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
  5251. 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
  5252. { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
  5253. 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
  5254. { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
  5255. 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
  5256. { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
  5257. 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
  5258. { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
  5259. 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
  5260. { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
  5261. 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
  5262. { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
  5263. 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
  5264. { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
  5265. 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
  5266. { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
  5267. 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
  5268. { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
  5269. 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
  5270. { 1, Iclass_xt_iclass_rsr_debugcause_args,
  5271. 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
  5272. { 1, Iclass_xt_iclass_wsr_debugcause_args,
  5273. 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
  5274. { 1, Iclass_xt_iclass_xsr_debugcause_args,
  5275. 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
  5276. { 1, Iclass_xt_iclass_rsr_icount_args,
  5277. 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
  5278. { 1, Iclass_xt_iclass_wsr_icount_args,
  5279. 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
  5280. { 1, Iclass_xt_iclass_xsr_icount_args,
  5281. 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
  5282. { 1, Iclass_xt_iclass_rsr_icountlevel_args,
  5283. 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
  5284. { 1, Iclass_xt_iclass_wsr_icountlevel_args,
  5285. 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
  5286. { 1, Iclass_xt_iclass_xsr_icountlevel_args,
  5287. 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
  5288. { 1, Iclass_xt_iclass_rsr_ddr_args,
  5289. 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
  5290. { 1, Iclass_xt_iclass_wsr_ddr_args,
  5291. 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
  5292. { 1, Iclass_xt_iclass_xsr_ddr_args,
  5293. 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
  5294. { 1, Iclass_xt_iclass_rfdo_args,
  5295. 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
  5296. { 0, 0 /* xt_iclass_rfdd */,
  5297. 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
  5298. { 1, Iclass_xt_iclass_wsr_mmid_args,
  5299. 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
  5300. { 1, Iclass_xt_iclass_rsr_ccount_args,
  5301. 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
  5302. { 1, Iclass_xt_iclass_wsr_ccount_args,
  5303. 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
  5304. { 1, Iclass_xt_iclass_xsr_ccount_args,
  5305. 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
  5306. { 1, Iclass_xt_iclass_rsr_ccompare0_args,
  5307. 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
  5308. { 1, Iclass_xt_iclass_wsr_ccompare0_args,
  5309. 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
  5310. { 1, Iclass_xt_iclass_xsr_ccompare0_args,
  5311. 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
  5312. { 1, Iclass_xt_iclass_rsr_ccompare1_args,
  5313. 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
  5314. { 1, Iclass_xt_iclass_wsr_ccompare1_args,
  5315. 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
  5316. { 1, Iclass_xt_iclass_xsr_ccompare1_args,
  5317. 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
  5318. { 1, Iclass_xt_iclass_rsr_ccompare2_args,
  5319. 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
  5320. { 1, Iclass_xt_iclass_wsr_ccompare2_args,
  5321. 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
  5322. { 1, Iclass_xt_iclass_xsr_ccompare2_args,
  5323. 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
  5324. { 2, Iclass_xt_iclass_icache_args,
  5325. 0, 0, 0, 0 },
  5326. { 2, Iclass_xt_iclass_icache_lock_args,
  5327. 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
  5328. { 2, Iclass_xt_iclass_icache_inv_args,
  5329. 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
  5330. { 2, Iclass_xt_iclass_licx_args,
  5331. 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
  5332. { 2, Iclass_xt_iclass_sicx_args,
  5333. 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
  5334. { 2, Iclass_xt_iclass_dcache_args,
  5335. 0, 0, 0, 0 },
  5336. { 2, Iclass_xt_iclass_dcache_ind_args,
  5337. 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
  5338. { 2, Iclass_xt_iclass_dcache_inv_args,
  5339. 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
  5340. { 2, Iclass_xt_iclass_dpf_args,
  5341. 0, 0, 0, 0 },
  5342. { 2, Iclass_xt_iclass_dcache_lock_args,
  5343. 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
  5344. { 2, Iclass_xt_iclass_sdct_args,
  5345. 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
  5346. { 2, Iclass_xt_iclass_ldct_args,
  5347. 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
  5348. { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
  5349. 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
  5350. { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
  5351. 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
  5352. { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
  5353. 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
  5354. { 1, Iclass_xt_iclass_rsr_rasid_args,
  5355. 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
  5356. { 1, Iclass_xt_iclass_wsr_rasid_args,
  5357. 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
  5358. { 1, Iclass_xt_iclass_xsr_rasid_args,
  5359. 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
  5360. { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
  5361. 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
  5362. { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
  5363. 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
  5364. { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
  5365. 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
  5366. { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
  5367. 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
  5368. { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
  5369. 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
  5370. { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
  5371. 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
  5372. { 1, Iclass_xt_iclass_idtlb_args,
  5373. 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
  5374. { 2, Iclass_xt_iclass_rdtlb_args,
  5375. 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
  5376. { 2, Iclass_xt_iclass_wdtlb_args,
  5377. 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
  5378. { 1, Iclass_xt_iclass_iitlb_args,
  5379. 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
  5380. { 2, Iclass_xt_iclass_ritlb_args,
  5381. 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
  5382. { 2, Iclass_xt_iclass_witlb_args,
  5383. 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
  5384. { 0, 0 /* xt_iclass_ldpte */,
  5385. 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
  5386. { 0, 0 /* xt_iclass_hwwitlba */,
  5387. 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
  5388. { 0, 0 /* xt_iclass_hwwdtlba */,
  5389. 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
  5390. { 1, Iclass_xt_iclass_rsr_cpenable_args,
  5391. 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
  5392. { 1, Iclass_xt_iclass_wsr_cpenable_args,
  5393. 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
  5394. { 1, Iclass_xt_iclass_xsr_cpenable_args,
  5395. 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
  5396. { 3, Iclass_xt_iclass_clamp_args,
  5397. 0, 0, 0, 0 },
  5398. { 3, Iclass_xt_iclass_minmax_args,
  5399. 0, 0, 0, 0 },
  5400. { 2, Iclass_xt_iclass_nsa_args,
  5401. 0, 0, 0, 0 },
  5402. { 3, Iclass_xt_iclass_sx_args,
  5403. 0, 0, 0, 0 },
  5404. { 3, Iclass_xt_iclass_l32ai_args,
  5405. 0, 0, 0, 0 },
  5406. { 3, Iclass_xt_iclass_s32ri_args,
  5407. 0, 0, 0, 0 },
  5408. { 3, Iclass_xt_iclass_s32c1i_args,
  5409. 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
  5410. { 1, Iclass_xt_iclass_rsr_scompare1_args,
  5411. 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
  5412. { 1, Iclass_xt_iclass_wsr_scompare1_args,
  5413. 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
  5414. { 1, Iclass_xt_iclass_xsr_scompare1_args,
  5415. 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
  5416. { 3, Iclass_xt_iclass_div_args,
  5417. 0, 0, 0, 0 },
  5418. { 3, Iclass_xt_mul32_args,
  5419. 0, 0, 0, 0 },
  5420. { 1, Iclass_rur_expstate_args,
  5421. 2, Iclass_rur_expstate_stateArgs, 0, 0 },
  5422. { 1, Iclass_wur_expstate_args,
  5423. 2, Iclass_wur_expstate_stateArgs, 0, 0 },
  5424. { 1, Iclass_iclass_READ_IMPWIRE_args,
  5425. 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
  5426. { 1, Iclass_iclass_SETB_EXPSTATE_args,
  5427. 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
  5428. { 1, Iclass_iclass_CLRB_EXPSTATE_args,
  5429. 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
  5430. { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
  5431. 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
  5432. };
  5433. /* Opcode encodings. */
  5434. static void
  5435. Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5436. {
  5437. slotbuf[0] = 0x2080;
  5438. }
  5439. static void
  5440. Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5441. {
  5442. slotbuf[0] = 0x3000;
  5443. }
  5444. static void
  5445. Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5446. {
  5447. slotbuf[0] = 0x3200;
  5448. }
  5449. static void
  5450. Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5451. {
  5452. slotbuf[0] = 0x5000;
  5453. }
  5454. static void
  5455. Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5456. {
  5457. slotbuf[0] = 0x5100;
  5458. }
  5459. static void
  5460. Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5461. {
  5462. slotbuf[0] = 0x35;
  5463. }
  5464. static void
  5465. Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5466. {
  5467. slotbuf[0] = 0x25;
  5468. }
  5469. static void
  5470. Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5471. {
  5472. slotbuf[0] = 0x15;
  5473. }
  5474. static void
  5475. Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5476. {
  5477. slotbuf[0] = 0xf0;
  5478. }
  5479. static void
  5480. Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5481. {
  5482. slotbuf[0] = 0xe0;
  5483. }
  5484. static void
  5485. Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5486. {
  5487. slotbuf[0] = 0xd0;
  5488. }
  5489. static void
  5490. Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5491. {
  5492. slotbuf[0] = 0x36;
  5493. }
  5494. static void
  5495. Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5496. {
  5497. slotbuf[0] = 0x1000;
  5498. }
  5499. static void
  5500. Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5501. {
  5502. slotbuf[0] = 0x408000;
  5503. }
  5504. static void
  5505. Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5506. {
  5507. slotbuf[0] = 0x90;
  5508. }
  5509. static void
  5510. Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  5511. {
  5512. slotbuf[0] = 0xf01d;
  5513. }
  5514. static void
  5515. Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5516. {
  5517. slotbuf[0] = 0x3400;
  5518. }
  5519. static void
  5520. Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5521. {
  5522. slotbuf[0] = 0x3500;
  5523. }
  5524. static void
  5525. Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5526. {
  5527. slotbuf[0] = 0x90000;
  5528. }
  5529. static void
  5530. Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5531. {
  5532. slotbuf[0] = 0x490000;
  5533. }
  5534. static void
  5535. Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5536. {
  5537. slotbuf[0] = 0x34800;
  5538. }
  5539. static void
  5540. Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5541. {
  5542. slotbuf[0] = 0x134800;
  5543. }
  5544. static void
  5545. Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5546. {
  5547. slotbuf[0] = 0x614800;
  5548. }
  5549. static void
  5550. Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5551. {
  5552. slotbuf[0] = 0x34900;
  5553. }
  5554. static void
  5555. Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5556. {
  5557. slotbuf[0] = 0x134900;
  5558. }
  5559. static void
  5560. Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5561. {
  5562. slotbuf[0] = 0x614900;
  5563. }
  5564. static void
  5565. Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
  5566. {
  5567. slotbuf[0] = 0xa;
  5568. }
  5569. static void
  5570. Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
  5571. {
  5572. slotbuf[0] = 0xb;
  5573. }
  5574. static void
  5575. Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  5576. {
  5577. slotbuf[0] = 0x8c;
  5578. }
  5579. static void
  5580. Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  5581. {
  5582. slotbuf[0] = 0xcc;
  5583. }
  5584. static void
  5585. Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  5586. {
  5587. slotbuf[0] = 0xf06d;
  5588. }
  5589. static void
  5590. Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
  5591. {
  5592. slotbuf[0] = 0x8;
  5593. }
  5594. static void
  5595. Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  5596. {
  5597. slotbuf[0] = 0xd;
  5598. }
  5599. static void
  5600. Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  5601. {
  5602. slotbuf[0] = 0xc;
  5603. }
  5604. static void
  5605. Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  5606. {
  5607. slotbuf[0] = 0xf03d;
  5608. }
  5609. static void
  5610. Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  5611. {
  5612. slotbuf[0] = 0xf00d;
  5613. }
  5614. static void
  5615. Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
  5616. {
  5617. slotbuf[0] = 0x9;
  5618. }
  5619. static void
  5620. Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5621. {
  5622. slotbuf[0] = 0xe30e70;
  5623. }
  5624. static void
  5625. Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5626. {
  5627. slotbuf[0] = 0xf3e700;
  5628. }
  5629. static void
  5630. Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5631. {
  5632. slotbuf[0] = 0xc002;
  5633. }
  5634. static void
  5635. Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5636. {
  5637. slotbuf[0] = 0xd002;
  5638. }
  5639. static void
  5640. Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5641. {
  5642. slotbuf[0] = 0x800000;
  5643. }
  5644. static void
  5645. Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5646. {
  5647. slotbuf[0] = 0xc00000;
  5648. }
  5649. static void
  5650. Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5651. {
  5652. slotbuf[0] = 0x900000;
  5653. }
  5654. static void
  5655. Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5656. {
  5657. slotbuf[0] = 0xa00000;
  5658. }
  5659. static void
  5660. Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5661. {
  5662. slotbuf[0] = 0xb00000;
  5663. }
  5664. static void
  5665. Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5666. {
  5667. slotbuf[0] = 0xd00000;
  5668. }
  5669. static void
  5670. Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5671. {
  5672. slotbuf[0] = 0xe00000;
  5673. }
  5674. static void
  5675. Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5676. {
  5677. slotbuf[0] = 0xf00000;
  5678. }
  5679. static void
  5680. Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5681. {
  5682. slotbuf[0] = 0x100000;
  5683. }
  5684. static void
  5685. Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5686. {
  5687. slotbuf[0] = 0x200000;
  5688. }
  5689. static void
  5690. Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5691. {
  5692. slotbuf[0] = 0x300000;
  5693. }
  5694. static void
  5695. Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5696. {
  5697. slotbuf[0] = 0x26;
  5698. }
  5699. static void
  5700. Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5701. {
  5702. slotbuf[0] = 0x66;
  5703. }
  5704. static void
  5705. Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5706. {
  5707. slotbuf[0] = 0xe6;
  5708. }
  5709. static void
  5710. Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5711. {
  5712. slotbuf[0] = 0xa6;
  5713. }
  5714. static void
  5715. Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5716. {
  5717. slotbuf[0] = 0x6007;
  5718. }
  5719. static void
  5720. Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5721. {
  5722. slotbuf[0] = 0xe007;
  5723. }
  5724. static void
  5725. Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5726. {
  5727. slotbuf[0] = 0xf6;
  5728. }
  5729. static void
  5730. Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5731. {
  5732. slotbuf[0] = 0xb6;
  5733. }
  5734. static void
  5735. Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5736. {
  5737. slotbuf[0] = 0x1007;
  5738. }
  5739. static void
  5740. Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5741. {
  5742. slotbuf[0] = 0x9007;
  5743. }
  5744. static void
  5745. Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5746. {
  5747. slotbuf[0] = 0xa007;
  5748. }
  5749. static void
  5750. Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5751. {
  5752. slotbuf[0] = 0x2007;
  5753. }
  5754. static void
  5755. Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5756. {
  5757. slotbuf[0] = 0xb007;
  5758. }
  5759. static void
  5760. Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5761. {
  5762. slotbuf[0] = 0x3007;
  5763. }
  5764. static void
  5765. Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5766. {
  5767. slotbuf[0] = 0x8007;
  5768. }
  5769. static void
  5770. Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5771. {
  5772. slotbuf[0] = 0x7;
  5773. }
  5774. static void
  5775. Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5776. {
  5777. slotbuf[0] = 0x4007;
  5778. }
  5779. static void
  5780. Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5781. {
  5782. slotbuf[0] = 0xc007;
  5783. }
  5784. static void
  5785. Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5786. {
  5787. slotbuf[0] = 0x5007;
  5788. }
  5789. static void
  5790. Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5791. {
  5792. slotbuf[0] = 0xd007;
  5793. }
  5794. static void
  5795. Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5796. {
  5797. slotbuf[0] = 0x16;
  5798. }
  5799. static void
  5800. Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5801. {
  5802. slotbuf[0] = 0x56;
  5803. }
  5804. static void
  5805. Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5806. {
  5807. slotbuf[0] = 0xd6;
  5808. }
  5809. static void
  5810. Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5811. {
  5812. slotbuf[0] = 0x96;
  5813. }
  5814. static void
  5815. Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5816. {
  5817. slotbuf[0] = 0x5;
  5818. }
  5819. static void
  5820. Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5821. {
  5822. slotbuf[0] = 0xc0;
  5823. }
  5824. static void
  5825. Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5826. {
  5827. slotbuf[0] = 0x40000;
  5828. }
  5829. static void
  5830. Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5831. {
  5832. slotbuf[0] = 0;
  5833. }
  5834. static void
  5835. Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5836. {
  5837. slotbuf[0] = 0x6;
  5838. }
  5839. static void
  5840. Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5841. {
  5842. slotbuf[0] = 0xa0;
  5843. }
  5844. static void
  5845. Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5846. {
  5847. slotbuf[0] = 0x1002;
  5848. }
  5849. static void
  5850. Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5851. {
  5852. slotbuf[0] = 0x9002;
  5853. }
  5854. static void
  5855. Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5856. {
  5857. slotbuf[0] = 0x2002;
  5858. }
  5859. static void
  5860. Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5861. {
  5862. slotbuf[0] = 0x1;
  5863. }
  5864. static void
  5865. Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5866. {
  5867. slotbuf[0] = 0x2;
  5868. }
  5869. static void
  5870. Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5871. {
  5872. slotbuf[0] = 0x8076;
  5873. }
  5874. static void
  5875. Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5876. {
  5877. slotbuf[0] = 0x9076;
  5878. }
  5879. static void
  5880. Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5881. {
  5882. slotbuf[0] = 0xa076;
  5883. }
  5884. static void
  5885. Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5886. {
  5887. slotbuf[0] = 0xa002;
  5888. }
  5889. static void
  5890. Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5891. {
  5892. slotbuf[0] = 0x830000;
  5893. }
  5894. static void
  5895. Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5896. {
  5897. slotbuf[0] = 0x930000;
  5898. }
  5899. static void
  5900. Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5901. {
  5902. slotbuf[0] = 0xa30000;
  5903. }
  5904. static void
  5905. Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5906. {
  5907. slotbuf[0] = 0xb30000;
  5908. }
  5909. static void
  5910. Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5911. {
  5912. slotbuf[0] = 0x600000;
  5913. }
  5914. static void
  5915. Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5916. {
  5917. slotbuf[0] = 0x600100;
  5918. }
  5919. static void
  5920. Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5921. {
  5922. slotbuf[0] = 0x20f0;
  5923. }
  5924. static void
  5925. Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5926. {
  5927. slotbuf[0] = 0x80;
  5928. }
  5929. static void
  5930. Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5931. {
  5932. slotbuf[0] = 0x5002;
  5933. }
  5934. static void
  5935. Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5936. {
  5937. slotbuf[0] = 0x6002;
  5938. }
  5939. static void
  5940. Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5941. {
  5942. slotbuf[0] = 0x4002;
  5943. }
  5944. static void
  5945. Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5946. {
  5947. slotbuf[0] = 0x400000;
  5948. }
  5949. static void
  5950. Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5951. {
  5952. slotbuf[0] = 0x401000;
  5953. }
  5954. static void
  5955. Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5956. {
  5957. slotbuf[0] = 0x402000;
  5958. }
  5959. static void
  5960. Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5961. {
  5962. slotbuf[0] = 0x403000;
  5963. }
  5964. static void
  5965. Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5966. {
  5967. slotbuf[0] = 0x404000;
  5968. }
  5969. static void
  5970. Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5971. {
  5972. slotbuf[0] = 0xa10000;
  5973. }
  5974. static void
  5975. Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5976. {
  5977. slotbuf[0] = 0x810000;
  5978. }
  5979. static void
  5980. Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5981. {
  5982. slotbuf[0] = 0x910000;
  5983. }
  5984. static void
  5985. Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5986. {
  5987. slotbuf[0] = 0xb10000;
  5988. }
  5989. static void
  5990. Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5991. {
  5992. slotbuf[0] = 0x10000;
  5993. }
  5994. static void
  5995. Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
  5996. {
  5997. slotbuf[0] = 0x210000;
  5998. }
  5999. static void
  6000. Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6001. {
  6002. slotbuf[0] = 0x410000;
  6003. }
  6004. static void
  6005. Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6006. {
  6007. slotbuf[0] = 0x20c0;
  6008. }
  6009. static void
  6010. Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6011. {
  6012. slotbuf[0] = 0x20d0;
  6013. }
  6014. static void
  6015. Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6016. {
  6017. slotbuf[0] = 0x2000;
  6018. }
  6019. static void
  6020. Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6021. {
  6022. slotbuf[0] = 0x2010;
  6023. }
  6024. static void
  6025. Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6026. {
  6027. slotbuf[0] = 0x2020;
  6028. }
  6029. static void
  6030. Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6031. {
  6032. slotbuf[0] = 0x2030;
  6033. }
  6034. static void
  6035. Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6036. {
  6037. slotbuf[0] = 0x6000;
  6038. }
  6039. static void
  6040. Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6041. {
  6042. slotbuf[0] = 0x30100;
  6043. }
  6044. static void
  6045. Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6046. {
  6047. slotbuf[0] = 0x130100;
  6048. }
  6049. static void
  6050. Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6051. {
  6052. slotbuf[0] = 0x610100;
  6053. }
  6054. static void
  6055. Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6056. {
  6057. slotbuf[0] = 0x30200;
  6058. }
  6059. static void
  6060. Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6061. {
  6062. slotbuf[0] = 0x130200;
  6063. }
  6064. static void
  6065. Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6066. {
  6067. slotbuf[0] = 0x610200;
  6068. }
  6069. static void
  6070. Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6071. {
  6072. slotbuf[0] = 0x30000;
  6073. }
  6074. static void
  6075. Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6076. {
  6077. slotbuf[0] = 0x130000;
  6078. }
  6079. static void
  6080. Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6081. {
  6082. slotbuf[0] = 0x610000;
  6083. }
  6084. static void
  6085. Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6086. {
  6087. slotbuf[0] = 0x30300;
  6088. }
  6089. static void
  6090. Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6091. {
  6092. slotbuf[0] = 0x130300;
  6093. }
  6094. static void
  6095. Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6096. {
  6097. slotbuf[0] = 0x610300;
  6098. }
  6099. static void
  6100. Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6101. {
  6102. slotbuf[0] = 0x30500;
  6103. }
  6104. static void
  6105. Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6106. {
  6107. slotbuf[0] = 0x130500;
  6108. }
  6109. static void
  6110. Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6111. {
  6112. slotbuf[0] = 0x610500;
  6113. }
  6114. static void
  6115. Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6116. {
  6117. slotbuf[0] = 0x3b000;
  6118. }
  6119. static void
  6120. Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6121. {
  6122. slotbuf[0] = 0x3d000;
  6123. }
  6124. static void
  6125. Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6126. {
  6127. slotbuf[0] = 0x3e600;
  6128. }
  6129. static void
  6130. Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6131. {
  6132. slotbuf[0] = 0x13e600;
  6133. }
  6134. static void
  6135. Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6136. {
  6137. slotbuf[0] = 0x61e600;
  6138. }
  6139. static void
  6140. Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6141. {
  6142. slotbuf[0] = 0x3b100;
  6143. }
  6144. static void
  6145. Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6146. {
  6147. slotbuf[0] = 0x13b100;
  6148. }
  6149. static void
  6150. Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6151. {
  6152. slotbuf[0] = 0x61b100;
  6153. }
  6154. static void
  6155. Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6156. {
  6157. slotbuf[0] = 0x3d100;
  6158. }
  6159. static void
  6160. Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6161. {
  6162. slotbuf[0] = 0x13d100;
  6163. }
  6164. static void
  6165. Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6166. {
  6167. slotbuf[0] = 0x61d100;
  6168. }
  6169. static void
  6170. Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6171. {
  6172. slotbuf[0] = 0x3b200;
  6173. }
  6174. static void
  6175. Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6176. {
  6177. slotbuf[0] = 0x13b200;
  6178. }
  6179. static void
  6180. Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6181. {
  6182. slotbuf[0] = 0x61b200;
  6183. }
  6184. static void
  6185. Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6186. {
  6187. slotbuf[0] = 0x3d200;
  6188. }
  6189. static void
  6190. Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6191. {
  6192. slotbuf[0] = 0x13d200;
  6193. }
  6194. static void
  6195. Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6196. {
  6197. slotbuf[0] = 0x61d200;
  6198. }
  6199. static void
  6200. Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6201. {
  6202. slotbuf[0] = 0x3b300;
  6203. }
  6204. static void
  6205. Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6206. {
  6207. slotbuf[0] = 0x13b300;
  6208. }
  6209. static void
  6210. Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6211. {
  6212. slotbuf[0] = 0x61b300;
  6213. }
  6214. static void
  6215. Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6216. {
  6217. slotbuf[0] = 0x3d300;
  6218. }
  6219. static void
  6220. Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6221. {
  6222. slotbuf[0] = 0x13d300;
  6223. }
  6224. static void
  6225. Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6226. {
  6227. slotbuf[0] = 0x61d300;
  6228. }
  6229. static void
  6230. Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6231. {
  6232. slotbuf[0] = 0x3b400;
  6233. }
  6234. static void
  6235. Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6236. {
  6237. slotbuf[0] = 0x13b400;
  6238. }
  6239. static void
  6240. Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6241. {
  6242. slotbuf[0] = 0x61b400;
  6243. }
  6244. static void
  6245. Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6246. {
  6247. slotbuf[0] = 0x3d400;
  6248. }
  6249. static void
  6250. Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6251. {
  6252. slotbuf[0] = 0x13d400;
  6253. }
  6254. static void
  6255. Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6256. {
  6257. slotbuf[0] = 0x61d400;
  6258. }
  6259. static void
  6260. Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6261. {
  6262. slotbuf[0] = 0x3b500;
  6263. }
  6264. static void
  6265. Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6266. {
  6267. slotbuf[0] = 0x13b500;
  6268. }
  6269. static void
  6270. Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6271. {
  6272. slotbuf[0] = 0x61b500;
  6273. }
  6274. static void
  6275. Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6276. {
  6277. slotbuf[0] = 0x3d500;
  6278. }
  6279. static void
  6280. Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6281. {
  6282. slotbuf[0] = 0x13d500;
  6283. }
  6284. static void
  6285. Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6286. {
  6287. slotbuf[0] = 0x61d500;
  6288. }
  6289. static void
  6290. Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6291. {
  6292. slotbuf[0] = 0x3b600;
  6293. }
  6294. static void
  6295. Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6296. {
  6297. slotbuf[0] = 0x13b600;
  6298. }
  6299. static void
  6300. Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6301. {
  6302. slotbuf[0] = 0x61b600;
  6303. }
  6304. static void
  6305. Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6306. {
  6307. slotbuf[0] = 0x3d600;
  6308. }
  6309. static void
  6310. Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6311. {
  6312. slotbuf[0] = 0x13d600;
  6313. }
  6314. static void
  6315. Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6316. {
  6317. slotbuf[0] = 0x61d600;
  6318. }
  6319. static void
  6320. Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6321. {
  6322. slotbuf[0] = 0x3b700;
  6323. }
  6324. static void
  6325. Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6326. {
  6327. slotbuf[0] = 0x13b700;
  6328. }
  6329. static void
  6330. Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6331. {
  6332. slotbuf[0] = 0x61b700;
  6333. }
  6334. static void
  6335. Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6336. {
  6337. slotbuf[0] = 0x3d700;
  6338. }
  6339. static void
  6340. Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6341. {
  6342. slotbuf[0] = 0x13d700;
  6343. }
  6344. static void
  6345. Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6346. {
  6347. slotbuf[0] = 0x61d700;
  6348. }
  6349. static void
  6350. Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6351. {
  6352. slotbuf[0] = 0x3c200;
  6353. }
  6354. static void
  6355. Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6356. {
  6357. slotbuf[0] = 0x13c200;
  6358. }
  6359. static void
  6360. Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6361. {
  6362. slotbuf[0] = 0x61c200;
  6363. }
  6364. static void
  6365. Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6366. {
  6367. slotbuf[0] = 0x3c300;
  6368. }
  6369. static void
  6370. Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6371. {
  6372. slotbuf[0] = 0x13c300;
  6373. }
  6374. static void
  6375. Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6376. {
  6377. slotbuf[0] = 0x61c300;
  6378. }
  6379. static void
  6380. Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6381. {
  6382. slotbuf[0] = 0x3c400;
  6383. }
  6384. static void
  6385. Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6386. {
  6387. slotbuf[0] = 0x13c400;
  6388. }
  6389. static void
  6390. Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6391. {
  6392. slotbuf[0] = 0x61c400;
  6393. }
  6394. static void
  6395. Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6396. {
  6397. slotbuf[0] = 0x3c500;
  6398. }
  6399. static void
  6400. Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6401. {
  6402. slotbuf[0] = 0x13c500;
  6403. }
  6404. static void
  6405. Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6406. {
  6407. slotbuf[0] = 0x61c500;
  6408. }
  6409. static void
  6410. Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6411. {
  6412. slotbuf[0] = 0x3c600;
  6413. }
  6414. static void
  6415. Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6416. {
  6417. slotbuf[0] = 0x13c600;
  6418. }
  6419. static void
  6420. Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6421. {
  6422. slotbuf[0] = 0x61c600;
  6423. }
  6424. static void
  6425. Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6426. {
  6427. slotbuf[0] = 0x3c700;
  6428. }
  6429. static void
  6430. Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6431. {
  6432. slotbuf[0] = 0x13c700;
  6433. }
  6434. static void
  6435. Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6436. {
  6437. slotbuf[0] = 0x61c700;
  6438. }
  6439. static void
  6440. Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6441. {
  6442. slotbuf[0] = 0x3ee00;
  6443. }
  6444. static void
  6445. Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6446. {
  6447. slotbuf[0] = 0x13ee00;
  6448. }
  6449. static void
  6450. Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6451. {
  6452. slotbuf[0] = 0x61ee00;
  6453. }
  6454. static void
  6455. Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6456. {
  6457. slotbuf[0] = 0x3c000;
  6458. }
  6459. static void
  6460. Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6461. {
  6462. slotbuf[0] = 0x13c000;
  6463. }
  6464. static void
  6465. Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6466. {
  6467. slotbuf[0] = 0x61c000;
  6468. }
  6469. static void
  6470. Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6471. {
  6472. slotbuf[0] = 0x3e800;
  6473. }
  6474. static void
  6475. Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6476. {
  6477. slotbuf[0] = 0x13e800;
  6478. }
  6479. static void
  6480. Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6481. {
  6482. slotbuf[0] = 0x61e800;
  6483. }
  6484. static void
  6485. Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6486. {
  6487. slotbuf[0] = 0x3f400;
  6488. }
  6489. static void
  6490. Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6491. {
  6492. slotbuf[0] = 0x13f400;
  6493. }
  6494. static void
  6495. Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6496. {
  6497. slotbuf[0] = 0x61f400;
  6498. }
  6499. static void
  6500. Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6501. {
  6502. slotbuf[0] = 0x3f500;
  6503. }
  6504. static void
  6505. Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6506. {
  6507. slotbuf[0] = 0x13f500;
  6508. }
  6509. static void
  6510. Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6511. {
  6512. slotbuf[0] = 0x61f500;
  6513. }
  6514. static void
  6515. Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6516. {
  6517. slotbuf[0] = 0x3eb00;
  6518. }
  6519. static void
  6520. Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6521. {
  6522. slotbuf[0] = 0x3e700;
  6523. }
  6524. static void
  6525. Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6526. {
  6527. slotbuf[0] = 0x13e700;
  6528. }
  6529. static void
  6530. Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6531. {
  6532. slotbuf[0] = 0x61e700;
  6533. }
  6534. static void
  6535. Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6536. {
  6537. slotbuf[0] = 0x740004;
  6538. }
  6539. static void
  6540. Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6541. {
  6542. slotbuf[0] = 0x750004;
  6543. }
  6544. static void
  6545. Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6546. {
  6547. slotbuf[0] = 0x760004;
  6548. }
  6549. static void
  6550. Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6551. {
  6552. slotbuf[0] = 0x770004;
  6553. }
  6554. static void
  6555. Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6556. {
  6557. slotbuf[0] = 0x700004;
  6558. }
  6559. static void
  6560. Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6561. {
  6562. slotbuf[0] = 0x710004;
  6563. }
  6564. static void
  6565. Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6566. {
  6567. slotbuf[0] = 0x720004;
  6568. }
  6569. static void
  6570. Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6571. {
  6572. slotbuf[0] = 0x730004;
  6573. }
  6574. static void
  6575. Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6576. {
  6577. slotbuf[0] = 0x340004;
  6578. }
  6579. static void
  6580. Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6581. {
  6582. slotbuf[0] = 0x350004;
  6583. }
  6584. static void
  6585. Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6586. {
  6587. slotbuf[0] = 0x360004;
  6588. }
  6589. static void
  6590. Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6591. {
  6592. slotbuf[0] = 0x370004;
  6593. }
  6594. static void
  6595. Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6596. {
  6597. slotbuf[0] = 0x640004;
  6598. }
  6599. static void
  6600. Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6601. {
  6602. slotbuf[0] = 0x650004;
  6603. }
  6604. static void
  6605. Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6606. {
  6607. slotbuf[0] = 0x660004;
  6608. }
  6609. static void
  6610. Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6611. {
  6612. slotbuf[0] = 0x670004;
  6613. }
  6614. static void
  6615. Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6616. {
  6617. slotbuf[0] = 0x240004;
  6618. }
  6619. static void
  6620. Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6621. {
  6622. slotbuf[0] = 0x250004;
  6623. }
  6624. static void
  6625. Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6626. {
  6627. slotbuf[0] = 0x260004;
  6628. }
  6629. static void
  6630. Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6631. {
  6632. slotbuf[0] = 0x270004;
  6633. }
  6634. static void
  6635. Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6636. {
  6637. slotbuf[0] = 0x780004;
  6638. }
  6639. static void
  6640. Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6641. {
  6642. slotbuf[0] = 0x790004;
  6643. }
  6644. static void
  6645. Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6646. {
  6647. slotbuf[0] = 0x7a0004;
  6648. }
  6649. static void
  6650. Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6651. {
  6652. slotbuf[0] = 0x7b0004;
  6653. }
  6654. static void
  6655. Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6656. {
  6657. slotbuf[0] = 0x7c0004;
  6658. }
  6659. static void
  6660. Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6661. {
  6662. slotbuf[0] = 0x7d0004;
  6663. }
  6664. static void
  6665. Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6666. {
  6667. slotbuf[0] = 0x7e0004;
  6668. }
  6669. static void
  6670. Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6671. {
  6672. slotbuf[0] = 0x7f0004;
  6673. }
  6674. static void
  6675. Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6676. {
  6677. slotbuf[0] = 0x380004;
  6678. }
  6679. static void
  6680. Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6681. {
  6682. slotbuf[0] = 0x390004;
  6683. }
  6684. static void
  6685. Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6686. {
  6687. slotbuf[0] = 0x3a0004;
  6688. }
  6689. static void
  6690. Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6691. {
  6692. slotbuf[0] = 0x3b0004;
  6693. }
  6694. static void
  6695. Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6696. {
  6697. slotbuf[0] = 0x3c0004;
  6698. }
  6699. static void
  6700. Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6701. {
  6702. slotbuf[0] = 0x3d0004;
  6703. }
  6704. static void
  6705. Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6706. {
  6707. slotbuf[0] = 0x3e0004;
  6708. }
  6709. static void
  6710. Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6711. {
  6712. slotbuf[0] = 0x3f0004;
  6713. }
  6714. static void
  6715. Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6716. {
  6717. slotbuf[0] = 0x680004;
  6718. }
  6719. static void
  6720. Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6721. {
  6722. slotbuf[0] = 0x690004;
  6723. }
  6724. static void
  6725. Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6726. {
  6727. slotbuf[0] = 0x6a0004;
  6728. }
  6729. static void
  6730. Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6731. {
  6732. slotbuf[0] = 0x6b0004;
  6733. }
  6734. static void
  6735. Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6736. {
  6737. slotbuf[0] = 0x6c0004;
  6738. }
  6739. static void
  6740. Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6741. {
  6742. slotbuf[0] = 0x6d0004;
  6743. }
  6744. static void
  6745. Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6746. {
  6747. slotbuf[0] = 0x6e0004;
  6748. }
  6749. static void
  6750. Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6751. {
  6752. slotbuf[0] = 0x6f0004;
  6753. }
  6754. static void
  6755. Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6756. {
  6757. slotbuf[0] = 0x280004;
  6758. }
  6759. static void
  6760. Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6761. {
  6762. slotbuf[0] = 0x290004;
  6763. }
  6764. static void
  6765. Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6766. {
  6767. slotbuf[0] = 0x2a0004;
  6768. }
  6769. static void
  6770. Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6771. {
  6772. slotbuf[0] = 0x2b0004;
  6773. }
  6774. static void
  6775. Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6776. {
  6777. slotbuf[0] = 0x2c0004;
  6778. }
  6779. static void
  6780. Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6781. {
  6782. slotbuf[0] = 0x2d0004;
  6783. }
  6784. static void
  6785. Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6786. {
  6787. slotbuf[0] = 0x2e0004;
  6788. }
  6789. static void
  6790. Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6791. {
  6792. slotbuf[0] = 0x2f0004;
  6793. }
  6794. static void
  6795. Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6796. {
  6797. slotbuf[0] = 0x580004;
  6798. }
  6799. static void
  6800. Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6801. {
  6802. slotbuf[0] = 0x480004;
  6803. }
  6804. static void
  6805. Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6806. {
  6807. slotbuf[0] = 0x590004;
  6808. }
  6809. static void
  6810. Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6811. {
  6812. slotbuf[0] = 0x490004;
  6813. }
  6814. static void
  6815. Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6816. {
  6817. slotbuf[0] = 0x5a0004;
  6818. }
  6819. static void
  6820. Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6821. {
  6822. slotbuf[0] = 0x4a0004;
  6823. }
  6824. static void
  6825. Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6826. {
  6827. slotbuf[0] = 0x5b0004;
  6828. }
  6829. static void
  6830. Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6831. {
  6832. slotbuf[0] = 0x4b0004;
  6833. }
  6834. static void
  6835. Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6836. {
  6837. slotbuf[0] = 0x180004;
  6838. }
  6839. static void
  6840. Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6841. {
  6842. slotbuf[0] = 0x80004;
  6843. }
  6844. static void
  6845. Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6846. {
  6847. slotbuf[0] = 0x190004;
  6848. }
  6849. static void
  6850. Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6851. {
  6852. slotbuf[0] = 0x90004;
  6853. }
  6854. static void
  6855. Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6856. {
  6857. slotbuf[0] = 0x1a0004;
  6858. }
  6859. static void
  6860. Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6861. {
  6862. slotbuf[0] = 0xa0004;
  6863. }
  6864. static void
  6865. Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6866. {
  6867. slotbuf[0] = 0x1b0004;
  6868. }
  6869. static void
  6870. Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6871. {
  6872. slotbuf[0] = 0xb0004;
  6873. }
  6874. static void
  6875. Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6876. {
  6877. slotbuf[0] = 0x900004;
  6878. }
  6879. static void
  6880. Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6881. {
  6882. slotbuf[0] = 0x800004;
  6883. }
  6884. static void
  6885. Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6886. {
  6887. slotbuf[0] = 0xc10000;
  6888. }
  6889. static void
  6890. Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6891. {
  6892. slotbuf[0] = 0xd10000;
  6893. }
  6894. static void
  6895. Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6896. {
  6897. slotbuf[0] = 0x32000;
  6898. }
  6899. static void
  6900. Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6901. {
  6902. slotbuf[0] = 0x132000;
  6903. }
  6904. static void
  6905. Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6906. {
  6907. slotbuf[0] = 0x612000;
  6908. }
  6909. static void
  6910. Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6911. {
  6912. slotbuf[0] = 0x32100;
  6913. }
  6914. static void
  6915. Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6916. {
  6917. slotbuf[0] = 0x132100;
  6918. }
  6919. static void
  6920. Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6921. {
  6922. slotbuf[0] = 0x612100;
  6923. }
  6924. static void
  6925. Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6926. {
  6927. slotbuf[0] = 0x32200;
  6928. }
  6929. static void
  6930. Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6931. {
  6932. slotbuf[0] = 0x132200;
  6933. }
  6934. static void
  6935. Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6936. {
  6937. slotbuf[0] = 0x612200;
  6938. }
  6939. static void
  6940. Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6941. {
  6942. slotbuf[0] = 0x32300;
  6943. }
  6944. static void
  6945. Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6946. {
  6947. slotbuf[0] = 0x132300;
  6948. }
  6949. static void
  6950. Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6951. {
  6952. slotbuf[0] = 0x612300;
  6953. }
  6954. static void
  6955. Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6956. {
  6957. slotbuf[0] = 0x31000;
  6958. }
  6959. static void
  6960. Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6961. {
  6962. slotbuf[0] = 0x131000;
  6963. }
  6964. static void
  6965. Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6966. {
  6967. slotbuf[0] = 0x611000;
  6968. }
  6969. static void
  6970. Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6971. {
  6972. slotbuf[0] = 0x31100;
  6973. }
  6974. static void
  6975. Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6976. {
  6977. slotbuf[0] = 0x131100;
  6978. }
  6979. static void
  6980. Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6981. {
  6982. slotbuf[0] = 0x611100;
  6983. }
  6984. static void
  6985. Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6986. {
  6987. slotbuf[0] = 0x3010;
  6988. }
  6989. static void
  6990. Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6991. {
  6992. slotbuf[0] = 0x7000;
  6993. }
  6994. static void
  6995. Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
  6996. {
  6997. slotbuf[0] = 0x3e200;
  6998. }
  6999. static void
  7000. Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7001. {
  7002. slotbuf[0] = 0x13e200;
  7003. }
  7004. static void
  7005. Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7006. {
  7007. slotbuf[0] = 0x13e300;
  7008. }
  7009. static void
  7010. Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7011. {
  7012. slotbuf[0] = 0x3e400;
  7013. }
  7014. static void
  7015. Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7016. {
  7017. slotbuf[0] = 0x13e400;
  7018. }
  7019. static void
  7020. Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7021. {
  7022. slotbuf[0] = 0x61e400;
  7023. }
  7024. static void
  7025. Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7026. {
  7027. slotbuf[0] = 0x4000;
  7028. }
  7029. static void
  7030. Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  7031. {
  7032. slotbuf[0] = 0xf02d;
  7033. }
  7034. static void
  7035. Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7036. {
  7037. slotbuf[0] = 0x39000;
  7038. }
  7039. static void
  7040. Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7041. {
  7042. slotbuf[0] = 0x139000;
  7043. }
  7044. static void
  7045. Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7046. {
  7047. slotbuf[0] = 0x619000;
  7048. }
  7049. static void
  7050. Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7051. {
  7052. slotbuf[0] = 0x3a000;
  7053. }
  7054. static void
  7055. Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7056. {
  7057. slotbuf[0] = 0x13a000;
  7058. }
  7059. static void
  7060. Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7061. {
  7062. slotbuf[0] = 0x61a000;
  7063. }
  7064. static void
  7065. Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7066. {
  7067. slotbuf[0] = 0x39100;
  7068. }
  7069. static void
  7070. Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7071. {
  7072. slotbuf[0] = 0x139100;
  7073. }
  7074. static void
  7075. Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7076. {
  7077. slotbuf[0] = 0x619100;
  7078. }
  7079. static void
  7080. Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7081. {
  7082. slotbuf[0] = 0x3a100;
  7083. }
  7084. static void
  7085. Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7086. {
  7087. slotbuf[0] = 0x13a100;
  7088. }
  7089. static void
  7090. Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7091. {
  7092. slotbuf[0] = 0x61a100;
  7093. }
  7094. static void
  7095. Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7096. {
  7097. slotbuf[0] = 0x38000;
  7098. }
  7099. static void
  7100. Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7101. {
  7102. slotbuf[0] = 0x138000;
  7103. }
  7104. static void
  7105. Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7106. {
  7107. slotbuf[0] = 0x618000;
  7108. }
  7109. static void
  7110. Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7111. {
  7112. slotbuf[0] = 0x38100;
  7113. }
  7114. static void
  7115. Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7116. {
  7117. slotbuf[0] = 0x138100;
  7118. }
  7119. static void
  7120. Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7121. {
  7122. slotbuf[0] = 0x618100;
  7123. }
  7124. static void
  7125. Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7126. {
  7127. slotbuf[0] = 0x36000;
  7128. }
  7129. static void
  7130. Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7131. {
  7132. slotbuf[0] = 0x136000;
  7133. }
  7134. static void
  7135. Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7136. {
  7137. slotbuf[0] = 0x616000;
  7138. }
  7139. static void
  7140. Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7141. {
  7142. slotbuf[0] = 0x3e900;
  7143. }
  7144. static void
  7145. Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7146. {
  7147. slotbuf[0] = 0x13e900;
  7148. }
  7149. static void
  7150. Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7151. {
  7152. slotbuf[0] = 0x61e900;
  7153. }
  7154. static void
  7155. Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7156. {
  7157. slotbuf[0] = 0x3ec00;
  7158. }
  7159. static void
  7160. Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7161. {
  7162. slotbuf[0] = 0x13ec00;
  7163. }
  7164. static void
  7165. Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7166. {
  7167. slotbuf[0] = 0x61ec00;
  7168. }
  7169. static void
  7170. Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7171. {
  7172. slotbuf[0] = 0x3ed00;
  7173. }
  7174. static void
  7175. Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7176. {
  7177. slotbuf[0] = 0x13ed00;
  7178. }
  7179. static void
  7180. Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7181. {
  7182. slotbuf[0] = 0x61ed00;
  7183. }
  7184. static void
  7185. Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7186. {
  7187. slotbuf[0] = 0x36800;
  7188. }
  7189. static void
  7190. Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7191. {
  7192. slotbuf[0] = 0x136800;
  7193. }
  7194. static void
  7195. Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7196. {
  7197. slotbuf[0] = 0x616800;
  7198. }
  7199. static void
  7200. Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7201. {
  7202. slotbuf[0] = 0xf1e000;
  7203. }
  7204. static void
  7205. Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7206. {
  7207. slotbuf[0] = 0xf1e010;
  7208. }
  7209. static void
  7210. Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7211. {
  7212. slotbuf[0] = 0x135900;
  7213. }
  7214. static void
  7215. Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7216. {
  7217. slotbuf[0] = 0x3ea00;
  7218. }
  7219. static void
  7220. Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7221. {
  7222. slotbuf[0] = 0x13ea00;
  7223. }
  7224. static void
  7225. Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7226. {
  7227. slotbuf[0] = 0x61ea00;
  7228. }
  7229. static void
  7230. Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7231. {
  7232. slotbuf[0] = 0x3f000;
  7233. }
  7234. static void
  7235. Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7236. {
  7237. slotbuf[0] = 0x13f000;
  7238. }
  7239. static void
  7240. Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7241. {
  7242. slotbuf[0] = 0x61f000;
  7243. }
  7244. static void
  7245. Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7246. {
  7247. slotbuf[0] = 0x3f100;
  7248. }
  7249. static void
  7250. Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7251. {
  7252. slotbuf[0] = 0x13f100;
  7253. }
  7254. static void
  7255. Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7256. {
  7257. slotbuf[0] = 0x61f100;
  7258. }
  7259. static void
  7260. Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7261. {
  7262. slotbuf[0] = 0x3f200;
  7263. }
  7264. static void
  7265. Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7266. {
  7267. slotbuf[0] = 0x13f200;
  7268. }
  7269. static void
  7270. Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7271. {
  7272. slotbuf[0] = 0x61f200;
  7273. }
  7274. static void
  7275. Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7276. {
  7277. slotbuf[0] = 0x70c2;
  7278. }
  7279. static void
  7280. Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7281. {
  7282. slotbuf[0] = 0x70e2;
  7283. }
  7284. static void
  7285. Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7286. {
  7287. slotbuf[0] = 0x70d2;
  7288. }
  7289. static void
  7290. Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7291. {
  7292. slotbuf[0] = 0x270d2;
  7293. }
  7294. static void
  7295. Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7296. {
  7297. slotbuf[0] = 0x370d2;
  7298. }
  7299. static void
  7300. Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7301. {
  7302. slotbuf[0] = 0x70f2;
  7303. }
  7304. static void
  7305. Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7306. {
  7307. slotbuf[0] = 0xf10000;
  7308. }
  7309. static void
  7310. Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7311. {
  7312. slotbuf[0] = 0xf12000;
  7313. }
  7314. static void
  7315. Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7316. {
  7317. slotbuf[0] = 0xf11000;
  7318. }
  7319. static void
  7320. Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7321. {
  7322. slotbuf[0] = 0xf13000;
  7323. }
  7324. static void
  7325. Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7326. {
  7327. slotbuf[0] = 0x7042;
  7328. }
  7329. static void
  7330. Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7331. {
  7332. slotbuf[0] = 0x7052;
  7333. }
  7334. static void
  7335. Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7336. {
  7337. slotbuf[0] = 0x47082;
  7338. }
  7339. static void
  7340. Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7341. {
  7342. slotbuf[0] = 0x57082;
  7343. }
  7344. static void
  7345. Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7346. {
  7347. slotbuf[0] = 0x7062;
  7348. }
  7349. static void
  7350. Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7351. {
  7352. slotbuf[0] = 0x7072;
  7353. }
  7354. static void
  7355. Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7356. {
  7357. slotbuf[0] = 0x7002;
  7358. }
  7359. static void
  7360. Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7361. {
  7362. slotbuf[0] = 0x7012;
  7363. }
  7364. static void
  7365. Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7366. {
  7367. slotbuf[0] = 0x7022;
  7368. }
  7369. static void
  7370. Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7371. {
  7372. slotbuf[0] = 0x7032;
  7373. }
  7374. static void
  7375. Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7376. {
  7377. slotbuf[0] = 0x7082;
  7378. }
  7379. static void
  7380. Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7381. {
  7382. slotbuf[0] = 0x27082;
  7383. }
  7384. static void
  7385. Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7386. {
  7387. slotbuf[0] = 0x37082;
  7388. }
  7389. static void
  7390. Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7391. {
  7392. slotbuf[0] = 0xf19000;
  7393. }
  7394. static void
  7395. Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7396. {
  7397. slotbuf[0] = 0xf18000;
  7398. }
  7399. static void
  7400. Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7401. {
  7402. slotbuf[0] = 0x135300;
  7403. }
  7404. static void
  7405. Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7406. {
  7407. slotbuf[0] = 0x35300;
  7408. }
  7409. static void
  7410. Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7411. {
  7412. slotbuf[0] = 0x615300;
  7413. }
  7414. static void
  7415. Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7416. {
  7417. slotbuf[0] = 0x35a00;
  7418. }
  7419. static void
  7420. Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7421. {
  7422. slotbuf[0] = 0x135a00;
  7423. }
  7424. static void
  7425. Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7426. {
  7427. slotbuf[0] = 0x615a00;
  7428. }
  7429. static void
  7430. Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7431. {
  7432. slotbuf[0] = 0x35b00;
  7433. }
  7434. static void
  7435. Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7436. {
  7437. slotbuf[0] = 0x135b00;
  7438. }
  7439. static void
  7440. Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7441. {
  7442. slotbuf[0] = 0x615b00;
  7443. }
  7444. static void
  7445. Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7446. {
  7447. slotbuf[0] = 0x35c00;
  7448. }
  7449. static void
  7450. Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7451. {
  7452. slotbuf[0] = 0x135c00;
  7453. }
  7454. static void
  7455. Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7456. {
  7457. slotbuf[0] = 0x615c00;
  7458. }
  7459. static void
  7460. Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7461. {
  7462. slotbuf[0] = 0x50c000;
  7463. }
  7464. static void
  7465. Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7466. {
  7467. slotbuf[0] = 0x50d000;
  7468. }
  7469. static void
  7470. Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7471. {
  7472. slotbuf[0] = 0x50b000;
  7473. }
  7474. static void
  7475. Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7476. {
  7477. slotbuf[0] = 0x50f000;
  7478. }
  7479. static void
  7480. Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7481. {
  7482. slotbuf[0] = 0x50e000;
  7483. }
  7484. static void
  7485. Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7486. {
  7487. slotbuf[0] = 0x504000;
  7488. }
  7489. static void
  7490. Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7491. {
  7492. slotbuf[0] = 0x505000;
  7493. }
  7494. static void
  7495. Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7496. {
  7497. slotbuf[0] = 0x503000;
  7498. }
  7499. static void
  7500. Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7501. {
  7502. slotbuf[0] = 0x507000;
  7503. }
  7504. static void
  7505. Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7506. {
  7507. slotbuf[0] = 0x506000;
  7508. }
  7509. static void
  7510. Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7511. {
  7512. slotbuf[0] = 0xf1f000;
  7513. }
  7514. static void
  7515. Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7516. {
  7517. slotbuf[0] = 0x501000;
  7518. }
  7519. static void
  7520. Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7521. {
  7522. slotbuf[0] = 0x509000;
  7523. }
  7524. static void
  7525. Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7526. {
  7527. slotbuf[0] = 0x3e000;
  7528. }
  7529. static void
  7530. Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7531. {
  7532. slotbuf[0] = 0x13e000;
  7533. }
  7534. static void
  7535. Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7536. {
  7537. slotbuf[0] = 0x61e000;
  7538. }
  7539. static void
  7540. Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7541. {
  7542. slotbuf[0] = 0x330000;
  7543. }
  7544. static void
  7545. Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7546. {
  7547. slotbuf[0] = 0x430000;
  7548. }
  7549. static void
  7550. Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7551. {
  7552. slotbuf[0] = 0x530000;
  7553. }
  7554. static void
  7555. Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7556. {
  7557. slotbuf[0] = 0x630000;
  7558. }
  7559. static void
  7560. Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7561. {
  7562. slotbuf[0] = 0x730000;
  7563. }
  7564. static void
  7565. Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7566. {
  7567. slotbuf[0] = 0x40e000;
  7568. }
  7569. static void
  7570. Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7571. {
  7572. slotbuf[0] = 0x40f000;
  7573. }
  7574. static void
  7575. Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7576. {
  7577. slotbuf[0] = 0x230000;
  7578. }
  7579. static void
  7580. Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7581. {
  7582. slotbuf[0] = 0xb002;
  7583. }
  7584. static void
  7585. Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7586. {
  7587. slotbuf[0] = 0xf002;
  7588. }
  7589. static void
  7590. Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7591. {
  7592. slotbuf[0] = 0xe002;
  7593. }
  7594. static void
  7595. Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7596. {
  7597. slotbuf[0] = 0x30c00;
  7598. }
  7599. static void
  7600. Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7601. {
  7602. slotbuf[0] = 0x130c00;
  7603. }
  7604. static void
  7605. Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7606. {
  7607. slotbuf[0] = 0x610c00;
  7608. }
  7609. static void
  7610. Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7611. {
  7612. slotbuf[0] = 0xc20000;
  7613. }
  7614. static void
  7615. Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7616. {
  7617. slotbuf[0] = 0xd20000;
  7618. }
  7619. static void
  7620. Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7621. {
  7622. slotbuf[0] = 0xe20000;
  7623. }
  7624. static void
  7625. Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7626. {
  7627. slotbuf[0] = 0xf20000;
  7628. }
  7629. static void
  7630. Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7631. {
  7632. slotbuf[0] = 0x820000;
  7633. }
  7634. static void
  7635. Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7636. {
  7637. slotbuf[0] = 0xe30e60;
  7638. }
  7639. static void
  7640. Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7641. {
  7642. slotbuf[0] = 0xf3e600;
  7643. }
  7644. static void
  7645. Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7646. {
  7647. slotbuf[0] = 0xe0000;
  7648. }
  7649. static void
  7650. Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7651. {
  7652. slotbuf[0] = 0xe1000;
  7653. }
  7654. static void
  7655. Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7656. {
  7657. slotbuf[0] = 0xe1200;
  7658. }
  7659. static void
  7660. Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  7661. {
  7662. slotbuf[0] = 0xe2000;
  7663. }
  7664. static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
  7665. Opcode_excw_Slot_inst_encode, 0, 0
  7666. };
  7667. static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
  7668. Opcode_rfe_Slot_inst_encode, 0, 0
  7669. };
  7670. static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
  7671. Opcode_rfde_Slot_inst_encode, 0, 0
  7672. };
  7673. static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
  7674. Opcode_syscall_Slot_inst_encode, 0, 0
  7675. };
  7676. static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
  7677. Opcode_simcall_Slot_inst_encode, 0, 0
  7678. };
  7679. static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
  7680. Opcode_call12_Slot_inst_encode, 0, 0
  7681. };
  7682. static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
  7683. Opcode_call8_Slot_inst_encode, 0, 0
  7684. };
  7685. static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
  7686. Opcode_call4_Slot_inst_encode, 0, 0
  7687. };
  7688. static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
  7689. Opcode_callx12_Slot_inst_encode, 0, 0
  7690. };
  7691. static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
  7692. Opcode_callx8_Slot_inst_encode, 0, 0
  7693. };
  7694. static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
  7695. Opcode_callx4_Slot_inst_encode, 0, 0
  7696. };
  7697. static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
  7698. Opcode_entry_Slot_inst_encode, 0, 0
  7699. };
  7700. static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
  7701. Opcode_movsp_Slot_inst_encode, 0, 0
  7702. };
  7703. static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
  7704. Opcode_rotw_Slot_inst_encode, 0, 0
  7705. };
  7706. static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
  7707. Opcode_retw_Slot_inst_encode, 0, 0
  7708. };
  7709. static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
  7710. 0, 0, Opcode_retw_n_Slot_inst16b_encode
  7711. };
  7712. static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
  7713. Opcode_rfwo_Slot_inst_encode, 0, 0
  7714. };
  7715. static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
  7716. Opcode_rfwu_Slot_inst_encode, 0, 0
  7717. };
  7718. static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
  7719. Opcode_l32e_Slot_inst_encode, 0, 0
  7720. };
  7721. static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
  7722. Opcode_s32e_Slot_inst_encode, 0, 0
  7723. };
  7724. static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
  7725. Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
  7726. };
  7727. static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
  7728. Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
  7729. };
  7730. static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
  7731. Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
  7732. };
  7733. static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
  7734. Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
  7735. };
  7736. static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
  7737. Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
  7738. };
  7739. static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
  7740. Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
  7741. };
  7742. static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
  7743. 0, Opcode_add_n_Slot_inst16a_encode, 0
  7744. };
  7745. static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
  7746. 0, Opcode_addi_n_Slot_inst16a_encode, 0
  7747. };
  7748. static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
  7749. 0, 0, Opcode_beqz_n_Slot_inst16b_encode
  7750. };
  7751. static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
  7752. 0, 0, Opcode_bnez_n_Slot_inst16b_encode
  7753. };
  7754. static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
  7755. 0, 0, Opcode_ill_n_Slot_inst16b_encode
  7756. };
  7757. static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
  7758. 0, Opcode_l32i_n_Slot_inst16a_encode, 0
  7759. };
  7760. static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
  7761. 0, 0, Opcode_mov_n_Slot_inst16b_encode
  7762. };
  7763. static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
  7764. 0, 0, Opcode_movi_n_Slot_inst16b_encode
  7765. };
  7766. static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
  7767. 0, 0, Opcode_nop_n_Slot_inst16b_encode
  7768. };
  7769. static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
  7770. 0, 0, Opcode_ret_n_Slot_inst16b_encode
  7771. };
  7772. static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
  7773. 0, Opcode_s32i_n_Slot_inst16a_encode, 0
  7774. };
  7775. static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
  7776. Opcode_rur_threadptr_Slot_inst_encode, 0, 0
  7777. };
  7778. static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
  7779. Opcode_wur_threadptr_Slot_inst_encode, 0, 0
  7780. };
  7781. static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
  7782. Opcode_addi_Slot_inst_encode, 0, 0
  7783. };
  7784. static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
  7785. Opcode_addmi_Slot_inst_encode, 0, 0
  7786. };
  7787. static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
  7788. Opcode_add_Slot_inst_encode, 0, 0
  7789. };
  7790. static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
  7791. Opcode_sub_Slot_inst_encode, 0, 0
  7792. };
  7793. static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
  7794. Opcode_addx2_Slot_inst_encode, 0, 0
  7795. };
  7796. static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
  7797. Opcode_addx4_Slot_inst_encode, 0, 0
  7798. };
  7799. static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
  7800. Opcode_addx8_Slot_inst_encode, 0, 0
  7801. };
  7802. static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
  7803. Opcode_subx2_Slot_inst_encode, 0, 0
  7804. };
  7805. static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
  7806. Opcode_subx4_Slot_inst_encode, 0, 0
  7807. };
  7808. static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
  7809. Opcode_subx8_Slot_inst_encode, 0, 0
  7810. };
  7811. static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
  7812. Opcode_and_Slot_inst_encode, 0, 0
  7813. };
  7814. static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
  7815. Opcode_or_Slot_inst_encode, 0, 0
  7816. };
  7817. static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
  7818. Opcode_xor_Slot_inst_encode, 0, 0
  7819. };
  7820. static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
  7821. Opcode_beqi_Slot_inst_encode, 0, 0
  7822. };
  7823. static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
  7824. Opcode_bnei_Slot_inst_encode, 0, 0
  7825. };
  7826. static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
  7827. Opcode_bgei_Slot_inst_encode, 0, 0
  7828. };
  7829. static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
  7830. Opcode_blti_Slot_inst_encode, 0, 0
  7831. };
  7832. static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
  7833. Opcode_bbci_Slot_inst_encode, 0, 0
  7834. };
  7835. static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
  7836. Opcode_bbsi_Slot_inst_encode, 0, 0
  7837. };
  7838. static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
  7839. Opcode_bgeui_Slot_inst_encode, 0, 0
  7840. };
  7841. static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
  7842. Opcode_bltui_Slot_inst_encode, 0, 0
  7843. };
  7844. static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
  7845. Opcode_beq_Slot_inst_encode, 0, 0
  7846. };
  7847. static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
  7848. Opcode_bne_Slot_inst_encode, 0, 0
  7849. };
  7850. static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
  7851. Opcode_bge_Slot_inst_encode, 0, 0
  7852. };
  7853. static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
  7854. Opcode_blt_Slot_inst_encode, 0, 0
  7855. };
  7856. static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
  7857. Opcode_bgeu_Slot_inst_encode, 0, 0
  7858. };
  7859. static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
  7860. Opcode_bltu_Slot_inst_encode, 0, 0
  7861. };
  7862. static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
  7863. Opcode_bany_Slot_inst_encode, 0, 0
  7864. };
  7865. static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
  7866. Opcode_bnone_Slot_inst_encode, 0, 0
  7867. };
  7868. static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
  7869. Opcode_ball_Slot_inst_encode, 0, 0
  7870. };
  7871. static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
  7872. Opcode_bnall_Slot_inst_encode, 0, 0
  7873. };
  7874. static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
  7875. Opcode_bbc_Slot_inst_encode, 0, 0
  7876. };
  7877. static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
  7878. Opcode_bbs_Slot_inst_encode, 0, 0
  7879. };
  7880. static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
  7881. Opcode_beqz_Slot_inst_encode, 0, 0
  7882. };
  7883. static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
  7884. Opcode_bnez_Slot_inst_encode, 0, 0
  7885. };
  7886. static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
  7887. Opcode_bgez_Slot_inst_encode, 0, 0
  7888. };
  7889. static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
  7890. Opcode_bltz_Slot_inst_encode, 0, 0
  7891. };
  7892. static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
  7893. Opcode_call0_Slot_inst_encode, 0, 0
  7894. };
  7895. static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
  7896. Opcode_callx0_Slot_inst_encode, 0, 0
  7897. };
  7898. static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
  7899. Opcode_extui_Slot_inst_encode, 0, 0
  7900. };
  7901. static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
  7902. Opcode_ill_Slot_inst_encode, 0, 0
  7903. };
  7904. static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
  7905. Opcode_j_Slot_inst_encode, 0, 0
  7906. };
  7907. static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
  7908. Opcode_jx_Slot_inst_encode, 0, 0
  7909. };
  7910. static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
  7911. Opcode_l16ui_Slot_inst_encode, 0, 0
  7912. };
  7913. static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
  7914. Opcode_l16si_Slot_inst_encode, 0, 0
  7915. };
  7916. static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
  7917. Opcode_l32i_Slot_inst_encode, 0, 0
  7918. };
  7919. static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
  7920. Opcode_l32r_Slot_inst_encode, 0, 0
  7921. };
  7922. static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
  7923. Opcode_l8ui_Slot_inst_encode, 0, 0
  7924. };
  7925. static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
  7926. Opcode_loop_Slot_inst_encode, 0, 0
  7927. };
  7928. static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
  7929. Opcode_loopnez_Slot_inst_encode, 0, 0
  7930. };
  7931. static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
  7932. Opcode_loopgtz_Slot_inst_encode, 0, 0
  7933. };
  7934. static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
  7935. Opcode_movi_Slot_inst_encode, 0, 0
  7936. };
  7937. static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
  7938. Opcode_moveqz_Slot_inst_encode, 0, 0
  7939. };
  7940. static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
  7941. Opcode_movnez_Slot_inst_encode, 0, 0
  7942. };
  7943. static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
  7944. Opcode_movltz_Slot_inst_encode, 0, 0
  7945. };
  7946. static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
  7947. Opcode_movgez_Slot_inst_encode, 0, 0
  7948. };
  7949. static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
  7950. Opcode_neg_Slot_inst_encode, 0, 0
  7951. };
  7952. static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
  7953. Opcode_abs_Slot_inst_encode, 0, 0
  7954. };
  7955. static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
  7956. Opcode_nop_Slot_inst_encode, 0, 0
  7957. };
  7958. static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
  7959. Opcode_ret_Slot_inst_encode, 0, 0
  7960. };
  7961. static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
  7962. Opcode_s16i_Slot_inst_encode, 0, 0
  7963. };
  7964. static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
  7965. Opcode_s32i_Slot_inst_encode, 0, 0
  7966. };
  7967. static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
  7968. Opcode_s8i_Slot_inst_encode, 0, 0
  7969. };
  7970. static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
  7971. Opcode_ssr_Slot_inst_encode, 0, 0
  7972. };
  7973. static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
  7974. Opcode_ssl_Slot_inst_encode, 0, 0
  7975. };
  7976. static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
  7977. Opcode_ssa8l_Slot_inst_encode, 0, 0
  7978. };
  7979. static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
  7980. Opcode_ssa8b_Slot_inst_encode, 0, 0
  7981. };
  7982. static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
  7983. Opcode_ssai_Slot_inst_encode, 0, 0
  7984. };
  7985. static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
  7986. Opcode_sll_Slot_inst_encode, 0, 0
  7987. };
  7988. static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
  7989. Opcode_src_Slot_inst_encode, 0, 0
  7990. };
  7991. static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
  7992. Opcode_srl_Slot_inst_encode, 0, 0
  7993. };
  7994. static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
  7995. Opcode_sra_Slot_inst_encode, 0, 0
  7996. };
  7997. static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
  7998. Opcode_slli_Slot_inst_encode, 0, 0
  7999. };
  8000. static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
  8001. Opcode_srai_Slot_inst_encode, 0, 0
  8002. };
  8003. static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
  8004. Opcode_srli_Slot_inst_encode, 0, 0
  8005. };
  8006. static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
  8007. Opcode_memw_Slot_inst_encode, 0, 0
  8008. };
  8009. static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
  8010. Opcode_extw_Slot_inst_encode, 0, 0
  8011. };
  8012. static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
  8013. Opcode_isync_Slot_inst_encode, 0, 0
  8014. };
  8015. static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
  8016. Opcode_rsync_Slot_inst_encode, 0, 0
  8017. };
  8018. static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
  8019. Opcode_esync_Slot_inst_encode, 0, 0
  8020. };
  8021. static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
  8022. Opcode_dsync_Slot_inst_encode, 0, 0
  8023. };
  8024. static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
  8025. Opcode_rsil_Slot_inst_encode, 0, 0
  8026. };
  8027. static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
  8028. Opcode_rsr_lend_Slot_inst_encode, 0, 0
  8029. };
  8030. static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
  8031. Opcode_wsr_lend_Slot_inst_encode, 0, 0
  8032. };
  8033. static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
  8034. Opcode_xsr_lend_Slot_inst_encode, 0, 0
  8035. };
  8036. static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
  8037. Opcode_rsr_lcount_Slot_inst_encode, 0, 0
  8038. };
  8039. static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
  8040. Opcode_wsr_lcount_Slot_inst_encode, 0, 0
  8041. };
  8042. static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
  8043. Opcode_xsr_lcount_Slot_inst_encode, 0, 0
  8044. };
  8045. static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
  8046. Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
  8047. };
  8048. static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
  8049. Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
  8050. };
  8051. static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
  8052. Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
  8053. };
  8054. static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
  8055. Opcode_rsr_sar_Slot_inst_encode, 0, 0
  8056. };
  8057. static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
  8058. Opcode_wsr_sar_Slot_inst_encode, 0, 0
  8059. };
  8060. static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
  8061. Opcode_xsr_sar_Slot_inst_encode, 0, 0
  8062. };
  8063. static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
  8064. Opcode_rsr_litbase_Slot_inst_encode, 0, 0
  8065. };
  8066. static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
  8067. Opcode_wsr_litbase_Slot_inst_encode, 0, 0
  8068. };
  8069. static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
  8070. Opcode_xsr_litbase_Slot_inst_encode, 0, 0
  8071. };
  8072. static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
  8073. Opcode_rsr_176_Slot_inst_encode, 0, 0
  8074. };
  8075. static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
  8076. Opcode_rsr_208_Slot_inst_encode, 0, 0
  8077. };
  8078. static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
  8079. Opcode_rsr_ps_Slot_inst_encode, 0, 0
  8080. };
  8081. static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
  8082. Opcode_wsr_ps_Slot_inst_encode, 0, 0
  8083. };
  8084. static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
  8085. Opcode_xsr_ps_Slot_inst_encode, 0, 0
  8086. };
  8087. static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
  8088. Opcode_rsr_epc1_Slot_inst_encode, 0, 0
  8089. };
  8090. static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
  8091. Opcode_wsr_epc1_Slot_inst_encode, 0, 0
  8092. };
  8093. static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
  8094. Opcode_xsr_epc1_Slot_inst_encode, 0, 0
  8095. };
  8096. static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
  8097. Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
  8098. };
  8099. static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
  8100. Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
  8101. };
  8102. static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
  8103. Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
  8104. };
  8105. static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
  8106. Opcode_rsr_epc2_Slot_inst_encode, 0, 0
  8107. };
  8108. static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
  8109. Opcode_wsr_epc2_Slot_inst_encode, 0, 0
  8110. };
  8111. static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
  8112. Opcode_xsr_epc2_Slot_inst_encode, 0, 0
  8113. };
  8114. static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
  8115. Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
  8116. };
  8117. static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
  8118. Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
  8119. };
  8120. static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
  8121. Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
  8122. };
  8123. static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
  8124. Opcode_rsr_epc3_Slot_inst_encode, 0, 0
  8125. };
  8126. static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
  8127. Opcode_wsr_epc3_Slot_inst_encode, 0, 0
  8128. };
  8129. static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
  8130. Opcode_xsr_epc3_Slot_inst_encode, 0, 0
  8131. };
  8132. static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
  8133. Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
  8134. };
  8135. static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
  8136. Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
  8137. };
  8138. static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
  8139. Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
  8140. };
  8141. static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
  8142. Opcode_rsr_epc4_Slot_inst_encode, 0, 0
  8143. };
  8144. static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
  8145. Opcode_wsr_epc4_Slot_inst_encode, 0, 0
  8146. };
  8147. static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
  8148. Opcode_xsr_epc4_Slot_inst_encode, 0, 0
  8149. };
  8150. static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
  8151. Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
  8152. };
  8153. static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
  8154. Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
  8155. };
  8156. static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
  8157. Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
  8158. };
  8159. static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
  8160. Opcode_rsr_epc5_Slot_inst_encode, 0, 0
  8161. };
  8162. static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
  8163. Opcode_wsr_epc5_Slot_inst_encode, 0, 0
  8164. };
  8165. static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
  8166. Opcode_xsr_epc5_Slot_inst_encode, 0, 0
  8167. };
  8168. static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
  8169. Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
  8170. };
  8171. static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
  8172. Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
  8173. };
  8174. static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
  8175. Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
  8176. };
  8177. static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
  8178. Opcode_rsr_epc6_Slot_inst_encode, 0, 0
  8179. };
  8180. static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
  8181. Opcode_wsr_epc6_Slot_inst_encode, 0, 0
  8182. };
  8183. static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
  8184. Opcode_xsr_epc6_Slot_inst_encode, 0, 0
  8185. };
  8186. static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
  8187. Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
  8188. };
  8189. static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
  8190. Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
  8191. };
  8192. static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
  8193. Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
  8194. };
  8195. static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
  8196. Opcode_rsr_epc7_Slot_inst_encode, 0, 0
  8197. };
  8198. static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
  8199. Opcode_wsr_epc7_Slot_inst_encode, 0, 0
  8200. };
  8201. static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
  8202. Opcode_xsr_epc7_Slot_inst_encode, 0, 0
  8203. };
  8204. static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
  8205. Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
  8206. };
  8207. static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
  8208. Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
  8209. };
  8210. static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
  8211. Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
  8212. };
  8213. static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
  8214. Opcode_rsr_eps2_Slot_inst_encode, 0, 0
  8215. };
  8216. static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
  8217. Opcode_wsr_eps2_Slot_inst_encode, 0, 0
  8218. };
  8219. static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
  8220. Opcode_xsr_eps2_Slot_inst_encode, 0, 0
  8221. };
  8222. static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
  8223. Opcode_rsr_eps3_Slot_inst_encode, 0, 0
  8224. };
  8225. static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
  8226. Opcode_wsr_eps3_Slot_inst_encode, 0, 0
  8227. };
  8228. static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
  8229. Opcode_xsr_eps3_Slot_inst_encode, 0, 0
  8230. };
  8231. static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
  8232. Opcode_rsr_eps4_Slot_inst_encode, 0, 0
  8233. };
  8234. static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
  8235. Opcode_wsr_eps4_Slot_inst_encode, 0, 0
  8236. };
  8237. static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
  8238. Opcode_xsr_eps4_Slot_inst_encode, 0, 0
  8239. };
  8240. static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
  8241. Opcode_rsr_eps5_Slot_inst_encode, 0, 0
  8242. };
  8243. static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
  8244. Opcode_wsr_eps5_Slot_inst_encode, 0, 0
  8245. };
  8246. static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
  8247. Opcode_xsr_eps5_Slot_inst_encode, 0, 0
  8248. };
  8249. static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
  8250. Opcode_rsr_eps6_Slot_inst_encode, 0, 0
  8251. };
  8252. static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
  8253. Opcode_wsr_eps6_Slot_inst_encode, 0, 0
  8254. };
  8255. static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
  8256. Opcode_xsr_eps6_Slot_inst_encode, 0, 0
  8257. };
  8258. static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
  8259. Opcode_rsr_eps7_Slot_inst_encode, 0, 0
  8260. };
  8261. static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
  8262. Opcode_wsr_eps7_Slot_inst_encode, 0, 0
  8263. };
  8264. static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
  8265. Opcode_xsr_eps7_Slot_inst_encode, 0, 0
  8266. };
  8267. static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
  8268. Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
  8269. };
  8270. static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
  8271. Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
  8272. };
  8273. static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
  8274. Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
  8275. };
  8276. static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
  8277. Opcode_rsr_depc_Slot_inst_encode, 0, 0
  8278. };
  8279. static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
  8280. Opcode_wsr_depc_Slot_inst_encode, 0, 0
  8281. };
  8282. static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
  8283. Opcode_xsr_depc_Slot_inst_encode, 0, 0
  8284. };
  8285. static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
  8286. Opcode_rsr_exccause_Slot_inst_encode, 0, 0
  8287. };
  8288. static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
  8289. Opcode_wsr_exccause_Slot_inst_encode, 0, 0
  8290. };
  8291. static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
  8292. Opcode_xsr_exccause_Slot_inst_encode, 0, 0
  8293. };
  8294. static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
  8295. Opcode_rsr_misc0_Slot_inst_encode, 0, 0
  8296. };
  8297. static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
  8298. Opcode_wsr_misc0_Slot_inst_encode, 0, 0
  8299. };
  8300. static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
  8301. Opcode_xsr_misc0_Slot_inst_encode, 0, 0
  8302. };
  8303. static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
  8304. Opcode_rsr_misc1_Slot_inst_encode, 0, 0
  8305. };
  8306. static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
  8307. Opcode_wsr_misc1_Slot_inst_encode, 0, 0
  8308. };
  8309. static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
  8310. Opcode_xsr_misc1_Slot_inst_encode, 0, 0
  8311. };
  8312. static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
  8313. Opcode_rsr_prid_Slot_inst_encode, 0, 0
  8314. };
  8315. static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
  8316. Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
  8317. };
  8318. static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
  8319. Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
  8320. };
  8321. static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
  8322. Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
  8323. };
  8324. static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
  8325. Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
  8326. };
  8327. static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
  8328. Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
  8329. };
  8330. static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
  8331. Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
  8332. };
  8333. static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
  8334. Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
  8335. };
  8336. static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
  8337. Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
  8338. };
  8339. static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
  8340. Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
  8341. };
  8342. static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
  8343. Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
  8344. };
  8345. static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
  8346. Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
  8347. };
  8348. static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
  8349. Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
  8350. };
  8351. static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
  8352. Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
  8353. };
  8354. static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
  8355. Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
  8356. };
  8357. static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
  8358. Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
  8359. };
  8360. static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
  8361. Opcode_mul_da_ll_Slot_inst_encode, 0, 0
  8362. };
  8363. static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
  8364. Opcode_mul_da_hl_Slot_inst_encode, 0, 0
  8365. };
  8366. static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
  8367. Opcode_mul_da_lh_Slot_inst_encode, 0, 0
  8368. };
  8369. static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
  8370. Opcode_mul_da_hh_Slot_inst_encode, 0, 0
  8371. };
  8372. static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
  8373. Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
  8374. };
  8375. static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
  8376. Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
  8377. };
  8378. static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
  8379. Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
  8380. };
  8381. static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
  8382. Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
  8383. };
  8384. static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
  8385. Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
  8386. };
  8387. static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
  8388. Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
  8389. };
  8390. static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
  8391. Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
  8392. };
  8393. static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
  8394. Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
  8395. };
  8396. static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
  8397. Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
  8398. };
  8399. static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
  8400. Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
  8401. };
  8402. static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
  8403. Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
  8404. };
  8405. static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
  8406. Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
  8407. };
  8408. static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
  8409. Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
  8410. };
  8411. static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
  8412. Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
  8413. };
  8414. static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
  8415. Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
  8416. };
  8417. static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
  8418. Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
  8419. };
  8420. static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
  8421. Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
  8422. };
  8423. static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
  8424. Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
  8425. };
  8426. static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
  8427. Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
  8428. };
  8429. static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
  8430. Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
  8431. };
  8432. static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
  8433. Opcode_mula_da_ll_Slot_inst_encode, 0, 0
  8434. };
  8435. static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
  8436. Opcode_mula_da_hl_Slot_inst_encode, 0, 0
  8437. };
  8438. static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
  8439. Opcode_mula_da_lh_Slot_inst_encode, 0, 0
  8440. };
  8441. static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
  8442. Opcode_mula_da_hh_Slot_inst_encode, 0, 0
  8443. };
  8444. static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
  8445. Opcode_muls_da_ll_Slot_inst_encode, 0, 0
  8446. };
  8447. static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
  8448. Opcode_muls_da_hl_Slot_inst_encode, 0, 0
  8449. };
  8450. static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
  8451. Opcode_muls_da_lh_Slot_inst_encode, 0, 0
  8452. };
  8453. static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
  8454. Opcode_muls_da_hh_Slot_inst_encode, 0, 0
  8455. };
  8456. static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
  8457. Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
  8458. };
  8459. static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
  8460. Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
  8461. };
  8462. static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
  8463. Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
  8464. };
  8465. static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
  8466. Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
  8467. };
  8468. static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
  8469. Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
  8470. };
  8471. static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
  8472. Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
  8473. };
  8474. static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
  8475. Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
  8476. };
  8477. static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
  8478. Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
  8479. };
  8480. static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
  8481. Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
  8482. };
  8483. static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
  8484. Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
  8485. };
  8486. static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
  8487. Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
  8488. };
  8489. static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
  8490. Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
  8491. };
  8492. static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
  8493. Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
  8494. };
  8495. static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
  8496. Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
  8497. };
  8498. static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
  8499. Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
  8500. };
  8501. static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
  8502. Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
  8503. };
  8504. static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
  8505. Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
  8506. };
  8507. static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
  8508. Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
  8509. };
  8510. static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
  8511. Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
  8512. };
  8513. static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
  8514. Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
  8515. };
  8516. static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
  8517. Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
  8518. };
  8519. static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
  8520. Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
  8521. };
  8522. static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
  8523. Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
  8524. };
  8525. static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
  8526. Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
  8527. };
  8528. static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
  8529. Opcode_lddec_Slot_inst_encode, 0, 0
  8530. };
  8531. static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
  8532. Opcode_ldinc_Slot_inst_encode, 0, 0
  8533. };
  8534. static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
  8535. Opcode_mul16u_Slot_inst_encode, 0, 0
  8536. };
  8537. static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
  8538. Opcode_mul16s_Slot_inst_encode, 0, 0
  8539. };
  8540. static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
  8541. Opcode_rsr_m0_Slot_inst_encode, 0, 0
  8542. };
  8543. static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
  8544. Opcode_wsr_m0_Slot_inst_encode, 0, 0
  8545. };
  8546. static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
  8547. Opcode_xsr_m0_Slot_inst_encode, 0, 0
  8548. };
  8549. static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
  8550. Opcode_rsr_m1_Slot_inst_encode, 0, 0
  8551. };
  8552. static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
  8553. Opcode_wsr_m1_Slot_inst_encode, 0, 0
  8554. };
  8555. static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
  8556. Opcode_xsr_m1_Slot_inst_encode, 0, 0
  8557. };
  8558. static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
  8559. Opcode_rsr_m2_Slot_inst_encode, 0, 0
  8560. };
  8561. static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
  8562. Opcode_wsr_m2_Slot_inst_encode, 0, 0
  8563. };
  8564. static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
  8565. Opcode_xsr_m2_Slot_inst_encode, 0, 0
  8566. };
  8567. static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
  8568. Opcode_rsr_m3_Slot_inst_encode, 0, 0
  8569. };
  8570. static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
  8571. Opcode_wsr_m3_Slot_inst_encode, 0, 0
  8572. };
  8573. static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
  8574. Opcode_xsr_m3_Slot_inst_encode, 0, 0
  8575. };
  8576. static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
  8577. Opcode_rsr_acclo_Slot_inst_encode, 0, 0
  8578. };
  8579. static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
  8580. Opcode_wsr_acclo_Slot_inst_encode, 0, 0
  8581. };
  8582. static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
  8583. Opcode_xsr_acclo_Slot_inst_encode, 0, 0
  8584. };
  8585. static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
  8586. Opcode_rsr_acchi_Slot_inst_encode, 0, 0
  8587. };
  8588. static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
  8589. Opcode_wsr_acchi_Slot_inst_encode, 0, 0
  8590. };
  8591. static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
  8592. Opcode_xsr_acchi_Slot_inst_encode, 0, 0
  8593. };
  8594. static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
  8595. Opcode_rfi_Slot_inst_encode, 0, 0
  8596. };
  8597. static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
  8598. Opcode_waiti_Slot_inst_encode, 0, 0
  8599. };
  8600. static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
  8601. Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
  8602. };
  8603. static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
  8604. Opcode_wsr_intset_Slot_inst_encode, 0, 0
  8605. };
  8606. static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
  8607. Opcode_wsr_intclear_Slot_inst_encode, 0, 0
  8608. };
  8609. static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
  8610. Opcode_rsr_intenable_Slot_inst_encode, 0, 0
  8611. };
  8612. static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
  8613. Opcode_wsr_intenable_Slot_inst_encode, 0, 0
  8614. };
  8615. static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
  8616. Opcode_xsr_intenable_Slot_inst_encode, 0, 0
  8617. };
  8618. static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
  8619. Opcode_break_Slot_inst_encode, 0, 0
  8620. };
  8621. static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
  8622. 0, 0, Opcode_break_n_Slot_inst16b_encode
  8623. };
  8624. static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
  8625. Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
  8626. };
  8627. static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
  8628. Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
  8629. };
  8630. static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
  8631. Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
  8632. };
  8633. static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
  8634. Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
  8635. };
  8636. static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
  8637. Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
  8638. };
  8639. static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
  8640. Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
  8641. };
  8642. static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
  8643. Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
  8644. };
  8645. static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
  8646. Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
  8647. };
  8648. static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
  8649. Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
  8650. };
  8651. static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
  8652. Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
  8653. };
  8654. static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
  8655. Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
  8656. };
  8657. static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
  8658. Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
  8659. };
  8660. static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
  8661. Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
  8662. };
  8663. static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
  8664. Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
  8665. };
  8666. static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
  8667. Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
  8668. };
  8669. static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
  8670. Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
  8671. };
  8672. static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
  8673. Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
  8674. };
  8675. static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
  8676. Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
  8677. };
  8678. static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
  8679. Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
  8680. };
  8681. static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
  8682. Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
  8683. };
  8684. static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
  8685. Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
  8686. };
  8687. static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
  8688. Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
  8689. };
  8690. static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
  8691. Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
  8692. };
  8693. static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
  8694. Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
  8695. };
  8696. static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
  8697. Opcode_rsr_icount_Slot_inst_encode, 0, 0
  8698. };
  8699. static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
  8700. Opcode_wsr_icount_Slot_inst_encode, 0, 0
  8701. };
  8702. static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
  8703. Opcode_xsr_icount_Slot_inst_encode, 0, 0
  8704. };
  8705. static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
  8706. Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
  8707. };
  8708. static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
  8709. Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
  8710. };
  8711. static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
  8712. Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
  8713. };
  8714. static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
  8715. Opcode_rsr_ddr_Slot_inst_encode, 0, 0
  8716. };
  8717. static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
  8718. Opcode_wsr_ddr_Slot_inst_encode, 0, 0
  8719. };
  8720. static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
  8721. Opcode_xsr_ddr_Slot_inst_encode, 0, 0
  8722. };
  8723. static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
  8724. Opcode_rfdo_Slot_inst_encode, 0, 0
  8725. };
  8726. static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
  8727. Opcode_rfdd_Slot_inst_encode, 0, 0
  8728. };
  8729. static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
  8730. Opcode_wsr_mmid_Slot_inst_encode, 0, 0
  8731. };
  8732. static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
  8733. Opcode_rsr_ccount_Slot_inst_encode, 0, 0
  8734. };
  8735. static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
  8736. Opcode_wsr_ccount_Slot_inst_encode, 0, 0
  8737. };
  8738. static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
  8739. Opcode_xsr_ccount_Slot_inst_encode, 0, 0
  8740. };
  8741. static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
  8742. Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
  8743. };
  8744. static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
  8745. Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
  8746. };
  8747. static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
  8748. Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
  8749. };
  8750. static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
  8751. Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
  8752. };
  8753. static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
  8754. Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
  8755. };
  8756. static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
  8757. Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
  8758. };
  8759. static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
  8760. Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
  8761. };
  8762. static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
  8763. Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
  8764. };
  8765. static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
  8766. Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
  8767. };
  8768. static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
  8769. Opcode_ipf_Slot_inst_encode, 0, 0
  8770. };
  8771. static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
  8772. Opcode_ihi_Slot_inst_encode, 0, 0
  8773. };
  8774. static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
  8775. Opcode_ipfl_Slot_inst_encode, 0, 0
  8776. };
  8777. static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
  8778. Opcode_ihu_Slot_inst_encode, 0, 0
  8779. };
  8780. static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
  8781. Opcode_iiu_Slot_inst_encode, 0, 0
  8782. };
  8783. static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
  8784. Opcode_iii_Slot_inst_encode, 0, 0
  8785. };
  8786. static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
  8787. Opcode_lict_Slot_inst_encode, 0, 0
  8788. };
  8789. static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
  8790. Opcode_licw_Slot_inst_encode, 0, 0
  8791. };
  8792. static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
  8793. Opcode_sict_Slot_inst_encode, 0, 0
  8794. };
  8795. static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
  8796. Opcode_sicw_Slot_inst_encode, 0, 0
  8797. };
  8798. static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
  8799. Opcode_dhwb_Slot_inst_encode, 0, 0
  8800. };
  8801. static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
  8802. Opcode_dhwbi_Slot_inst_encode, 0, 0
  8803. };
  8804. static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
  8805. Opcode_diwb_Slot_inst_encode, 0, 0
  8806. };
  8807. static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
  8808. Opcode_diwbi_Slot_inst_encode, 0, 0
  8809. };
  8810. static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
  8811. Opcode_dhi_Slot_inst_encode, 0, 0
  8812. };
  8813. static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
  8814. Opcode_dii_Slot_inst_encode, 0, 0
  8815. };
  8816. static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
  8817. Opcode_dpfr_Slot_inst_encode, 0, 0
  8818. };
  8819. static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
  8820. Opcode_dpfw_Slot_inst_encode, 0, 0
  8821. };
  8822. static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
  8823. Opcode_dpfro_Slot_inst_encode, 0, 0
  8824. };
  8825. static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
  8826. Opcode_dpfwo_Slot_inst_encode, 0, 0
  8827. };
  8828. static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
  8829. Opcode_dpfl_Slot_inst_encode, 0, 0
  8830. };
  8831. static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
  8832. Opcode_dhu_Slot_inst_encode, 0, 0
  8833. };
  8834. static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
  8835. Opcode_diu_Slot_inst_encode, 0, 0
  8836. };
  8837. static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
  8838. Opcode_sdct_Slot_inst_encode, 0, 0
  8839. };
  8840. static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
  8841. Opcode_ldct_Slot_inst_encode, 0, 0
  8842. };
  8843. static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
  8844. Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
  8845. };
  8846. static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
  8847. Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
  8848. };
  8849. static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
  8850. Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
  8851. };
  8852. static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
  8853. Opcode_rsr_rasid_Slot_inst_encode, 0, 0
  8854. };
  8855. static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
  8856. Opcode_wsr_rasid_Slot_inst_encode, 0, 0
  8857. };
  8858. static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
  8859. Opcode_xsr_rasid_Slot_inst_encode, 0, 0
  8860. };
  8861. static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
  8862. Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
  8863. };
  8864. static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
  8865. Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
  8866. };
  8867. static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
  8868. Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
  8869. };
  8870. static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
  8871. Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
  8872. };
  8873. static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
  8874. Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
  8875. };
  8876. static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
  8877. Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
  8878. };
  8879. static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
  8880. Opcode_idtlb_Slot_inst_encode, 0, 0
  8881. };
  8882. static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
  8883. Opcode_pdtlb_Slot_inst_encode, 0, 0
  8884. };
  8885. static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
  8886. Opcode_rdtlb0_Slot_inst_encode, 0, 0
  8887. };
  8888. static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
  8889. Opcode_rdtlb1_Slot_inst_encode, 0, 0
  8890. };
  8891. static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
  8892. Opcode_wdtlb_Slot_inst_encode, 0, 0
  8893. };
  8894. static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
  8895. Opcode_iitlb_Slot_inst_encode, 0, 0
  8896. };
  8897. static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
  8898. Opcode_pitlb_Slot_inst_encode, 0, 0
  8899. };
  8900. static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
  8901. Opcode_ritlb0_Slot_inst_encode, 0, 0
  8902. };
  8903. static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
  8904. Opcode_ritlb1_Slot_inst_encode, 0, 0
  8905. };
  8906. static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
  8907. Opcode_witlb_Slot_inst_encode, 0, 0
  8908. };
  8909. static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
  8910. Opcode_ldpte_Slot_inst_encode, 0, 0
  8911. };
  8912. static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
  8913. Opcode_hwwitlba_Slot_inst_encode, 0, 0
  8914. };
  8915. static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
  8916. Opcode_hwwdtlba_Slot_inst_encode, 0, 0
  8917. };
  8918. static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
  8919. Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
  8920. };
  8921. static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
  8922. Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
  8923. };
  8924. static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
  8925. Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
  8926. };
  8927. static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
  8928. Opcode_clamps_Slot_inst_encode, 0, 0
  8929. };
  8930. static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
  8931. Opcode_min_Slot_inst_encode, 0, 0
  8932. };
  8933. static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
  8934. Opcode_max_Slot_inst_encode, 0, 0
  8935. };
  8936. static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
  8937. Opcode_minu_Slot_inst_encode, 0, 0
  8938. };
  8939. static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
  8940. Opcode_maxu_Slot_inst_encode, 0, 0
  8941. };
  8942. static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
  8943. Opcode_nsa_Slot_inst_encode, 0, 0
  8944. };
  8945. static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
  8946. Opcode_nsau_Slot_inst_encode, 0, 0
  8947. };
  8948. static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
  8949. Opcode_sext_Slot_inst_encode, 0, 0
  8950. };
  8951. static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
  8952. Opcode_l32ai_Slot_inst_encode, 0, 0
  8953. };
  8954. static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
  8955. Opcode_s32ri_Slot_inst_encode, 0, 0
  8956. };
  8957. static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
  8958. Opcode_s32c1i_Slot_inst_encode, 0, 0
  8959. };
  8960. static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
  8961. Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
  8962. };
  8963. static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
  8964. Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
  8965. };
  8966. static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
  8967. Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
  8968. };
  8969. static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
  8970. Opcode_quou_Slot_inst_encode, 0, 0
  8971. };
  8972. static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
  8973. Opcode_quos_Slot_inst_encode, 0, 0
  8974. };
  8975. static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
  8976. Opcode_remu_Slot_inst_encode, 0, 0
  8977. };
  8978. static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
  8979. Opcode_rems_Slot_inst_encode, 0, 0
  8980. };
  8981. static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
  8982. Opcode_mull_Slot_inst_encode, 0, 0
  8983. };
  8984. static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
  8985. Opcode_rur_expstate_Slot_inst_encode, 0, 0
  8986. };
  8987. static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
  8988. Opcode_wur_expstate_Slot_inst_encode, 0, 0
  8989. };
  8990. static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
  8991. Opcode_read_impwire_Slot_inst_encode, 0, 0
  8992. };
  8993. static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
  8994. Opcode_setb_expstate_Slot_inst_encode, 0, 0
  8995. };
  8996. static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
  8997. Opcode_clrb_expstate_Slot_inst_encode, 0, 0
  8998. };
  8999. static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
  9000. Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
  9001. };
  9002. /* Opcode table. */
  9003. static xtensa_opcode_internal opcodes[] = {
  9004. { "excw", 0 /* xt_iclass_excw */,
  9005. 0,
  9006. Opcode_excw_encode_fns, 0, 0 },
  9007. { "rfe", 1 /* xt_iclass_rfe */,
  9008. XTENSA_OPCODE_IS_JUMP,
  9009. Opcode_rfe_encode_fns, 0, 0 },
  9010. { "rfde", 2 /* xt_iclass_rfde */,
  9011. XTENSA_OPCODE_IS_JUMP,
  9012. Opcode_rfde_encode_fns, 0, 0 },
  9013. { "syscall", 3 /* xt_iclass_syscall */,
  9014. 0,
  9015. Opcode_syscall_encode_fns, 0, 0 },
  9016. { "simcall", 4 /* xt_iclass_simcall */,
  9017. 0,
  9018. Opcode_simcall_encode_fns, 0, 0 },
  9019. { "call12", 5 /* xt_iclass_call12 */,
  9020. XTENSA_OPCODE_IS_CALL,
  9021. Opcode_call12_encode_fns, 0, 0 },
  9022. { "call8", 6 /* xt_iclass_call8 */,
  9023. XTENSA_OPCODE_IS_CALL,
  9024. Opcode_call8_encode_fns, 0, 0 },
  9025. { "call4", 7 /* xt_iclass_call4 */,
  9026. XTENSA_OPCODE_IS_CALL,
  9027. Opcode_call4_encode_fns, 0, 0 },
  9028. { "callx12", 8 /* xt_iclass_callx12 */,
  9029. XTENSA_OPCODE_IS_CALL,
  9030. Opcode_callx12_encode_fns, 0, 0 },
  9031. { "callx8", 9 /* xt_iclass_callx8 */,
  9032. XTENSA_OPCODE_IS_CALL,
  9033. Opcode_callx8_encode_fns, 0, 0 },
  9034. { "callx4", 10 /* xt_iclass_callx4 */,
  9035. XTENSA_OPCODE_IS_CALL,
  9036. Opcode_callx4_encode_fns, 0, 0 },
  9037. { "entry", 11 /* xt_iclass_entry */,
  9038. 0,
  9039. Opcode_entry_encode_fns, 0, 0 },
  9040. { "movsp", 12 /* xt_iclass_movsp */,
  9041. 0,
  9042. Opcode_movsp_encode_fns, 0, 0 },
  9043. { "rotw", 13 /* xt_iclass_rotw */,
  9044. 0,
  9045. Opcode_rotw_encode_fns, 0, 0 },
  9046. { "retw", 14 /* xt_iclass_retw */,
  9047. XTENSA_OPCODE_IS_JUMP,
  9048. Opcode_retw_encode_fns, 0, 0 },
  9049. { "retw.n", 14 /* xt_iclass_retw */,
  9050. XTENSA_OPCODE_IS_JUMP,
  9051. Opcode_retw_n_encode_fns, 0, 0 },
  9052. { "rfwo", 15 /* xt_iclass_rfwou */,
  9053. XTENSA_OPCODE_IS_JUMP,
  9054. Opcode_rfwo_encode_fns, 0, 0 },
  9055. { "rfwu", 15 /* xt_iclass_rfwou */,
  9056. XTENSA_OPCODE_IS_JUMP,
  9057. Opcode_rfwu_encode_fns, 0, 0 },
  9058. { "l32e", 16 /* xt_iclass_l32e */,
  9059. 0,
  9060. Opcode_l32e_encode_fns, 0, 0 },
  9061. { "s32e", 17 /* xt_iclass_s32e */,
  9062. 0,
  9063. Opcode_s32e_encode_fns, 0, 0 },
  9064. { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
  9065. 0,
  9066. Opcode_rsr_windowbase_encode_fns, 0, 0 },
  9067. { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
  9068. 0,
  9069. Opcode_wsr_windowbase_encode_fns, 0, 0 },
  9070. { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
  9071. 0,
  9072. Opcode_xsr_windowbase_encode_fns, 0, 0 },
  9073. { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
  9074. 0,
  9075. Opcode_rsr_windowstart_encode_fns, 0, 0 },
  9076. { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
  9077. 0,
  9078. Opcode_wsr_windowstart_encode_fns, 0, 0 },
  9079. { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
  9080. 0,
  9081. Opcode_xsr_windowstart_encode_fns, 0, 0 },
  9082. { "add.n", 24 /* xt_iclass_add.n */,
  9083. 0,
  9084. Opcode_add_n_encode_fns, 0, 0 },
  9085. { "addi.n", 25 /* xt_iclass_addi.n */,
  9086. 0,
  9087. Opcode_addi_n_encode_fns, 0, 0 },
  9088. { "beqz.n", 26 /* xt_iclass_bz6 */,
  9089. XTENSA_OPCODE_IS_BRANCH,
  9090. Opcode_beqz_n_encode_fns, 0, 0 },
  9091. { "bnez.n", 26 /* xt_iclass_bz6 */,
  9092. XTENSA_OPCODE_IS_BRANCH,
  9093. Opcode_bnez_n_encode_fns, 0, 0 },
  9094. { "ill.n", 27 /* xt_iclass_ill.n */,
  9095. 0,
  9096. Opcode_ill_n_encode_fns, 0, 0 },
  9097. { "l32i.n", 28 /* xt_iclass_loadi4 */,
  9098. 0,
  9099. Opcode_l32i_n_encode_fns, 0, 0 },
  9100. { "mov.n", 29 /* xt_iclass_mov.n */,
  9101. 0,
  9102. Opcode_mov_n_encode_fns, 0, 0 },
  9103. { "movi.n", 30 /* xt_iclass_movi.n */,
  9104. 0,
  9105. Opcode_movi_n_encode_fns, 0, 0 },
  9106. { "nop.n", 31 /* xt_iclass_nopn */,
  9107. 0,
  9108. Opcode_nop_n_encode_fns, 0, 0 },
  9109. { "ret.n", 32 /* xt_iclass_retn */,
  9110. XTENSA_OPCODE_IS_JUMP,
  9111. Opcode_ret_n_encode_fns, 0, 0 },
  9112. { "s32i.n", 33 /* xt_iclass_storei4 */,
  9113. 0,
  9114. Opcode_s32i_n_encode_fns, 0, 0 },
  9115. { "rur.threadptr", 34 /* rur_threadptr */,
  9116. 0,
  9117. Opcode_rur_threadptr_encode_fns, 0, 0 },
  9118. { "wur.threadptr", 35 /* wur_threadptr */,
  9119. 0,
  9120. Opcode_wur_threadptr_encode_fns, 0, 0 },
  9121. { "addi", 36 /* xt_iclass_addi */,
  9122. 0,
  9123. Opcode_addi_encode_fns, 0, 0 },
  9124. { "addmi", 37 /* xt_iclass_addmi */,
  9125. 0,
  9126. Opcode_addmi_encode_fns, 0, 0 },
  9127. { "add", 38 /* xt_iclass_addsub */,
  9128. 0,
  9129. Opcode_add_encode_fns, 0, 0 },
  9130. { "sub", 38 /* xt_iclass_addsub */,
  9131. 0,
  9132. Opcode_sub_encode_fns, 0, 0 },
  9133. { "addx2", 38 /* xt_iclass_addsub */,
  9134. 0,
  9135. Opcode_addx2_encode_fns, 0, 0 },
  9136. { "addx4", 38 /* xt_iclass_addsub */,
  9137. 0,
  9138. Opcode_addx4_encode_fns, 0, 0 },
  9139. { "addx8", 38 /* xt_iclass_addsub */,
  9140. 0,
  9141. Opcode_addx8_encode_fns, 0, 0 },
  9142. { "subx2", 38 /* xt_iclass_addsub */,
  9143. 0,
  9144. Opcode_subx2_encode_fns, 0, 0 },
  9145. { "subx4", 38 /* xt_iclass_addsub */,
  9146. 0,
  9147. Opcode_subx4_encode_fns, 0, 0 },
  9148. { "subx8", 38 /* xt_iclass_addsub */,
  9149. 0,
  9150. Opcode_subx8_encode_fns, 0, 0 },
  9151. { "and", 39 /* xt_iclass_bit */,
  9152. 0,
  9153. Opcode_and_encode_fns, 0, 0 },
  9154. { "or", 39 /* xt_iclass_bit */,
  9155. 0,
  9156. Opcode_or_encode_fns, 0, 0 },
  9157. { "xor", 39 /* xt_iclass_bit */,
  9158. 0,
  9159. Opcode_xor_encode_fns, 0, 0 },
  9160. { "beqi", 40 /* xt_iclass_bsi8 */,
  9161. XTENSA_OPCODE_IS_BRANCH,
  9162. Opcode_beqi_encode_fns, 0, 0 },
  9163. { "bnei", 40 /* xt_iclass_bsi8 */,
  9164. XTENSA_OPCODE_IS_BRANCH,
  9165. Opcode_bnei_encode_fns, 0, 0 },
  9166. { "bgei", 40 /* xt_iclass_bsi8 */,
  9167. XTENSA_OPCODE_IS_BRANCH,
  9168. Opcode_bgei_encode_fns, 0, 0 },
  9169. { "blti", 40 /* xt_iclass_bsi8 */,
  9170. XTENSA_OPCODE_IS_BRANCH,
  9171. Opcode_blti_encode_fns, 0, 0 },
  9172. { "bbci", 41 /* xt_iclass_bsi8b */,
  9173. XTENSA_OPCODE_IS_BRANCH,
  9174. Opcode_bbci_encode_fns, 0, 0 },
  9175. { "bbsi", 41 /* xt_iclass_bsi8b */,
  9176. XTENSA_OPCODE_IS_BRANCH,
  9177. Opcode_bbsi_encode_fns, 0, 0 },
  9178. { "bgeui", 42 /* xt_iclass_bsi8u */,
  9179. XTENSA_OPCODE_IS_BRANCH,
  9180. Opcode_bgeui_encode_fns, 0, 0 },
  9181. { "bltui", 42 /* xt_iclass_bsi8u */,
  9182. XTENSA_OPCODE_IS_BRANCH,
  9183. Opcode_bltui_encode_fns, 0, 0 },
  9184. { "beq", 43 /* xt_iclass_bst8 */,
  9185. XTENSA_OPCODE_IS_BRANCH,
  9186. Opcode_beq_encode_fns, 0, 0 },
  9187. { "bne", 43 /* xt_iclass_bst8 */,
  9188. XTENSA_OPCODE_IS_BRANCH,
  9189. Opcode_bne_encode_fns, 0, 0 },
  9190. { "bge", 43 /* xt_iclass_bst8 */,
  9191. XTENSA_OPCODE_IS_BRANCH,
  9192. Opcode_bge_encode_fns, 0, 0 },
  9193. { "blt", 43 /* xt_iclass_bst8 */,
  9194. XTENSA_OPCODE_IS_BRANCH,
  9195. Opcode_blt_encode_fns, 0, 0 },
  9196. { "bgeu", 43 /* xt_iclass_bst8 */,
  9197. XTENSA_OPCODE_IS_BRANCH,
  9198. Opcode_bgeu_encode_fns, 0, 0 },
  9199. { "bltu", 43 /* xt_iclass_bst8 */,
  9200. XTENSA_OPCODE_IS_BRANCH,
  9201. Opcode_bltu_encode_fns, 0, 0 },
  9202. { "bany", 43 /* xt_iclass_bst8 */,
  9203. XTENSA_OPCODE_IS_BRANCH,
  9204. Opcode_bany_encode_fns, 0, 0 },
  9205. { "bnone", 43 /* xt_iclass_bst8 */,
  9206. XTENSA_OPCODE_IS_BRANCH,
  9207. Opcode_bnone_encode_fns, 0, 0 },
  9208. { "ball", 43 /* xt_iclass_bst8 */,
  9209. XTENSA_OPCODE_IS_BRANCH,
  9210. Opcode_ball_encode_fns, 0, 0 },
  9211. { "bnall", 43 /* xt_iclass_bst8 */,
  9212. XTENSA_OPCODE_IS_BRANCH,
  9213. Opcode_bnall_encode_fns, 0, 0 },
  9214. { "bbc", 43 /* xt_iclass_bst8 */,
  9215. XTENSA_OPCODE_IS_BRANCH,
  9216. Opcode_bbc_encode_fns, 0, 0 },
  9217. { "bbs", 43 /* xt_iclass_bst8 */,
  9218. XTENSA_OPCODE_IS_BRANCH,
  9219. Opcode_bbs_encode_fns, 0, 0 },
  9220. { "beqz", 44 /* xt_iclass_bsz12 */,
  9221. XTENSA_OPCODE_IS_BRANCH,
  9222. Opcode_beqz_encode_fns, 0, 0 },
  9223. { "bnez", 44 /* xt_iclass_bsz12 */,
  9224. XTENSA_OPCODE_IS_BRANCH,
  9225. Opcode_bnez_encode_fns, 0, 0 },
  9226. { "bgez", 44 /* xt_iclass_bsz12 */,
  9227. XTENSA_OPCODE_IS_BRANCH,
  9228. Opcode_bgez_encode_fns, 0, 0 },
  9229. { "bltz", 44 /* xt_iclass_bsz12 */,
  9230. XTENSA_OPCODE_IS_BRANCH,
  9231. Opcode_bltz_encode_fns, 0, 0 },
  9232. { "call0", 45 /* xt_iclass_call0 */,
  9233. XTENSA_OPCODE_IS_CALL,
  9234. Opcode_call0_encode_fns, 0, 0 },
  9235. { "callx0", 46 /* xt_iclass_callx0 */,
  9236. XTENSA_OPCODE_IS_CALL,
  9237. Opcode_callx0_encode_fns, 0, 0 },
  9238. { "extui", 47 /* xt_iclass_exti */,
  9239. 0,
  9240. Opcode_extui_encode_fns, 0, 0 },
  9241. { "ill", 48 /* xt_iclass_ill */,
  9242. 0,
  9243. Opcode_ill_encode_fns, 0, 0 },
  9244. { "j", 49 /* xt_iclass_jump */,
  9245. XTENSA_OPCODE_IS_JUMP,
  9246. Opcode_j_encode_fns, 0, 0 },
  9247. { "jx", 50 /* xt_iclass_jumpx */,
  9248. XTENSA_OPCODE_IS_JUMP,
  9249. Opcode_jx_encode_fns, 0, 0 },
  9250. { "l16ui", 51 /* xt_iclass_l16ui */,
  9251. 0,
  9252. Opcode_l16ui_encode_fns, 0, 0 },
  9253. { "l16si", 52 /* xt_iclass_l16si */,
  9254. 0,
  9255. Opcode_l16si_encode_fns, 0, 0 },
  9256. { "l32i", 53 /* xt_iclass_l32i */,
  9257. 0,
  9258. Opcode_l32i_encode_fns, 0, 0 },
  9259. { "l32r", 54 /* xt_iclass_l32r */,
  9260. 0,
  9261. Opcode_l32r_encode_fns, 0, 0 },
  9262. { "l8ui", 55 /* xt_iclass_l8i */,
  9263. 0,
  9264. Opcode_l8ui_encode_fns, 0, 0 },
  9265. { "loop", 56 /* xt_iclass_loop */,
  9266. XTENSA_OPCODE_IS_LOOP,
  9267. Opcode_loop_encode_fns, 0, 0 },
  9268. { "loopnez", 57 /* xt_iclass_loopz */,
  9269. XTENSA_OPCODE_IS_LOOP,
  9270. Opcode_loopnez_encode_fns, 0, 0 },
  9271. { "loopgtz", 57 /* xt_iclass_loopz */,
  9272. XTENSA_OPCODE_IS_LOOP,
  9273. Opcode_loopgtz_encode_fns, 0, 0 },
  9274. { "movi", 58 /* xt_iclass_movi */,
  9275. 0,
  9276. Opcode_movi_encode_fns, 0, 0 },
  9277. { "moveqz", 59 /* xt_iclass_movz */,
  9278. 0,
  9279. Opcode_moveqz_encode_fns, 0, 0 },
  9280. { "movnez", 59 /* xt_iclass_movz */,
  9281. 0,
  9282. Opcode_movnez_encode_fns, 0, 0 },
  9283. { "movltz", 59 /* xt_iclass_movz */,
  9284. 0,
  9285. Opcode_movltz_encode_fns, 0, 0 },
  9286. { "movgez", 59 /* xt_iclass_movz */,
  9287. 0,
  9288. Opcode_movgez_encode_fns, 0, 0 },
  9289. { "neg", 60 /* xt_iclass_neg */,
  9290. 0,
  9291. Opcode_neg_encode_fns, 0, 0 },
  9292. { "abs", 60 /* xt_iclass_neg */,
  9293. 0,
  9294. Opcode_abs_encode_fns, 0, 0 },
  9295. { "nop", 61 /* xt_iclass_nop */,
  9296. 0,
  9297. Opcode_nop_encode_fns, 0, 0 },
  9298. { "ret", 62 /* xt_iclass_return */,
  9299. XTENSA_OPCODE_IS_JUMP,
  9300. Opcode_ret_encode_fns, 0, 0 },
  9301. { "s16i", 63 /* xt_iclass_s16i */,
  9302. 0,
  9303. Opcode_s16i_encode_fns, 0, 0 },
  9304. { "s32i", 64 /* xt_iclass_s32i */,
  9305. 0,
  9306. Opcode_s32i_encode_fns, 0, 0 },
  9307. { "s8i", 65 /* xt_iclass_s8i */,
  9308. 0,
  9309. Opcode_s8i_encode_fns, 0, 0 },
  9310. { "ssr", 66 /* xt_iclass_sar */,
  9311. 0,
  9312. Opcode_ssr_encode_fns, 0, 0 },
  9313. { "ssl", 66 /* xt_iclass_sar */,
  9314. 0,
  9315. Opcode_ssl_encode_fns, 0, 0 },
  9316. { "ssa8l", 66 /* xt_iclass_sar */,
  9317. 0,
  9318. Opcode_ssa8l_encode_fns, 0, 0 },
  9319. { "ssa8b", 66 /* xt_iclass_sar */,
  9320. 0,
  9321. Opcode_ssa8b_encode_fns, 0, 0 },
  9322. { "ssai", 67 /* xt_iclass_sari */,
  9323. 0,
  9324. Opcode_ssai_encode_fns, 0, 0 },
  9325. { "sll", 68 /* xt_iclass_shifts */,
  9326. 0,
  9327. Opcode_sll_encode_fns, 0, 0 },
  9328. { "src", 69 /* xt_iclass_shiftst */,
  9329. 0,
  9330. Opcode_src_encode_fns, 0, 0 },
  9331. { "srl", 70 /* xt_iclass_shiftt */,
  9332. 0,
  9333. Opcode_srl_encode_fns, 0, 0 },
  9334. { "sra", 70 /* xt_iclass_shiftt */,
  9335. 0,
  9336. Opcode_sra_encode_fns, 0, 0 },
  9337. { "slli", 71 /* xt_iclass_slli */,
  9338. 0,
  9339. Opcode_slli_encode_fns, 0, 0 },
  9340. { "srai", 72 /* xt_iclass_srai */,
  9341. 0,
  9342. Opcode_srai_encode_fns, 0, 0 },
  9343. { "srli", 73 /* xt_iclass_srli */,
  9344. 0,
  9345. Opcode_srli_encode_fns, 0, 0 },
  9346. { "memw", 74 /* xt_iclass_memw */,
  9347. 0,
  9348. Opcode_memw_encode_fns, 0, 0 },
  9349. { "extw", 75 /* xt_iclass_extw */,
  9350. 0,
  9351. Opcode_extw_encode_fns, 0, 0 },
  9352. { "isync", 76 /* xt_iclass_isync */,
  9353. 0,
  9354. Opcode_isync_encode_fns, 0, 0 },
  9355. { "rsync", 77 /* xt_iclass_sync */,
  9356. 0,
  9357. Opcode_rsync_encode_fns, 0, 0 },
  9358. { "esync", 77 /* xt_iclass_sync */,
  9359. 0,
  9360. Opcode_esync_encode_fns, 0, 0 },
  9361. { "dsync", 77 /* xt_iclass_sync */,
  9362. 0,
  9363. Opcode_dsync_encode_fns, 0, 0 },
  9364. { "rsil", 78 /* xt_iclass_rsil */,
  9365. 0,
  9366. Opcode_rsil_encode_fns, 0, 0 },
  9367. { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
  9368. 0,
  9369. Opcode_rsr_lend_encode_fns, 0, 0 },
  9370. { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
  9371. 0,
  9372. Opcode_wsr_lend_encode_fns, 0, 0 },
  9373. { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
  9374. 0,
  9375. Opcode_xsr_lend_encode_fns, 0, 0 },
  9376. { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
  9377. 0,
  9378. Opcode_rsr_lcount_encode_fns, 0, 0 },
  9379. { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
  9380. 0,
  9381. Opcode_wsr_lcount_encode_fns, 0, 0 },
  9382. { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
  9383. 0,
  9384. Opcode_xsr_lcount_encode_fns, 0, 0 },
  9385. { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
  9386. 0,
  9387. Opcode_rsr_lbeg_encode_fns, 0, 0 },
  9388. { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
  9389. 0,
  9390. Opcode_wsr_lbeg_encode_fns, 0, 0 },
  9391. { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
  9392. 0,
  9393. Opcode_xsr_lbeg_encode_fns, 0, 0 },
  9394. { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
  9395. 0,
  9396. Opcode_rsr_sar_encode_fns, 0, 0 },
  9397. { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
  9398. 0,
  9399. Opcode_wsr_sar_encode_fns, 0, 0 },
  9400. { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
  9401. 0,
  9402. Opcode_xsr_sar_encode_fns, 0, 0 },
  9403. { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
  9404. 0,
  9405. Opcode_rsr_litbase_encode_fns, 0, 0 },
  9406. { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
  9407. 0,
  9408. Opcode_wsr_litbase_encode_fns, 0, 0 },
  9409. { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
  9410. 0,
  9411. Opcode_xsr_litbase_encode_fns, 0, 0 },
  9412. { "rsr.176", 94 /* xt_iclass_rsr.176 */,
  9413. 0,
  9414. Opcode_rsr_176_encode_fns, 0, 0 },
  9415. { "rsr.208", 95 /* xt_iclass_rsr.208 */,
  9416. 0,
  9417. Opcode_rsr_208_encode_fns, 0, 0 },
  9418. { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
  9419. 0,
  9420. Opcode_rsr_ps_encode_fns, 0, 0 },
  9421. { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
  9422. 0,
  9423. Opcode_wsr_ps_encode_fns, 0, 0 },
  9424. { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
  9425. 0,
  9426. Opcode_xsr_ps_encode_fns, 0, 0 },
  9427. { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
  9428. 0,
  9429. Opcode_rsr_epc1_encode_fns, 0, 0 },
  9430. { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
  9431. 0,
  9432. Opcode_wsr_epc1_encode_fns, 0, 0 },
  9433. { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
  9434. 0,
  9435. Opcode_xsr_epc1_encode_fns, 0, 0 },
  9436. { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
  9437. 0,
  9438. Opcode_rsr_excsave1_encode_fns, 0, 0 },
  9439. { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
  9440. 0,
  9441. Opcode_wsr_excsave1_encode_fns, 0, 0 },
  9442. { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
  9443. 0,
  9444. Opcode_xsr_excsave1_encode_fns, 0, 0 },
  9445. { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
  9446. 0,
  9447. Opcode_rsr_epc2_encode_fns, 0, 0 },
  9448. { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
  9449. 0,
  9450. Opcode_wsr_epc2_encode_fns, 0, 0 },
  9451. { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
  9452. 0,
  9453. Opcode_xsr_epc2_encode_fns, 0, 0 },
  9454. { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
  9455. 0,
  9456. Opcode_rsr_excsave2_encode_fns, 0, 0 },
  9457. { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
  9458. 0,
  9459. Opcode_wsr_excsave2_encode_fns, 0, 0 },
  9460. { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
  9461. 0,
  9462. Opcode_xsr_excsave2_encode_fns, 0, 0 },
  9463. { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
  9464. 0,
  9465. Opcode_rsr_epc3_encode_fns, 0, 0 },
  9466. { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
  9467. 0,
  9468. Opcode_wsr_epc3_encode_fns, 0, 0 },
  9469. { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
  9470. 0,
  9471. Opcode_xsr_epc3_encode_fns, 0, 0 },
  9472. { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
  9473. 0,
  9474. Opcode_rsr_excsave3_encode_fns, 0, 0 },
  9475. { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
  9476. 0,
  9477. Opcode_wsr_excsave3_encode_fns, 0, 0 },
  9478. { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
  9479. 0,
  9480. Opcode_xsr_excsave3_encode_fns, 0, 0 },
  9481. { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
  9482. 0,
  9483. Opcode_rsr_epc4_encode_fns, 0, 0 },
  9484. { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
  9485. 0,
  9486. Opcode_wsr_epc4_encode_fns, 0, 0 },
  9487. { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
  9488. 0,
  9489. Opcode_xsr_epc4_encode_fns, 0, 0 },
  9490. { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
  9491. 0,
  9492. Opcode_rsr_excsave4_encode_fns, 0, 0 },
  9493. { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
  9494. 0,
  9495. Opcode_wsr_excsave4_encode_fns, 0, 0 },
  9496. { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
  9497. 0,
  9498. Opcode_xsr_excsave4_encode_fns, 0, 0 },
  9499. { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
  9500. 0,
  9501. Opcode_rsr_epc5_encode_fns, 0, 0 },
  9502. { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
  9503. 0,
  9504. Opcode_wsr_epc5_encode_fns, 0, 0 },
  9505. { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
  9506. 0,
  9507. Opcode_xsr_epc5_encode_fns, 0, 0 },
  9508. { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
  9509. 0,
  9510. Opcode_rsr_excsave5_encode_fns, 0, 0 },
  9511. { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
  9512. 0,
  9513. Opcode_wsr_excsave5_encode_fns, 0, 0 },
  9514. { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
  9515. 0,
  9516. Opcode_xsr_excsave5_encode_fns, 0, 0 },
  9517. { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
  9518. 0,
  9519. Opcode_rsr_epc6_encode_fns, 0, 0 },
  9520. { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
  9521. 0,
  9522. Opcode_wsr_epc6_encode_fns, 0, 0 },
  9523. { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
  9524. 0,
  9525. Opcode_xsr_epc6_encode_fns, 0, 0 },
  9526. { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
  9527. 0,
  9528. Opcode_rsr_excsave6_encode_fns, 0, 0 },
  9529. { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
  9530. 0,
  9531. Opcode_wsr_excsave6_encode_fns, 0, 0 },
  9532. { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
  9533. 0,
  9534. Opcode_xsr_excsave6_encode_fns, 0, 0 },
  9535. { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
  9536. 0,
  9537. Opcode_rsr_epc7_encode_fns, 0, 0 },
  9538. { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
  9539. 0,
  9540. Opcode_wsr_epc7_encode_fns, 0, 0 },
  9541. { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
  9542. 0,
  9543. Opcode_xsr_epc7_encode_fns, 0, 0 },
  9544. { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
  9545. 0,
  9546. Opcode_rsr_excsave7_encode_fns, 0, 0 },
  9547. { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
  9548. 0,
  9549. Opcode_wsr_excsave7_encode_fns, 0, 0 },
  9550. { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
  9551. 0,
  9552. Opcode_xsr_excsave7_encode_fns, 0, 0 },
  9553. { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
  9554. 0,
  9555. Opcode_rsr_eps2_encode_fns, 0, 0 },
  9556. { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
  9557. 0,
  9558. Opcode_wsr_eps2_encode_fns, 0, 0 },
  9559. { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
  9560. 0,
  9561. Opcode_xsr_eps2_encode_fns, 0, 0 },
  9562. { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
  9563. 0,
  9564. Opcode_rsr_eps3_encode_fns, 0, 0 },
  9565. { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
  9566. 0,
  9567. Opcode_wsr_eps3_encode_fns, 0, 0 },
  9568. { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
  9569. 0,
  9570. Opcode_xsr_eps3_encode_fns, 0, 0 },
  9571. { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
  9572. 0,
  9573. Opcode_rsr_eps4_encode_fns, 0, 0 },
  9574. { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
  9575. 0,
  9576. Opcode_wsr_eps4_encode_fns, 0, 0 },
  9577. { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
  9578. 0,
  9579. Opcode_xsr_eps4_encode_fns, 0, 0 },
  9580. { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
  9581. 0,
  9582. Opcode_rsr_eps5_encode_fns, 0, 0 },
  9583. { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
  9584. 0,
  9585. Opcode_wsr_eps5_encode_fns, 0, 0 },
  9586. { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
  9587. 0,
  9588. Opcode_xsr_eps5_encode_fns, 0, 0 },
  9589. { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
  9590. 0,
  9591. Opcode_rsr_eps6_encode_fns, 0, 0 },
  9592. { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
  9593. 0,
  9594. Opcode_wsr_eps6_encode_fns, 0, 0 },
  9595. { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
  9596. 0,
  9597. Opcode_xsr_eps6_encode_fns, 0, 0 },
  9598. { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
  9599. 0,
  9600. Opcode_rsr_eps7_encode_fns, 0, 0 },
  9601. { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
  9602. 0,
  9603. Opcode_wsr_eps7_encode_fns, 0, 0 },
  9604. { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
  9605. 0,
  9606. Opcode_xsr_eps7_encode_fns, 0, 0 },
  9607. { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
  9608. 0,
  9609. Opcode_rsr_excvaddr_encode_fns, 0, 0 },
  9610. { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
  9611. 0,
  9612. Opcode_wsr_excvaddr_encode_fns, 0, 0 },
  9613. { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
  9614. 0,
  9615. Opcode_xsr_excvaddr_encode_fns, 0, 0 },
  9616. { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
  9617. 0,
  9618. Opcode_rsr_depc_encode_fns, 0, 0 },
  9619. { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
  9620. 0,
  9621. Opcode_wsr_depc_encode_fns, 0, 0 },
  9622. { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
  9623. 0,
  9624. Opcode_xsr_depc_encode_fns, 0, 0 },
  9625. { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
  9626. 0,
  9627. Opcode_rsr_exccause_encode_fns, 0, 0 },
  9628. { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
  9629. 0,
  9630. Opcode_wsr_exccause_encode_fns, 0, 0 },
  9631. { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
  9632. 0,
  9633. Opcode_xsr_exccause_encode_fns, 0, 0 },
  9634. { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
  9635. 0,
  9636. Opcode_rsr_misc0_encode_fns, 0, 0 },
  9637. { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
  9638. 0,
  9639. Opcode_wsr_misc0_encode_fns, 0, 0 },
  9640. { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
  9641. 0,
  9642. Opcode_xsr_misc0_encode_fns, 0, 0 },
  9643. { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
  9644. 0,
  9645. Opcode_rsr_misc1_encode_fns, 0, 0 },
  9646. { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
  9647. 0,
  9648. Opcode_wsr_misc1_encode_fns, 0, 0 },
  9649. { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
  9650. 0,
  9651. Opcode_xsr_misc1_encode_fns, 0, 0 },
  9652. { "rsr.prid", 174 /* xt_iclass_rsr.prid */,
  9653. 0,
  9654. Opcode_rsr_prid_encode_fns, 0, 0 },
  9655. { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */,
  9656. 0,
  9657. Opcode_rsr_vecbase_encode_fns, 0, 0 },
  9658. { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */,
  9659. 0,
  9660. Opcode_wsr_vecbase_encode_fns, 0, 0 },
  9661. { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */,
  9662. 0,
  9663. Opcode_xsr_vecbase_encode_fns, 0, 0 },
  9664. { "mul.aa.ll", 178 /* xt_iclass_mac16_aa */,
  9665. 0,
  9666. Opcode_mul_aa_ll_encode_fns, 0, 0 },
  9667. { "mul.aa.hl", 178 /* xt_iclass_mac16_aa */,
  9668. 0,
  9669. Opcode_mul_aa_hl_encode_fns, 0, 0 },
  9670. { "mul.aa.lh", 178 /* xt_iclass_mac16_aa */,
  9671. 0,
  9672. Opcode_mul_aa_lh_encode_fns, 0, 0 },
  9673. { "mul.aa.hh", 178 /* xt_iclass_mac16_aa */,
  9674. 0,
  9675. Opcode_mul_aa_hh_encode_fns, 0, 0 },
  9676. { "umul.aa.ll", 178 /* xt_iclass_mac16_aa */,
  9677. 0,
  9678. Opcode_umul_aa_ll_encode_fns, 0, 0 },
  9679. { "umul.aa.hl", 178 /* xt_iclass_mac16_aa */,
  9680. 0,
  9681. Opcode_umul_aa_hl_encode_fns, 0, 0 },
  9682. { "umul.aa.lh", 178 /* xt_iclass_mac16_aa */,
  9683. 0,
  9684. Opcode_umul_aa_lh_encode_fns, 0, 0 },
  9685. { "umul.aa.hh", 178 /* xt_iclass_mac16_aa */,
  9686. 0,
  9687. Opcode_umul_aa_hh_encode_fns, 0, 0 },
  9688. { "mul.ad.ll", 179 /* xt_iclass_mac16_ad */,
  9689. 0,
  9690. Opcode_mul_ad_ll_encode_fns, 0, 0 },
  9691. { "mul.ad.hl", 179 /* xt_iclass_mac16_ad */,
  9692. 0,
  9693. Opcode_mul_ad_hl_encode_fns, 0, 0 },
  9694. { "mul.ad.lh", 179 /* xt_iclass_mac16_ad */,
  9695. 0,
  9696. Opcode_mul_ad_lh_encode_fns, 0, 0 },
  9697. { "mul.ad.hh", 179 /* xt_iclass_mac16_ad */,
  9698. 0,
  9699. Opcode_mul_ad_hh_encode_fns, 0, 0 },
  9700. { "mul.da.ll", 180 /* xt_iclass_mac16_da */,
  9701. 0,
  9702. Opcode_mul_da_ll_encode_fns, 0, 0 },
  9703. { "mul.da.hl", 180 /* xt_iclass_mac16_da */,
  9704. 0,
  9705. Opcode_mul_da_hl_encode_fns, 0, 0 },
  9706. { "mul.da.lh", 180 /* xt_iclass_mac16_da */,
  9707. 0,
  9708. Opcode_mul_da_lh_encode_fns, 0, 0 },
  9709. { "mul.da.hh", 180 /* xt_iclass_mac16_da */,
  9710. 0,
  9711. Opcode_mul_da_hh_encode_fns, 0, 0 },
  9712. { "mul.dd.ll", 181 /* xt_iclass_mac16_dd */,
  9713. 0,
  9714. Opcode_mul_dd_ll_encode_fns, 0, 0 },
  9715. { "mul.dd.hl", 181 /* xt_iclass_mac16_dd */,
  9716. 0,
  9717. Opcode_mul_dd_hl_encode_fns, 0, 0 },
  9718. { "mul.dd.lh", 181 /* xt_iclass_mac16_dd */,
  9719. 0,
  9720. Opcode_mul_dd_lh_encode_fns, 0, 0 },
  9721. { "mul.dd.hh", 181 /* xt_iclass_mac16_dd */,
  9722. 0,
  9723. Opcode_mul_dd_hh_encode_fns, 0, 0 },
  9724. { "mula.aa.ll", 182 /* xt_iclass_mac16a_aa */,
  9725. 0,
  9726. Opcode_mula_aa_ll_encode_fns, 0, 0 },
  9727. { "mula.aa.hl", 182 /* xt_iclass_mac16a_aa */,
  9728. 0,
  9729. Opcode_mula_aa_hl_encode_fns, 0, 0 },
  9730. { "mula.aa.lh", 182 /* xt_iclass_mac16a_aa */,
  9731. 0,
  9732. Opcode_mula_aa_lh_encode_fns, 0, 0 },
  9733. { "mula.aa.hh", 182 /* xt_iclass_mac16a_aa */,
  9734. 0,
  9735. Opcode_mula_aa_hh_encode_fns, 0, 0 },
  9736. { "muls.aa.ll", 182 /* xt_iclass_mac16a_aa */,
  9737. 0,
  9738. Opcode_muls_aa_ll_encode_fns, 0, 0 },
  9739. { "muls.aa.hl", 182 /* xt_iclass_mac16a_aa */,
  9740. 0,
  9741. Opcode_muls_aa_hl_encode_fns, 0, 0 },
  9742. { "muls.aa.lh", 182 /* xt_iclass_mac16a_aa */,
  9743. 0,
  9744. Opcode_muls_aa_lh_encode_fns, 0, 0 },
  9745. { "muls.aa.hh", 182 /* xt_iclass_mac16a_aa */,
  9746. 0,
  9747. Opcode_muls_aa_hh_encode_fns, 0, 0 },
  9748. { "mula.ad.ll", 183 /* xt_iclass_mac16a_ad */,
  9749. 0,
  9750. Opcode_mula_ad_ll_encode_fns, 0, 0 },
  9751. { "mula.ad.hl", 183 /* xt_iclass_mac16a_ad */,
  9752. 0,
  9753. Opcode_mula_ad_hl_encode_fns, 0, 0 },
  9754. { "mula.ad.lh", 183 /* xt_iclass_mac16a_ad */,
  9755. 0,
  9756. Opcode_mula_ad_lh_encode_fns, 0, 0 },
  9757. { "mula.ad.hh", 183 /* xt_iclass_mac16a_ad */,
  9758. 0,
  9759. Opcode_mula_ad_hh_encode_fns, 0, 0 },
  9760. { "muls.ad.ll", 183 /* xt_iclass_mac16a_ad */,
  9761. 0,
  9762. Opcode_muls_ad_ll_encode_fns, 0, 0 },
  9763. { "muls.ad.hl", 183 /* xt_iclass_mac16a_ad */,
  9764. 0,
  9765. Opcode_muls_ad_hl_encode_fns, 0, 0 },
  9766. { "muls.ad.lh", 183 /* xt_iclass_mac16a_ad */,
  9767. 0,
  9768. Opcode_muls_ad_lh_encode_fns, 0, 0 },
  9769. { "muls.ad.hh", 183 /* xt_iclass_mac16a_ad */,
  9770. 0,
  9771. Opcode_muls_ad_hh_encode_fns, 0, 0 },
  9772. { "mula.da.ll", 184 /* xt_iclass_mac16a_da */,
  9773. 0,
  9774. Opcode_mula_da_ll_encode_fns, 0, 0 },
  9775. { "mula.da.hl", 184 /* xt_iclass_mac16a_da */,
  9776. 0,
  9777. Opcode_mula_da_hl_encode_fns, 0, 0 },
  9778. { "mula.da.lh", 184 /* xt_iclass_mac16a_da */,
  9779. 0,
  9780. Opcode_mula_da_lh_encode_fns, 0, 0 },
  9781. { "mula.da.hh", 184 /* xt_iclass_mac16a_da */,
  9782. 0,
  9783. Opcode_mula_da_hh_encode_fns, 0, 0 },
  9784. { "muls.da.ll", 184 /* xt_iclass_mac16a_da */,
  9785. 0,
  9786. Opcode_muls_da_ll_encode_fns, 0, 0 },
  9787. { "muls.da.hl", 184 /* xt_iclass_mac16a_da */,
  9788. 0,
  9789. Opcode_muls_da_hl_encode_fns, 0, 0 },
  9790. { "muls.da.lh", 184 /* xt_iclass_mac16a_da */,
  9791. 0,
  9792. Opcode_muls_da_lh_encode_fns, 0, 0 },
  9793. { "muls.da.hh", 184 /* xt_iclass_mac16a_da */,
  9794. 0,
  9795. Opcode_muls_da_hh_encode_fns, 0, 0 },
  9796. { "mula.dd.ll", 185 /* xt_iclass_mac16a_dd */,
  9797. 0,
  9798. Opcode_mula_dd_ll_encode_fns, 0, 0 },
  9799. { "mula.dd.hl", 185 /* xt_iclass_mac16a_dd */,
  9800. 0,
  9801. Opcode_mula_dd_hl_encode_fns, 0, 0 },
  9802. { "mula.dd.lh", 185 /* xt_iclass_mac16a_dd */,
  9803. 0,
  9804. Opcode_mula_dd_lh_encode_fns, 0, 0 },
  9805. { "mula.dd.hh", 185 /* xt_iclass_mac16a_dd */,
  9806. 0,
  9807. Opcode_mula_dd_hh_encode_fns, 0, 0 },
  9808. { "muls.dd.ll", 185 /* xt_iclass_mac16a_dd */,
  9809. 0,
  9810. Opcode_muls_dd_ll_encode_fns, 0, 0 },
  9811. { "muls.dd.hl", 185 /* xt_iclass_mac16a_dd */,
  9812. 0,
  9813. Opcode_muls_dd_hl_encode_fns, 0, 0 },
  9814. { "muls.dd.lh", 185 /* xt_iclass_mac16a_dd */,
  9815. 0,
  9816. Opcode_muls_dd_lh_encode_fns, 0, 0 },
  9817. { "muls.dd.hh", 185 /* xt_iclass_mac16a_dd */,
  9818. 0,
  9819. Opcode_muls_dd_hh_encode_fns, 0, 0 },
  9820. { "mula.da.ll.lddec", 186 /* xt_iclass_mac16al_da */,
  9821. 0,
  9822. Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
  9823. { "mula.da.ll.ldinc", 186 /* xt_iclass_mac16al_da */,
  9824. 0,
  9825. Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
  9826. { "mula.da.hl.lddec", 186 /* xt_iclass_mac16al_da */,
  9827. 0,
  9828. Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
  9829. { "mula.da.hl.ldinc", 186 /* xt_iclass_mac16al_da */,
  9830. 0,
  9831. Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
  9832. { "mula.da.lh.lddec", 186 /* xt_iclass_mac16al_da */,
  9833. 0,
  9834. Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
  9835. { "mula.da.lh.ldinc", 186 /* xt_iclass_mac16al_da */,
  9836. 0,
  9837. Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
  9838. { "mula.da.hh.lddec", 186 /* xt_iclass_mac16al_da */,
  9839. 0,
  9840. Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
  9841. { "mula.da.hh.ldinc", 186 /* xt_iclass_mac16al_da */,
  9842. 0,
  9843. Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
  9844. { "mula.dd.ll.lddec", 187 /* xt_iclass_mac16al_dd */,
  9845. 0,
  9846. Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
  9847. { "mula.dd.ll.ldinc", 187 /* xt_iclass_mac16al_dd */,
  9848. 0,
  9849. Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
  9850. { "mula.dd.hl.lddec", 187 /* xt_iclass_mac16al_dd */,
  9851. 0,
  9852. Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
  9853. { "mula.dd.hl.ldinc", 187 /* xt_iclass_mac16al_dd */,
  9854. 0,
  9855. Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
  9856. { "mula.dd.lh.lddec", 187 /* xt_iclass_mac16al_dd */,
  9857. 0,
  9858. Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
  9859. { "mula.dd.lh.ldinc", 187 /* xt_iclass_mac16al_dd */,
  9860. 0,
  9861. Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
  9862. { "mula.dd.hh.lddec", 187 /* xt_iclass_mac16al_dd */,
  9863. 0,
  9864. Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
  9865. { "mula.dd.hh.ldinc", 187 /* xt_iclass_mac16al_dd */,
  9866. 0,
  9867. Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
  9868. { "lddec", 188 /* xt_iclass_mac16_l */,
  9869. 0,
  9870. Opcode_lddec_encode_fns, 0, 0 },
  9871. { "ldinc", 188 /* xt_iclass_mac16_l */,
  9872. 0,
  9873. Opcode_ldinc_encode_fns, 0, 0 },
  9874. { "mul16u", 189 /* xt_iclass_mul16 */,
  9875. 0,
  9876. Opcode_mul16u_encode_fns, 0, 0 },
  9877. { "mul16s", 189 /* xt_iclass_mul16 */,
  9878. 0,
  9879. Opcode_mul16s_encode_fns, 0, 0 },
  9880. { "rsr.m0", 190 /* xt_iclass_rsr.m0 */,
  9881. 0,
  9882. Opcode_rsr_m0_encode_fns, 0, 0 },
  9883. { "wsr.m0", 191 /* xt_iclass_wsr.m0 */,
  9884. 0,
  9885. Opcode_wsr_m0_encode_fns, 0, 0 },
  9886. { "xsr.m0", 192 /* xt_iclass_xsr.m0 */,
  9887. 0,
  9888. Opcode_xsr_m0_encode_fns, 0, 0 },
  9889. { "rsr.m1", 193 /* xt_iclass_rsr.m1 */,
  9890. 0,
  9891. Opcode_rsr_m1_encode_fns, 0, 0 },
  9892. { "wsr.m1", 194 /* xt_iclass_wsr.m1 */,
  9893. 0,
  9894. Opcode_wsr_m1_encode_fns, 0, 0 },
  9895. { "xsr.m1", 195 /* xt_iclass_xsr.m1 */,
  9896. 0,
  9897. Opcode_xsr_m1_encode_fns, 0, 0 },
  9898. { "rsr.m2", 196 /* xt_iclass_rsr.m2 */,
  9899. 0,
  9900. Opcode_rsr_m2_encode_fns, 0, 0 },
  9901. { "wsr.m2", 197 /* xt_iclass_wsr.m2 */,
  9902. 0,
  9903. Opcode_wsr_m2_encode_fns, 0, 0 },
  9904. { "xsr.m2", 198 /* xt_iclass_xsr.m2 */,
  9905. 0,
  9906. Opcode_xsr_m2_encode_fns, 0, 0 },
  9907. { "rsr.m3", 199 /* xt_iclass_rsr.m3 */,
  9908. 0,
  9909. Opcode_rsr_m3_encode_fns, 0, 0 },
  9910. { "wsr.m3", 200 /* xt_iclass_wsr.m3 */,
  9911. 0,
  9912. Opcode_wsr_m3_encode_fns, 0, 0 },
  9913. { "xsr.m3", 201 /* xt_iclass_xsr.m3 */,
  9914. 0,
  9915. Opcode_xsr_m3_encode_fns, 0, 0 },
  9916. { "rsr.acclo", 202 /* xt_iclass_rsr.acclo */,
  9917. 0,
  9918. Opcode_rsr_acclo_encode_fns, 0, 0 },
  9919. { "wsr.acclo", 203 /* xt_iclass_wsr.acclo */,
  9920. 0,
  9921. Opcode_wsr_acclo_encode_fns, 0, 0 },
  9922. { "xsr.acclo", 204 /* xt_iclass_xsr.acclo */,
  9923. 0,
  9924. Opcode_xsr_acclo_encode_fns, 0, 0 },
  9925. { "rsr.acchi", 205 /* xt_iclass_rsr.acchi */,
  9926. 0,
  9927. Opcode_rsr_acchi_encode_fns, 0, 0 },
  9928. { "wsr.acchi", 206 /* xt_iclass_wsr.acchi */,
  9929. 0,
  9930. Opcode_wsr_acchi_encode_fns, 0, 0 },
  9931. { "xsr.acchi", 207 /* xt_iclass_xsr.acchi */,
  9932. 0,
  9933. Opcode_xsr_acchi_encode_fns, 0, 0 },
  9934. { "rfi", 208 /* xt_iclass_rfi */,
  9935. XTENSA_OPCODE_IS_JUMP,
  9936. Opcode_rfi_encode_fns, 0, 0 },
  9937. { "waiti", 209 /* xt_iclass_wait */,
  9938. 0,
  9939. Opcode_waiti_encode_fns, 0, 0 },
  9940. { "rsr.interrupt", 210 /* xt_iclass_rsr.interrupt */,
  9941. 0,
  9942. Opcode_rsr_interrupt_encode_fns, 0, 0 },
  9943. { "wsr.intset", 211 /* xt_iclass_wsr.intset */,
  9944. 0,
  9945. Opcode_wsr_intset_encode_fns, 0, 0 },
  9946. { "wsr.intclear", 212 /* xt_iclass_wsr.intclear */,
  9947. 0,
  9948. Opcode_wsr_intclear_encode_fns, 0, 0 },
  9949. { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */,
  9950. 0,
  9951. Opcode_rsr_intenable_encode_fns, 0, 0 },
  9952. { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */,
  9953. 0,
  9954. Opcode_wsr_intenable_encode_fns, 0, 0 },
  9955. { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */,
  9956. 0,
  9957. Opcode_xsr_intenable_encode_fns, 0, 0 },
  9958. { "break", 216 /* xt_iclass_break */,
  9959. 0,
  9960. Opcode_break_encode_fns, 0, 0 },
  9961. { "break.n", 217 /* xt_iclass_break.n */,
  9962. 0,
  9963. Opcode_break_n_encode_fns, 0, 0 },
  9964. { "rsr.dbreaka0", 218 /* xt_iclass_rsr.dbreaka0 */,
  9965. 0,
  9966. Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
  9967. { "wsr.dbreaka0", 219 /* xt_iclass_wsr.dbreaka0 */,
  9968. 0,
  9969. Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
  9970. { "xsr.dbreaka0", 220 /* xt_iclass_xsr.dbreaka0 */,
  9971. 0,
  9972. Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
  9973. { "rsr.dbreakc0", 221 /* xt_iclass_rsr.dbreakc0 */,
  9974. 0,
  9975. Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
  9976. { "wsr.dbreakc0", 222 /* xt_iclass_wsr.dbreakc0 */,
  9977. 0,
  9978. Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
  9979. { "xsr.dbreakc0", 223 /* xt_iclass_xsr.dbreakc0 */,
  9980. 0,
  9981. Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
  9982. { "rsr.dbreaka1", 224 /* xt_iclass_rsr.dbreaka1 */,
  9983. 0,
  9984. Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
  9985. { "wsr.dbreaka1", 225 /* xt_iclass_wsr.dbreaka1 */,
  9986. 0,
  9987. Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
  9988. { "xsr.dbreaka1", 226 /* xt_iclass_xsr.dbreaka1 */,
  9989. 0,
  9990. Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
  9991. { "rsr.dbreakc1", 227 /* xt_iclass_rsr.dbreakc1 */,
  9992. 0,
  9993. Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
  9994. { "wsr.dbreakc1", 228 /* xt_iclass_wsr.dbreakc1 */,
  9995. 0,
  9996. Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
  9997. { "xsr.dbreakc1", 229 /* xt_iclass_xsr.dbreakc1 */,
  9998. 0,
  9999. Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
  10000. { "rsr.ibreaka0", 230 /* xt_iclass_rsr.ibreaka0 */,
  10001. 0,
  10002. Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
  10003. { "wsr.ibreaka0", 231 /* xt_iclass_wsr.ibreaka0 */,
  10004. 0,
  10005. Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
  10006. { "xsr.ibreaka0", 232 /* xt_iclass_xsr.ibreaka0 */,
  10007. 0,
  10008. Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
  10009. { "rsr.ibreaka1", 233 /* xt_iclass_rsr.ibreaka1 */,
  10010. 0,
  10011. Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
  10012. { "wsr.ibreaka1", 234 /* xt_iclass_wsr.ibreaka1 */,
  10013. 0,
  10014. Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
  10015. { "xsr.ibreaka1", 235 /* xt_iclass_xsr.ibreaka1 */,
  10016. 0,
  10017. Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
  10018. { "rsr.ibreakenable", 236 /* xt_iclass_rsr.ibreakenable */,
  10019. 0,
  10020. Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
  10021. { "wsr.ibreakenable", 237 /* xt_iclass_wsr.ibreakenable */,
  10022. 0,
  10023. Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
  10024. { "xsr.ibreakenable", 238 /* xt_iclass_xsr.ibreakenable */,
  10025. 0,
  10026. Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
  10027. { "rsr.debugcause", 239 /* xt_iclass_rsr.debugcause */,
  10028. 0,
  10029. Opcode_rsr_debugcause_encode_fns, 0, 0 },
  10030. { "wsr.debugcause", 240 /* xt_iclass_wsr.debugcause */,
  10031. 0,
  10032. Opcode_wsr_debugcause_encode_fns, 0, 0 },
  10033. { "xsr.debugcause", 241 /* xt_iclass_xsr.debugcause */,
  10034. 0,
  10035. Opcode_xsr_debugcause_encode_fns, 0, 0 },
  10036. { "rsr.icount", 242 /* xt_iclass_rsr.icount */,
  10037. 0,
  10038. Opcode_rsr_icount_encode_fns, 0, 0 },
  10039. { "wsr.icount", 243 /* xt_iclass_wsr.icount */,
  10040. 0,
  10041. Opcode_wsr_icount_encode_fns, 0, 0 },
  10042. { "xsr.icount", 244 /* xt_iclass_xsr.icount */,
  10043. 0,
  10044. Opcode_xsr_icount_encode_fns, 0, 0 },
  10045. { "rsr.icountlevel", 245 /* xt_iclass_rsr.icountlevel */,
  10046. 0,
  10047. Opcode_rsr_icountlevel_encode_fns, 0, 0 },
  10048. { "wsr.icountlevel", 246 /* xt_iclass_wsr.icountlevel */,
  10049. 0,
  10050. Opcode_wsr_icountlevel_encode_fns, 0, 0 },
  10051. { "xsr.icountlevel", 247 /* xt_iclass_xsr.icountlevel */,
  10052. 0,
  10053. Opcode_xsr_icountlevel_encode_fns, 0, 0 },
  10054. { "rsr.ddr", 248 /* xt_iclass_rsr.ddr */,
  10055. 0,
  10056. Opcode_rsr_ddr_encode_fns, 0, 0 },
  10057. { "wsr.ddr", 249 /* xt_iclass_wsr.ddr */,
  10058. 0,
  10059. Opcode_wsr_ddr_encode_fns, 0, 0 },
  10060. { "xsr.ddr", 250 /* xt_iclass_xsr.ddr */,
  10061. 0,
  10062. Opcode_xsr_ddr_encode_fns, 0, 0 },
  10063. { "rfdo", 251 /* xt_iclass_rfdo */,
  10064. XTENSA_OPCODE_IS_JUMP,
  10065. Opcode_rfdo_encode_fns, 0, 0 },
  10066. { "rfdd", 252 /* xt_iclass_rfdd */,
  10067. XTENSA_OPCODE_IS_JUMP,
  10068. Opcode_rfdd_encode_fns, 0, 0 },
  10069. { "wsr.mmid", 253 /* xt_iclass_wsr.mmid */,
  10070. 0,
  10071. Opcode_wsr_mmid_encode_fns, 0, 0 },
  10072. { "rsr.ccount", 254 /* xt_iclass_rsr.ccount */,
  10073. 0,
  10074. Opcode_rsr_ccount_encode_fns, 0, 0 },
  10075. { "wsr.ccount", 255 /* xt_iclass_wsr.ccount */,
  10076. 0,
  10077. Opcode_wsr_ccount_encode_fns, 0, 0 },
  10078. { "xsr.ccount", 256 /* xt_iclass_xsr.ccount */,
  10079. 0,
  10080. Opcode_xsr_ccount_encode_fns, 0, 0 },
  10081. { "rsr.ccompare0", 257 /* xt_iclass_rsr.ccompare0 */,
  10082. 0,
  10083. Opcode_rsr_ccompare0_encode_fns, 0, 0 },
  10084. { "wsr.ccompare0", 258 /* xt_iclass_wsr.ccompare0 */,
  10085. 0,
  10086. Opcode_wsr_ccompare0_encode_fns, 0, 0 },
  10087. { "xsr.ccompare0", 259 /* xt_iclass_xsr.ccompare0 */,
  10088. 0,
  10089. Opcode_xsr_ccompare0_encode_fns, 0, 0 },
  10090. { "rsr.ccompare1", 260 /* xt_iclass_rsr.ccompare1 */,
  10091. 0,
  10092. Opcode_rsr_ccompare1_encode_fns, 0, 0 },
  10093. { "wsr.ccompare1", 261 /* xt_iclass_wsr.ccompare1 */,
  10094. 0,
  10095. Opcode_wsr_ccompare1_encode_fns, 0, 0 },
  10096. { "xsr.ccompare1", 262 /* xt_iclass_xsr.ccompare1 */,
  10097. 0,
  10098. Opcode_xsr_ccompare1_encode_fns, 0, 0 },
  10099. { "rsr.ccompare2", 263 /* xt_iclass_rsr.ccompare2 */,
  10100. 0,
  10101. Opcode_rsr_ccompare2_encode_fns, 0, 0 },
  10102. { "wsr.ccompare2", 264 /* xt_iclass_wsr.ccompare2 */,
  10103. 0,
  10104. Opcode_wsr_ccompare2_encode_fns, 0, 0 },
  10105. { "xsr.ccompare2", 265 /* xt_iclass_xsr.ccompare2 */,
  10106. 0,
  10107. Opcode_xsr_ccompare2_encode_fns, 0, 0 },
  10108. { "ipf", 266 /* xt_iclass_icache */,
  10109. 0,
  10110. Opcode_ipf_encode_fns, 0, 0 },
  10111. { "ihi", 266 /* xt_iclass_icache */,
  10112. 0,
  10113. Opcode_ihi_encode_fns, 0, 0 },
  10114. { "ipfl", 267 /* xt_iclass_icache_lock */,
  10115. 0,
  10116. Opcode_ipfl_encode_fns, 0, 0 },
  10117. { "ihu", 267 /* xt_iclass_icache_lock */,
  10118. 0,
  10119. Opcode_ihu_encode_fns, 0, 0 },
  10120. { "iiu", 267 /* xt_iclass_icache_lock */,
  10121. 0,
  10122. Opcode_iiu_encode_fns, 0, 0 },
  10123. { "iii", 268 /* xt_iclass_icache_inv */,
  10124. 0,
  10125. Opcode_iii_encode_fns, 0, 0 },
  10126. { "lict", 269 /* xt_iclass_licx */,
  10127. 0,
  10128. Opcode_lict_encode_fns, 0, 0 },
  10129. { "licw", 269 /* xt_iclass_licx */,
  10130. 0,
  10131. Opcode_licw_encode_fns, 0, 0 },
  10132. { "sict", 270 /* xt_iclass_sicx */,
  10133. 0,
  10134. Opcode_sict_encode_fns, 0, 0 },
  10135. { "sicw", 270 /* xt_iclass_sicx */,
  10136. 0,
  10137. Opcode_sicw_encode_fns, 0, 0 },
  10138. { "dhwb", 271 /* xt_iclass_dcache */,
  10139. 0,
  10140. Opcode_dhwb_encode_fns, 0, 0 },
  10141. { "dhwbi", 271 /* xt_iclass_dcache */,
  10142. 0,
  10143. Opcode_dhwbi_encode_fns, 0, 0 },
  10144. { "diwb", 272 /* xt_iclass_dcache_ind */,
  10145. 0,
  10146. Opcode_diwb_encode_fns, 0, 0 },
  10147. { "diwbi", 272 /* xt_iclass_dcache_ind */,
  10148. 0,
  10149. Opcode_diwbi_encode_fns, 0, 0 },
  10150. { "dhi", 273 /* xt_iclass_dcache_inv */,
  10151. 0,
  10152. Opcode_dhi_encode_fns, 0, 0 },
  10153. { "dii", 273 /* xt_iclass_dcache_inv */,
  10154. 0,
  10155. Opcode_dii_encode_fns, 0, 0 },
  10156. { "dpfr", 274 /* xt_iclass_dpf */,
  10157. 0,
  10158. Opcode_dpfr_encode_fns, 0, 0 },
  10159. { "dpfw", 274 /* xt_iclass_dpf */,
  10160. 0,
  10161. Opcode_dpfw_encode_fns, 0, 0 },
  10162. { "dpfro", 274 /* xt_iclass_dpf */,
  10163. 0,
  10164. Opcode_dpfro_encode_fns, 0, 0 },
  10165. { "dpfwo", 274 /* xt_iclass_dpf */,
  10166. 0,
  10167. Opcode_dpfwo_encode_fns, 0, 0 },
  10168. { "dpfl", 275 /* xt_iclass_dcache_lock */,
  10169. 0,
  10170. Opcode_dpfl_encode_fns, 0, 0 },
  10171. { "dhu", 275 /* xt_iclass_dcache_lock */,
  10172. 0,
  10173. Opcode_dhu_encode_fns, 0, 0 },
  10174. { "diu", 275 /* xt_iclass_dcache_lock */,
  10175. 0,
  10176. Opcode_diu_encode_fns, 0, 0 },
  10177. { "sdct", 276 /* xt_iclass_sdct */,
  10178. 0,
  10179. Opcode_sdct_encode_fns, 0, 0 },
  10180. { "ldct", 277 /* xt_iclass_ldct */,
  10181. 0,
  10182. Opcode_ldct_encode_fns, 0, 0 },
  10183. { "wsr.ptevaddr", 278 /* xt_iclass_wsr.ptevaddr */,
  10184. 0,
  10185. Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
  10186. { "rsr.ptevaddr", 279 /* xt_iclass_rsr.ptevaddr */,
  10187. 0,
  10188. Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
  10189. { "xsr.ptevaddr", 280 /* xt_iclass_xsr.ptevaddr */,
  10190. 0,
  10191. Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
  10192. { "rsr.rasid", 281 /* xt_iclass_rsr.rasid */,
  10193. 0,
  10194. Opcode_rsr_rasid_encode_fns, 0, 0 },
  10195. { "wsr.rasid", 282 /* xt_iclass_wsr.rasid */,
  10196. 0,
  10197. Opcode_wsr_rasid_encode_fns, 0, 0 },
  10198. { "xsr.rasid", 283 /* xt_iclass_xsr.rasid */,
  10199. 0,
  10200. Opcode_xsr_rasid_encode_fns, 0, 0 },
  10201. { "rsr.itlbcfg", 284 /* xt_iclass_rsr.itlbcfg */,
  10202. 0,
  10203. Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
  10204. { "wsr.itlbcfg", 285 /* xt_iclass_wsr.itlbcfg */,
  10205. 0,
  10206. Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
  10207. { "xsr.itlbcfg", 286 /* xt_iclass_xsr.itlbcfg */,
  10208. 0,
  10209. Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
  10210. { "rsr.dtlbcfg", 287 /* xt_iclass_rsr.dtlbcfg */,
  10211. 0,
  10212. Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
  10213. { "wsr.dtlbcfg", 288 /* xt_iclass_wsr.dtlbcfg */,
  10214. 0,
  10215. Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
  10216. { "xsr.dtlbcfg", 289 /* xt_iclass_xsr.dtlbcfg */,
  10217. 0,
  10218. Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
  10219. { "idtlb", 290 /* xt_iclass_idtlb */,
  10220. 0,
  10221. Opcode_idtlb_encode_fns, 0, 0 },
  10222. { "pdtlb", 291 /* xt_iclass_rdtlb */,
  10223. 0,
  10224. Opcode_pdtlb_encode_fns, 0, 0 },
  10225. { "rdtlb0", 291 /* xt_iclass_rdtlb */,
  10226. 0,
  10227. Opcode_rdtlb0_encode_fns, 0, 0 },
  10228. { "rdtlb1", 291 /* xt_iclass_rdtlb */,
  10229. 0,
  10230. Opcode_rdtlb1_encode_fns, 0, 0 },
  10231. { "wdtlb", 292 /* xt_iclass_wdtlb */,
  10232. 0,
  10233. Opcode_wdtlb_encode_fns, 0, 0 },
  10234. { "iitlb", 293 /* xt_iclass_iitlb */,
  10235. 0,
  10236. Opcode_iitlb_encode_fns, 0, 0 },
  10237. { "pitlb", 294 /* xt_iclass_ritlb */,
  10238. 0,
  10239. Opcode_pitlb_encode_fns, 0, 0 },
  10240. { "ritlb0", 294 /* xt_iclass_ritlb */,
  10241. 0,
  10242. Opcode_ritlb0_encode_fns, 0, 0 },
  10243. { "ritlb1", 294 /* xt_iclass_ritlb */,
  10244. 0,
  10245. Opcode_ritlb1_encode_fns, 0, 0 },
  10246. { "witlb", 295 /* xt_iclass_witlb */,
  10247. 0,
  10248. Opcode_witlb_encode_fns, 0, 0 },
  10249. { "ldpte", 296 /* xt_iclass_ldpte */,
  10250. 0,
  10251. Opcode_ldpte_encode_fns, 0, 0 },
  10252. { "hwwitlba", 297 /* xt_iclass_hwwitlba */,
  10253. XTENSA_OPCODE_IS_BRANCH,
  10254. Opcode_hwwitlba_encode_fns, 0, 0 },
  10255. { "hwwdtlba", 298 /* xt_iclass_hwwdtlba */,
  10256. 0,
  10257. Opcode_hwwdtlba_encode_fns, 0, 0 },
  10258. { "rsr.cpenable", 299 /* xt_iclass_rsr.cpenable */,
  10259. 0,
  10260. Opcode_rsr_cpenable_encode_fns, 0, 0 },
  10261. { "wsr.cpenable", 300 /* xt_iclass_wsr.cpenable */,
  10262. 0,
  10263. Opcode_wsr_cpenable_encode_fns, 0, 0 },
  10264. { "xsr.cpenable", 301 /* xt_iclass_xsr.cpenable */,
  10265. 0,
  10266. Opcode_xsr_cpenable_encode_fns, 0, 0 },
  10267. { "clamps", 302 /* xt_iclass_clamp */,
  10268. 0,
  10269. Opcode_clamps_encode_fns, 0, 0 },
  10270. { "min", 303 /* xt_iclass_minmax */,
  10271. 0,
  10272. Opcode_min_encode_fns, 0, 0 },
  10273. { "max", 303 /* xt_iclass_minmax */,
  10274. 0,
  10275. Opcode_max_encode_fns, 0, 0 },
  10276. { "minu", 303 /* xt_iclass_minmax */,
  10277. 0,
  10278. Opcode_minu_encode_fns, 0, 0 },
  10279. { "maxu", 303 /* xt_iclass_minmax */,
  10280. 0,
  10281. Opcode_maxu_encode_fns, 0, 0 },
  10282. { "nsa", 304 /* xt_iclass_nsa */,
  10283. 0,
  10284. Opcode_nsa_encode_fns, 0, 0 },
  10285. { "nsau", 304 /* xt_iclass_nsa */,
  10286. 0,
  10287. Opcode_nsau_encode_fns, 0, 0 },
  10288. { "sext", 305 /* xt_iclass_sx */,
  10289. 0,
  10290. Opcode_sext_encode_fns, 0, 0 },
  10291. { "l32ai", 306 /* xt_iclass_l32ai */,
  10292. 0,
  10293. Opcode_l32ai_encode_fns, 0, 0 },
  10294. { "s32ri", 307 /* xt_iclass_s32ri */,
  10295. 0,
  10296. Opcode_s32ri_encode_fns, 0, 0 },
  10297. { "s32c1i", 308 /* xt_iclass_s32c1i */,
  10298. 0,
  10299. Opcode_s32c1i_encode_fns, 0, 0 },
  10300. { "rsr.scompare1", 309 /* xt_iclass_rsr.scompare1 */,
  10301. 0,
  10302. Opcode_rsr_scompare1_encode_fns, 0, 0 },
  10303. { "wsr.scompare1", 310 /* xt_iclass_wsr.scompare1 */,
  10304. 0,
  10305. Opcode_wsr_scompare1_encode_fns, 0, 0 },
  10306. { "xsr.scompare1", 311 /* xt_iclass_xsr.scompare1 */,
  10307. 0,
  10308. Opcode_xsr_scompare1_encode_fns, 0, 0 },
  10309. { "quou", 312 /* xt_iclass_div */,
  10310. 0,
  10311. Opcode_quou_encode_fns, 0, 0 },
  10312. { "quos", 312 /* xt_iclass_div */,
  10313. 0,
  10314. Opcode_quos_encode_fns, 0, 0 },
  10315. { "remu", 312 /* xt_iclass_div */,
  10316. 0,
  10317. Opcode_remu_encode_fns, 0, 0 },
  10318. { "rems", 312 /* xt_iclass_div */,
  10319. 0,
  10320. Opcode_rems_encode_fns, 0, 0 },
  10321. { "mull", 313 /* xt_mul32 */,
  10322. 0,
  10323. Opcode_mull_encode_fns, 0, 0 },
  10324. { "rur.expstate", 314 /* rur_expstate */,
  10325. 0,
  10326. Opcode_rur_expstate_encode_fns, 0, 0 },
  10327. { "wur.expstate", 315 /* wur_expstate */,
  10328. 0,
  10329. Opcode_wur_expstate_encode_fns, 0, 0 },
  10330. { "read_impwire", 316 /* iclass_READ_IMPWIRE */,
  10331. 0,
  10332. Opcode_read_impwire_encode_fns, 0, 0 },
  10333. { "setb_expstate", 317 /* iclass_SETB_EXPSTATE */,
  10334. 0,
  10335. Opcode_setb_expstate_encode_fns, 0, 0 },
  10336. { "clrb_expstate", 318 /* iclass_CLRB_EXPSTATE */,
  10337. 0,
  10338. Opcode_clrb_expstate_encode_fns, 0, 0 },
  10339. { "wrmsk_expstate", 319 /* iclass_WRMSK_EXPSTATE */,
  10340. 0,
  10341. Opcode_wrmsk_expstate_encode_fns, 0, 0 }
  10342. };
  10343. /* Slot-specific opcode decode functions. */
  10344. static int
  10345. Slot_inst_decode (const xtensa_insnbuf insn)
  10346. {
  10347. switch (Field_op0_Slot_inst_get (insn))
  10348. {
  10349. case 0:
  10350. switch (Field_op1_Slot_inst_get (insn))
  10351. {
  10352. case 0:
  10353. switch (Field_op2_Slot_inst_get (insn))
  10354. {
  10355. case 0:
  10356. switch (Field_r_Slot_inst_get (insn))
  10357. {
  10358. case 0:
  10359. switch (Field_m_Slot_inst_get (insn))
  10360. {
  10361. case 0:
  10362. if (Field_s_Slot_inst_get (insn) == 0 &&
  10363. Field_n_Slot_inst_get (insn) == 0)
  10364. return 79; /* ill */
  10365. break;
  10366. case 2:
  10367. switch (Field_n_Slot_inst_get (insn))
  10368. {
  10369. case 0:
  10370. return 98; /* ret */
  10371. case 1:
  10372. return 14; /* retw */
  10373. case 2:
  10374. return 81; /* jx */
  10375. }
  10376. break;
  10377. case 3:
  10378. switch (Field_n_Slot_inst_get (insn))
  10379. {
  10380. case 0:
  10381. return 77; /* callx0 */
  10382. case 1:
  10383. return 10; /* callx4 */
  10384. case 2:
  10385. return 9; /* callx8 */
  10386. case 3:
  10387. return 8; /* callx12 */
  10388. }
  10389. break;
  10390. }
  10391. break;
  10392. case 1:
  10393. return 12; /* movsp */
  10394. case 2:
  10395. if (Field_s_Slot_inst_get (insn) == 0)
  10396. {
  10397. switch (Field_t_Slot_inst_get (insn))
  10398. {
  10399. case 0:
  10400. return 116; /* isync */
  10401. case 1:
  10402. return 117; /* rsync */
  10403. case 2:
  10404. return 118; /* esync */
  10405. case 3:
  10406. return 119; /* dsync */
  10407. case 8:
  10408. return 0; /* excw */
  10409. case 12:
  10410. return 114; /* memw */
  10411. case 13:
  10412. return 115; /* extw */
  10413. case 15:
  10414. return 97; /* nop */
  10415. }
  10416. }
  10417. break;
  10418. case 3:
  10419. switch (Field_t_Slot_inst_get (insn))
  10420. {
  10421. case 0:
  10422. switch (Field_s_Slot_inst_get (insn))
  10423. {
  10424. case 0:
  10425. return 1; /* rfe */
  10426. case 2:
  10427. return 2; /* rfde */
  10428. case 4:
  10429. return 16; /* rfwo */
  10430. case 5:
  10431. return 17; /* rfwu */
  10432. }
  10433. break;
  10434. case 1:
  10435. return 310; /* rfi */
  10436. }
  10437. break;
  10438. case 4:
  10439. return 318; /* break */
  10440. case 5:
  10441. switch (Field_s_Slot_inst_get (insn))
  10442. {
  10443. case 0:
  10444. if (Field_t_Slot_inst_get (insn) == 0)
  10445. return 3; /* syscall */
  10446. break;
  10447. case 1:
  10448. if (Field_t_Slot_inst_get (insn) == 0)
  10449. return 4; /* simcall */
  10450. break;
  10451. }
  10452. break;
  10453. case 6:
  10454. return 120; /* rsil */
  10455. case 7:
  10456. if (Field_t_Slot_inst_get (insn) == 0)
  10457. return 311; /* waiti */
  10458. break;
  10459. }
  10460. break;
  10461. case 1:
  10462. return 49; /* and */
  10463. case 2:
  10464. return 50; /* or */
  10465. case 3:
  10466. return 51; /* xor */
  10467. case 4:
  10468. switch (Field_r_Slot_inst_get (insn))
  10469. {
  10470. case 0:
  10471. if (Field_t_Slot_inst_get (insn) == 0)
  10472. return 102; /* ssr */
  10473. break;
  10474. case 1:
  10475. if (Field_t_Slot_inst_get (insn) == 0)
  10476. return 103; /* ssl */
  10477. break;
  10478. case 2:
  10479. if (Field_t_Slot_inst_get (insn) == 0)
  10480. return 104; /* ssa8l */
  10481. break;
  10482. case 3:
  10483. if (Field_t_Slot_inst_get (insn) == 0)
  10484. return 105; /* ssa8b */
  10485. break;
  10486. case 4:
  10487. if (Field_thi3_Slot_inst_get (insn) == 0)
  10488. return 106; /* ssai */
  10489. break;
  10490. case 8:
  10491. if (Field_s_Slot_inst_get (insn) == 0)
  10492. return 13; /* rotw */
  10493. break;
  10494. case 14:
  10495. return 426; /* nsa */
  10496. case 15:
  10497. return 427; /* nsau */
  10498. }
  10499. break;
  10500. case 5:
  10501. switch (Field_r_Slot_inst_get (insn))
  10502. {
  10503. case 1:
  10504. return 416; /* hwwitlba */
  10505. case 3:
  10506. return 412; /* ritlb0 */
  10507. case 4:
  10508. if (Field_t_Slot_inst_get (insn) == 0)
  10509. return 410; /* iitlb */
  10510. break;
  10511. case 5:
  10512. return 411; /* pitlb */
  10513. case 6:
  10514. return 414; /* witlb */
  10515. case 7:
  10516. return 413; /* ritlb1 */
  10517. case 9:
  10518. return 417; /* hwwdtlba */
  10519. case 11:
  10520. return 407; /* rdtlb0 */
  10521. case 12:
  10522. if (Field_t_Slot_inst_get (insn) == 0)
  10523. return 405; /* idtlb */
  10524. break;
  10525. case 13:
  10526. return 406; /* pdtlb */
  10527. case 14:
  10528. return 409; /* wdtlb */
  10529. case 15:
  10530. return 408; /* rdtlb1 */
  10531. }
  10532. break;
  10533. case 6:
  10534. switch (Field_s_Slot_inst_get (insn))
  10535. {
  10536. case 0:
  10537. return 95; /* neg */
  10538. case 1:
  10539. return 96; /* abs */
  10540. }
  10541. break;
  10542. case 8:
  10543. return 41; /* add */
  10544. case 9:
  10545. return 43; /* addx2 */
  10546. case 10:
  10547. return 44; /* addx4 */
  10548. case 11:
  10549. return 45; /* addx8 */
  10550. case 12:
  10551. return 42; /* sub */
  10552. case 13:
  10553. return 46; /* subx2 */
  10554. case 14:
  10555. return 47; /* subx4 */
  10556. case 15:
  10557. return 48; /* subx8 */
  10558. }
  10559. break;
  10560. case 1:
  10561. switch (Field_op2_Slot_inst_get (insn))
  10562. {
  10563. case 0:
  10564. case 1:
  10565. return 111; /* slli */
  10566. case 2:
  10567. case 3:
  10568. return 112; /* srai */
  10569. case 4:
  10570. return 113; /* srli */
  10571. case 6:
  10572. switch (Field_sr_Slot_inst_get (insn))
  10573. {
  10574. case 0:
  10575. return 129; /* xsr.lbeg */
  10576. case 1:
  10577. return 123; /* xsr.lend */
  10578. case 2:
  10579. return 126; /* xsr.lcount */
  10580. case 3:
  10581. return 132; /* xsr.sar */
  10582. case 5:
  10583. return 135; /* xsr.litbase */
  10584. case 12:
  10585. return 434; /* xsr.scompare1 */
  10586. case 16:
  10587. return 306; /* xsr.acclo */
  10588. case 17:
  10589. return 309; /* xsr.acchi */
  10590. case 32:
  10591. return 294; /* xsr.m0 */
  10592. case 33:
  10593. return 297; /* xsr.m1 */
  10594. case 34:
  10595. return 300; /* xsr.m2 */
  10596. case 35:
  10597. return 303; /* xsr.m3 */
  10598. case 72:
  10599. return 22; /* xsr.windowbase */
  10600. case 73:
  10601. return 25; /* xsr.windowstart */
  10602. case 83:
  10603. return 395; /* xsr.ptevaddr */
  10604. case 90:
  10605. return 398; /* xsr.rasid */
  10606. case 91:
  10607. return 401; /* xsr.itlbcfg */
  10608. case 92:
  10609. return 404; /* xsr.dtlbcfg */
  10610. case 96:
  10611. return 340; /* xsr.ibreakenable */
  10612. case 104:
  10613. return 352; /* xsr.ddr */
  10614. case 128:
  10615. return 334; /* xsr.ibreaka0 */
  10616. case 129:
  10617. return 337; /* xsr.ibreaka1 */
  10618. case 144:
  10619. return 322; /* xsr.dbreaka0 */
  10620. case 145:
  10621. return 328; /* xsr.dbreaka1 */
  10622. case 160:
  10623. return 325; /* xsr.dbreakc0 */
  10624. case 161:
  10625. return 331; /* xsr.dbreakc1 */
  10626. case 177:
  10627. return 143; /* xsr.epc1 */
  10628. case 178:
  10629. return 149; /* xsr.epc2 */
  10630. case 179:
  10631. return 155; /* xsr.epc3 */
  10632. case 180:
  10633. return 161; /* xsr.epc4 */
  10634. case 181:
  10635. return 167; /* xsr.epc5 */
  10636. case 182:
  10637. return 173; /* xsr.epc6 */
  10638. case 183:
  10639. return 179; /* xsr.epc7 */
  10640. case 192:
  10641. return 206; /* xsr.depc */
  10642. case 194:
  10643. return 185; /* xsr.eps2 */
  10644. case 195:
  10645. return 188; /* xsr.eps3 */
  10646. case 196:
  10647. return 191; /* xsr.eps4 */
  10648. case 197:
  10649. return 194; /* xsr.eps5 */
  10650. case 198:
  10651. return 197; /* xsr.eps6 */
  10652. case 199:
  10653. return 200; /* xsr.eps7 */
  10654. case 209:
  10655. return 146; /* xsr.excsave1 */
  10656. case 210:
  10657. return 152; /* xsr.excsave2 */
  10658. case 211:
  10659. return 158; /* xsr.excsave3 */
  10660. case 212:
  10661. return 164; /* xsr.excsave4 */
  10662. case 213:
  10663. return 170; /* xsr.excsave5 */
  10664. case 214:
  10665. return 176; /* xsr.excsave6 */
  10666. case 215:
  10667. return 182; /* xsr.excsave7 */
  10668. case 224:
  10669. return 420; /* xsr.cpenable */
  10670. case 228:
  10671. return 317; /* xsr.intenable */
  10672. case 230:
  10673. return 140; /* xsr.ps */
  10674. case 231:
  10675. return 219; /* xsr.vecbase */
  10676. case 232:
  10677. return 209; /* xsr.exccause */
  10678. case 233:
  10679. return 343; /* xsr.debugcause */
  10680. case 234:
  10681. return 358; /* xsr.ccount */
  10682. case 236:
  10683. return 346; /* xsr.icount */
  10684. case 237:
  10685. return 349; /* xsr.icountlevel */
  10686. case 238:
  10687. return 203; /* xsr.excvaddr */
  10688. case 240:
  10689. return 361; /* xsr.ccompare0 */
  10690. case 241:
  10691. return 364; /* xsr.ccompare1 */
  10692. case 242:
  10693. return 367; /* xsr.ccompare2 */
  10694. case 244:
  10695. return 212; /* xsr.misc0 */
  10696. case 245:
  10697. return 215; /* xsr.misc1 */
  10698. }
  10699. break;
  10700. case 8:
  10701. return 108; /* src */
  10702. case 9:
  10703. if (Field_s_Slot_inst_get (insn) == 0)
  10704. return 109; /* srl */
  10705. break;
  10706. case 10:
  10707. if (Field_t_Slot_inst_get (insn) == 0)
  10708. return 107; /* sll */
  10709. break;
  10710. case 11:
  10711. if (Field_s_Slot_inst_get (insn) == 0)
  10712. return 110; /* sra */
  10713. break;
  10714. case 12:
  10715. return 290; /* mul16u */
  10716. case 13:
  10717. return 291; /* mul16s */
  10718. case 15:
  10719. switch (Field_r_Slot_inst_get (insn))
  10720. {
  10721. case 0:
  10722. return 374; /* lict */
  10723. case 1:
  10724. return 376; /* sict */
  10725. case 2:
  10726. return 375; /* licw */
  10727. case 3:
  10728. return 377; /* sicw */
  10729. case 8:
  10730. return 392; /* ldct */
  10731. case 9:
  10732. return 391; /* sdct */
  10733. case 14:
  10734. if (Field_t_Slot_inst_get (insn) == 0)
  10735. return 353; /* rfdo */
  10736. if (Field_t_Slot_inst_get (insn) == 1)
  10737. return 354; /* rfdd */
  10738. break;
  10739. case 15:
  10740. return 415; /* ldpte */
  10741. }
  10742. break;
  10743. }
  10744. break;
  10745. case 2:
  10746. switch (Field_op2_Slot_inst_get (insn))
  10747. {
  10748. case 8:
  10749. return 439; /* mull */
  10750. case 12:
  10751. return 435; /* quou */
  10752. case 13:
  10753. return 436; /* quos */
  10754. case 14:
  10755. return 437; /* remu */
  10756. case 15:
  10757. return 438; /* rems */
  10758. }
  10759. break;
  10760. case 3:
  10761. switch (Field_op2_Slot_inst_get (insn))
  10762. {
  10763. case 0:
  10764. switch (Field_sr_Slot_inst_get (insn))
  10765. {
  10766. case 0:
  10767. return 127; /* rsr.lbeg */
  10768. case 1:
  10769. return 121; /* rsr.lend */
  10770. case 2:
  10771. return 124; /* rsr.lcount */
  10772. case 3:
  10773. return 130; /* rsr.sar */
  10774. case 5:
  10775. return 133; /* rsr.litbase */
  10776. case 12:
  10777. return 432; /* rsr.scompare1 */
  10778. case 16:
  10779. return 304; /* rsr.acclo */
  10780. case 17:
  10781. return 307; /* rsr.acchi */
  10782. case 32:
  10783. return 292; /* rsr.m0 */
  10784. case 33:
  10785. return 295; /* rsr.m1 */
  10786. case 34:
  10787. return 298; /* rsr.m2 */
  10788. case 35:
  10789. return 301; /* rsr.m3 */
  10790. case 72:
  10791. return 20; /* rsr.windowbase */
  10792. case 73:
  10793. return 23; /* rsr.windowstart */
  10794. case 83:
  10795. return 394; /* rsr.ptevaddr */
  10796. case 90:
  10797. return 396; /* rsr.rasid */
  10798. case 91:
  10799. return 399; /* rsr.itlbcfg */
  10800. case 92:
  10801. return 402; /* rsr.dtlbcfg */
  10802. case 96:
  10803. return 338; /* rsr.ibreakenable */
  10804. case 104:
  10805. return 350; /* rsr.ddr */
  10806. case 128:
  10807. return 332; /* rsr.ibreaka0 */
  10808. case 129:
  10809. return 335; /* rsr.ibreaka1 */
  10810. case 144:
  10811. return 320; /* rsr.dbreaka0 */
  10812. case 145:
  10813. return 326; /* rsr.dbreaka1 */
  10814. case 160:
  10815. return 323; /* rsr.dbreakc0 */
  10816. case 161:
  10817. return 329; /* rsr.dbreakc1 */
  10818. case 176:
  10819. return 136; /* rsr.176 */
  10820. case 177:
  10821. return 141; /* rsr.epc1 */
  10822. case 178:
  10823. return 147; /* rsr.epc2 */
  10824. case 179:
  10825. return 153; /* rsr.epc3 */
  10826. case 180:
  10827. return 159; /* rsr.epc4 */
  10828. case 181:
  10829. return 165; /* rsr.epc5 */
  10830. case 182:
  10831. return 171; /* rsr.epc6 */
  10832. case 183:
  10833. return 177; /* rsr.epc7 */
  10834. case 192:
  10835. return 204; /* rsr.depc */
  10836. case 194:
  10837. return 183; /* rsr.eps2 */
  10838. case 195:
  10839. return 186; /* rsr.eps3 */
  10840. case 196:
  10841. return 189; /* rsr.eps4 */
  10842. case 197:
  10843. return 192; /* rsr.eps5 */
  10844. case 198:
  10845. return 195; /* rsr.eps6 */
  10846. case 199:
  10847. return 198; /* rsr.eps7 */
  10848. case 208:
  10849. return 137; /* rsr.208 */
  10850. case 209:
  10851. return 144; /* rsr.excsave1 */
  10852. case 210:
  10853. return 150; /* rsr.excsave2 */
  10854. case 211:
  10855. return 156; /* rsr.excsave3 */
  10856. case 212:
  10857. return 162; /* rsr.excsave4 */
  10858. case 213:
  10859. return 168; /* rsr.excsave5 */
  10860. case 214:
  10861. return 174; /* rsr.excsave6 */
  10862. case 215:
  10863. return 180; /* rsr.excsave7 */
  10864. case 224:
  10865. return 418; /* rsr.cpenable */
  10866. case 226:
  10867. return 312; /* rsr.interrupt */
  10868. case 228:
  10869. return 315; /* rsr.intenable */
  10870. case 230:
  10871. return 138; /* rsr.ps */
  10872. case 231:
  10873. return 217; /* rsr.vecbase */
  10874. case 232:
  10875. return 207; /* rsr.exccause */
  10876. case 233:
  10877. return 341; /* rsr.debugcause */
  10878. case 234:
  10879. return 356; /* rsr.ccount */
  10880. case 235:
  10881. return 216; /* rsr.prid */
  10882. case 236:
  10883. return 344; /* rsr.icount */
  10884. case 237:
  10885. return 347; /* rsr.icountlevel */
  10886. case 238:
  10887. return 201; /* rsr.excvaddr */
  10888. case 240:
  10889. return 359; /* rsr.ccompare0 */
  10890. case 241:
  10891. return 362; /* rsr.ccompare1 */
  10892. case 242:
  10893. return 365; /* rsr.ccompare2 */
  10894. case 244:
  10895. return 210; /* rsr.misc0 */
  10896. case 245:
  10897. return 213; /* rsr.misc1 */
  10898. }
  10899. break;
  10900. case 1:
  10901. switch (Field_sr_Slot_inst_get (insn))
  10902. {
  10903. case 0:
  10904. return 128; /* wsr.lbeg */
  10905. case 1:
  10906. return 122; /* wsr.lend */
  10907. case 2:
  10908. return 125; /* wsr.lcount */
  10909. case 3:
  10910. return 131; /* wsr.sar */
  10911. case 5:
  10912. return 134; /* wsr.litbase */
  10913. case 12:
  10914. return 433; /* wsr.scompare1 */
  10915. case 16:
  10916. return 305; /* wsr.acclo */
  10917. case 17:
  10918. return 308; /* wsr.acchi */
  10919. case 32:
  10920. return 293; /* wsr.m0 */
  10921. case 33:
  10922. return 296; /* wsr.m1 */
  10923. case 34:
  10924. return 299; /* wsr.m2 */
  10925. case 35:
  10926. return 302; /* wsr.m3 */
  10927. case 72:
  10928. return 21; /* wsr.windowbase */
  10929. case 73:
  10930. return 24; /* wsr.windowstart */
  10931. case 83:
  10932. return 393; /* wsr.ptevaddr */
  10933. case 89:
  10934. return 355; /* wsr.mmid */
  10935. case 90:
  10936. return 397; /* wsr.rasid */
  10937. case 91:
  10938. return 400; /* wsr.itlbcfg */
  10939. case 92:
  10940. return 403; /* wsr.dtlbcfg */
  10941. case 96:
  10942. return 339; /* wsr.ibreakenable */
  10943. case 104:
  10944. return 351; /* wsr.ddr */
  10945. case 128:
  10946. return 333; /* wsr.ibreaka0 */
  10947. case 129:
  10948. return 336; /* wsr.ibreaka1 */
  10949. case 144:
  10950. return 321; /* wsr.dbreaka0 */
  10951. case 145:
  10952. return 327; /* wsr.dbreaka1 */
  10953. case 160:
  10954. return 324; /* wsr.dbreakc0 */
  10955. case 161:
  10956. return 330; /* wsr.dbreakc1 */
  10957. case 177:
  10958. return 142; /* wsr.epc1 */
  10959. case 178:
  10960. return 148; /* wsr.epc2 */
  10961. case 179:
  10962. return 154; /* wsr.epc3 */
  10963. case 180:
  10964. return 160; /* wsr.epc4 */
  10965. case 181:
  10966. return 166; /* wsr.epc5 */
  10967. case 182:
  10968. return 172; /* wsr.epc6 */
  10969. case 183:
  10970. return 178; /* wsr.epc7 */
  10971. case 192:
  10972. return 205; /* wsr.depc */
  10973. case 194:
  10974. return 184; /* wsr.eps2 */
  10975. case 195:
  10976. return 187; /* wsr.eps3 */
  10977. case 196:
  10978. return 190; /* wsr.eps4 */
  10979. case 197:
  10980. return 193; /* wsr.eps5 */
  10981. case 198:
  10982. return 196; /* wsr.eps6 */
  10983. case 199:
  10984. return 199; /* wsr.eps7 */
  10985. case 209:
  10986. return 145; /* wsr.excsave1 */
  10987. case 210:
  10988. return 151; /* wsr.excsave2 */
  10989. case 211:
  10990. return 157; /* wsr.excsave3 */
  10991. case 212:
  10992. return 163; /* wsr.excsave4 */
  10993. case 213:
  10994. return 169; /* wsr.excsave5 */
  10995. case 214:
  10996. return 175; /* wsr.excsave6 */
  10997. case 215:
  10998. return 181; /* wsr.excsave7 */
  10999. case 224:
  11000. return 419; /* wsr.cpenable */
  11001. case 226:
  11002. return 313; /* wsr.intset */
  11003. case 227:
  11004. return 314; /* wsr.intclear */
  11005. case 228:
  11006. return 316; /* wsr.intenable */
  11007. case 230:
  11008. return 139; /* wsr.ps */
  11009. case 231:
  11010. return 218; /* wsr.vecbase */
  11011. case 232:
  11012. return 208; /* wsr.exccause */
  11013. case 233:
  11014. return 342; /* wsr.debugcause */
  11015. case 234:
  11016. return 357; /* wsr.ccount */
  11017. case 236:
  11018. return 345; /* wsr.icount */
  11019. case 237:
  11020. return 348; /* wsr.icountlevel */
  11021. case 238:
  11022. return 202; /* wsr.excvaddr */
  11023. case 240:
  11024. return 360; /* wsr.ccompare0 */
  11025. case 241:
  11026. return 363; /* wsr.ccompare1 */
  11027. case 242:
  11028. return 366; /* wsr.ccompare2 */
  11029. case 244:
  11030. return 211; /* wsr.misc0 */
  11031. case 245:
  11032. return 214; /* wsr.misc1 */
  11033. }
  11034. break;
  11035. case 2:
  11036. return 428; /* sext */
  11037. case 3:
  11038. return 421; /* clamps */
  11039. case 4:
  11040. return 422; /* min */
  11041. case 5:
  11042. return 423; /* max */
  11043. case 6:
  11044. return 424; /* minu */
  11045. case 7:
  11046. return 425; /* maxu */
  11047. case 8:
  11048. return 91; /* moveqz */
  11049. case 9:
  11050. return 92; /* movnez */
  11051. case 10:
  11052. return 93; /* movltz */
  11053. case 11:
  11054. return 94; /* movgez */
  11055. case 14:
  11056. switch (Field_st_Slot_inst_get (insn))
  11057. {
  11058. case 230:
  11059. return 440; /* rur.expstate */
  11060. case 231:
  11061. return 37; /* rur.threadptr */
  11062. }
  11063. break;
  11064. case 15:
  11065. switch (Field_sr_Slot_inst_get (insn))
  11066. {
  11067. case 230:
  11068. return 441; /* wur.expstate */
  11069. case 231:
  11070. return 38; /* wur.threadptr */
  11071. }
  11072. break;
  11073. }
  11074. break;
  11075. case 4:
  11076. case 5:
  11077. return 78; /* extui */
  11078. case 9:
  11079. switch (Field_op2_Slot_inst_get (insn))
  11080. {
  11081. case 0:
  11082. return 18; /* l32e */
  11083. case 4:
  11084. return 19; /* s32e */
  11085. }
  11086. break;
  11087. }
  11088. switch (Field_r_Slot_inst_get (insn))
  11089. {
  11090. case 0:
  11091. if (Field_s_Slot_inst_get (insn) == 0 &&
  11092. Field_op2_Slot_inst_get (insn) == 0 &&
  11093. Field_op1_Slot_inst_get (insn) == 14)
  11094. return 442; /* read_impwire */
  11095. break;
  11096. case 1:
  11097. if (Field_s3to1_Slot_inst_get (insn) == 0 &&
  11098. Field_op2_Slot_inst_get (insn) == 0 &&
  11099. Field_op1_Slot_inst_get (insn) == 14)
  11100. return 443; /* setb_expstate */
  11101. if (Field_s3to1_Slot_inst_get (insn) == 1 &&
  11102. Field_op2_Slot_inst_get (insn) == 0 &&
  11103. Field_op1_Slot_inst_get (insn) == 14)
  11104. return 444; /* clrb_expstate */
  11105. break;
  11106. case 2:
  11107. if (Field_op2_Slot_inst_get (insn) == 0 &&
  11108. Field_op1_Slot_inst_get (insn) == 14)
  11109. return 445; /* wrmsk_expstate */
  11110. break;
  11111. }
  11112. break;
  11113. case 1:
  11114. return 85; /* l32r */
  11115. case 2:
  11116. switch (Field_r_Slot_inst_get (insn))
  11117. {
  11118. case 0:
  11119. return 86; /* l8ui */
  11120. case 1:
  11121. return 82; /* l16ui */
  11122. case 2:
  11123. return 84; /* l32i */
  11124. case 4:
  11125. return 101; /* s8i */
  11126. case 5:
  11127. return 99; /* s16i */
  11128. case 6:
  11129. return 100; /* s32i */
  11130. case 7:
  11131. switch (Field_t_Slot_inst_get (insn))
  11132. {
  11133. case 0:
  11134. return 384; /* dpfr */
  11135. case 1:
  11136. return 385; /* dpfw */
  11137. case 2:
  11138. return 386; /* dpfro */
  11139. case 3:
  11140. return 387; /* dpfwo */
  11141. case 4:
  11142. return 378; /* dhwb */
  11143. case 5:
  11144. return 379; /* dhwbi */
  11145. case 6:
  11146. return 382; /* dhi */
  11147. case 7:
  11148. return 383; /* dii */
  11149. case 8:
  11150. switch (Field_op1_Slot_inst_get (insn))
  11151. {
  11152. case 0:
  11153. return 388; /* dpfl */
  11154. case 2:
  11155. return 389; /* dhu */
  11156. case 3:
  11157. return 390; /* diu */
  11158. case 4:
  11159. return 380; /* diwb */
  11160. case 5:
  11161. return 381; /* diwbi */
  11162. }
  11163. break;
  11164. case 12:
  11165. return 368; /* ipf */
  11166. case 13:
  11167. switch (Field_op1_Slot_inst_get (insn))
  11168. {
  11169. case 0:
  11170. return 370; /* ipfl */
  11171. case 2:
  11172. return 371; /* ihu */
  11173. case 3:
  11174. return 372; /* iiu */
  11175. }
  11176. break;
  11177. case 14:
  11178. return 369; /* ihi */
  11179. case 15:
  11180. return 373; /* iii */
  11181. }
  11182. break;
  11183. case 9:
  11184. return 83; /* l16si */
  11185. case 10:
  11186. return 90; /* movi */
  11187. case 11:
  11188. return 429; /* l32ai */
  11189. case 12:
  11190. return 39; /* addi */
  11191. case 13:
  11192. return 40; /* addmi */
  11193. case 14:
  11194. return 431; /* s32c1i */
  11195. case 15:
  11196. return 430; /* s32ri */
  11197. }
  11198. break;
  11199. case 4:
  11200. switch (Field_op2_Slot_inst_get (insn))
  11201. {
  11202. case 0:
  11203. switch (Field_op1_Slot_inst_get (insn))
  11204. {
  11205. case 8:
  11206. if (Field_t3_Slot_inst_get (insn) == 0 &&
  11207. Field_tlo_Slot_inst_get (insn) == 0 &&
  11208. Field_r3_Slot_inst_get (insn) == 0)
  11209. return 281; /* mula.dd.ll.ldinc */
  11210. break;
  11211. case 9:
  11212. if (Field_t3_Slot_inst_get (insn) == 0 &&
  11213. Field_tlo_Slot_inst_get (insn) == 0 &&
  11214. Field_r3_Slot_inst_get (insn) == 0)
  11215. return 283; /* mula.dd.hl.ldinc */
  11216. break;
  11217. case 10:
  11218. if (Field_t3_Slot_inst_get (insn) == 0 &&
  11219. Field_tlo_Slot_inst_get (insn) == 0 &&
  11220. Field_r3_Slot_inst_get (insn) == 0)
  11221. return 285; /* mula.dd.lh.ldinc */
  11222. break;
  11223. case 11:
  11224. if (Field_t3_Slot_inst_get (insn) == 0 &&
  11225. Field_tlo_Slot_inst_get (insn) == 0 &&
  11226. Field_r3_Slot_inst_get (insn) == 0)
  11227. return 287; /* mula.dd.hh.ldinc */
  11228. break;
  11229. }
  11230. break;
  11231. case 1:
  11232. switch (Field_op1_Slot_inst_get (insn))
  11233. {
  11234. case 8:
  11235. if (Field_t3_Slot_inst_get (insn) == 0 &&
  11236. Field_tlo_Slot_inst_get (insn) == 0 &&
  11237. Field_r3_Slot_inst_get (insn) == 0)
  11238. return 280; /* mula.dd.ll.lddec */
  11239. break;
  11240. case 9:
  11241. if (Field_t3_Slot_inst_get (insn) == 0 &&
  11242. Field_tlo_Slot_inst_get (insn) == 0 &&
  11243. Field_r3_Slot_inst_get (insn) == 0)
  11244. return 282; /* mula.dd.hl.lddec */
  11245. break;
  11246. case 10:
  11247. if (Field_t3_Slot_inst_get (insn) == 0 &&
  11248. Field_tlo_Slot_inst_get (insn) == 0 &&
  11249. Field_r3_Slot_inst_get (insn) == 0)
  11250. return 284; /* mula.dd.lh.lddec */
  11251. break;
  11252. case 11:
  11253. if (Field_t3_Slot_inst_get (insn) == 0 &&
  11254. Field_tlo_Slot_inst_get (insn) == 0 &&
  11255. Field_r3_Slot_inst_get (insn) == 0)
  11256. return 286; /* mula.dd.hh.lddec */
  11257. break;
  11258. }
  11259. break;
  11260. case 2:
  11261. switch (Field_op1_Slot_inst_get (insn))
  11262. {
  11263. case 4:
  11264. if (Field_s_Slot_inst_get (insn) == 0 &&
  11265. Field_w_Slot_inst_get (insn) == 0 &&
  11266. Field_r3_Slot_inst_get (insn) == 0 &&
  11267. Field_t3_Slot_inst_get (insn) == 0 &&
  11268. Field_tlo_Slot_inst_get (insn) == 0)
  11269. return 236; /* mul.dd.ll */
  11270. break;
  11271. case 5:
  11272. if (Field_s_Slot_inst_get (insn) == 0 &&
  11273. Field_w_Slot_inst_get (insn) == 0 &&
  11274. Field_r3_Slot_inst_get (insn) == 0 &&
  11275. Field_t3_Slot_inst_get (insn) == 0 &&
  11276. Field_tlo_Slot_inst_get (insn) == 0)
  11277. return 237; /* mul.dd.hl */
  11278. break;
  11279. case 6:
  11280. if (Field_s_Slot_inst_get (insn) == 0 &&
  11281. Field_w_Slot_inst_get (insn) == 0 &&
  11282. Field_r3_Slot_inst_get (insn) == 0 &&
  11283. Field_t3_Slot_inst_get (insn) == 0 &&
  11284. Field_tlo_Slot_inst_get (insn) == 0)
  11285. return 238; /* mul.dd.lh */
  11286. break;
  11287. case 7:
  11288. if (Field_s_Slot_inst_get (insn) == 0 &&
  11289. Field_w_Slot_inst_get (insn) == 0 &&
  11290. Field_r3_Slot_inst_get (insn) == 0 &&
  11291. Field_t3_Slot_inst_get (insn) == 0 &&
  11292. Field_tlo_Slot_inst_get (insn) == 0)
  11293. return 239; /* mul.dd.hh */
  11294. break;
  11295. case 8:
  11296. if (Field_s_Slot_inst_get (insn) == 0 &&
  11297. Field_w_Slot_inst_get (insn) == 0 &&
  11298. Field_r3_Slot_inst_get (insn) == 0 &&
  11299. Field_t3_Slot_inst_get (insn) == 0 &&
  11300. Field_tlo_Slot_inst_get (insn) == 0)
  11301. return 264; /* mula.dd.ll */
  11302. break;
  11303. case 9:
  11304. if (Field_s_Slot_inst_get (insn) == 0 &&
  11305. Field_w_Slot_inst_get (insn) == 0 &&
  11306. Field_r3_Slot_inst_get (insn) == 0 &&
  11307. Field_t3_Slot_inst_get (insn) == 0 &&
  11308. Field_tlo_Slot_inst_get (insn) == 0)
  11309. return 265; /* mula.dd.hl */
  11310. break;
  11311. case 10:
  11312. if (Field_s_Slot_inst_get (insn) == 0 &&
  11313. Field_w_Slot_inst_get (insn) == 0 &&
  11314. Field_r3_Slot_inst_get (insn) == 0 &&
  11315. Field_t3_Slot_inst_get (insn) == 0 &&
  11316. Field_tlo_Slot_inst_get (insn) == 0)
  11317. return 266; /* mula.dd.lh */
  11318. break;
  11319. case 11:
  11320. if (Field_s_Slot_inst_get (insn) == 0 &&
  11321. Field_w_Slot_inst_get (insn) == 0 &&
  11322. Field_r3_Slot_inst_get (insn) == 0 &&
  11323. Field_t3_Slot_inst_get (insn) == 0 &&
  11324. Field_tlo_Slot_inst_get (insn) == 0)
  11325. return 267; /* mula.dd.hh */
  11326. break;
  11327. case 12:
  11328. if (Field_s_Slot_inst_get (insn) == 0 &&
  11329. Field_w_Slot_inst_get (insn) == 0 &&
  11330. Field_r3_Slot_inst_get (insn) == 0 &&
  11331. Field_t3_Slot_inst_get (insn) == 0 &&
  11332. Field_tlo_Slot_inst_get (insn) == 0)
  11333. return 268; /* muls.dd.ll */
  11334. break;
  11335. case 13:
  11336. if (Field_s_Slot_inst_get (insn) == 0 &&
  11337. Field_w_Slot_inst_get (insn) == 0 &&
  11338. Field_r3_Slot_inst_get (insn) == 0 &&
  11339. Field_t3_Slot_inst_get (insn) == 0 &&
  11340. Field_tlo_Slot_inst_get (insn) == 0)
  11341. return 269; /* muls.dd.hl */
  11342. break;
  11343. case 14:
  11344. if (Field_s_Slot_inst_get (insn) == 0 &&
  11345. Field_w_Slot_inst_get (insn) == 0 &&
  11346. Field_r3_Slot_inst_get (insn) == 0 &&
  11347. Field_t3_Slot_inst_get (insn) == 0 &&
  11348. Field_tlo_Slot_inst_get (insn) == 0)
  11349. return 270; /* muls.dd.lh */
  11350. break;
  11351. case 15:
  11352. if (Field_s_Slot_inst_get (insn) == 0 &&
  11353. Field_w_Slot_inst_get (insn) == 0 &&
  11354. Field_r3_Slot_inst_get (insn) == 0 &&
  11355. Field_t3_Slot_inst_get (insn) == 0 &&
  11356. Field_tlo_Slot_inst_get (insn) == 0)
  11357. return 271; /* muls.dd.hh */
  11358. break;
  11359. }
  11360. break;
  11361. case 3:
  11362. switch (Field_op1_Slot_inst_get (insn))
  11363. {
  11364. case 4:
  11365. if (Field_r_Slot_inst_get (insn) == 0 &&
  11366. Field_t3_Slot_inst_get (insn) == 0 &&
  11367. Field_tlo_Slot_inst_get (insn) == 0)
  11368. return 228; /* mul.ad.ll */
  11369. break;
  11370. case 5:
  11371. if (Field_r_Slot_inst_get (insn) == 0 &&
  11372. Field_t3_Slot_inst_get (insn) == 0 &&
  11373. Field_tlo_Slot_inst_get (insn) == 0)
  11374. return 229; /* mul.ad.hl */
  11375. break;
  11376. case 6:
  11377. if (Field_r_Slot_inst_get (insn) == 0 &&
  11378. Field_t3_Slot_inst_get (insn) == 0 &&
  11379. Field_tlo_Slot_inst_get (insn) == 0)
  11380. return 230; /* mul.ad.lh */
  11381. break;
  11382. case 7:
  11383. if (Field_r_Slot_inst_get (insn) == 0 &&
  11384. Field_t3_Slot_inst_get (insn) == 0 &&
  11385. Field_tlo_Slot_inst_get (insn) == 0)
  11386. return 231; /* mul.ad.hh */
  11387. break;
  11388. case 8:
  11389. if (Field_r_Slot_inst_get (insn) == 0 &&
  11390. Field_t3_Slot_inst_get (insn) == 0 &&
  11391. Field_tlo_Slot_inst_get (insn) == 0)
  11392. return 248; /* mula.ad.ll */
  11393. break;
  11394. case 9:
  11395. if (Field_r_Slot_inst_get (insn) == 0 &&
  11396. Field_t3_Slot_inst_get (insn) == 0 &&
  11397. Field_tlo_Slot_inst_get (insn) == 0)
  11398. return 249; /* mula.ad.hl */
  11399. break;
  11400. case 10:
  11401. if (Field_r_Slot_inst_get (insn) == 0 &&
  11402. Field_t3_Slot_inst_get (insn) == 0 &&
  11403. Field_tlo_Slot_inst_get (insn) == 0)
  11404. return 250; /* mula.ad.lh */
  11405. break;
  11406. case 11:
  11407. if (Field_r_Slot_inst_get (insn) == 0 &&
  11408. Field_t3_Slot_inst_get (insn) == 0 &&
  11409. Field_tlo_Slot_inst_get (insn) == 0)
  11410. return 251; /* mula.ad.hh */
  11411. break;
  11412. case 12:
  11413. if (Field_r_Slot_inst_get (insn) == 0 &&
  11414. Field_t3_Slot_inst_get (insn) == 0 &&
  11415. Field_tlo_Slot_inst_get (insn) == 0)
  11416. return 252; /* muls.ad.ll */
  11417. break;
  11418. case 13:
  11419. if (Field_r_Slot_inst_get (insn) == 0 &&
  11420. Field_t3_Slot_inst_get (insn) == 0 &&
  11421. Field_tlo_Slot_inst_get (insn) == 0)
  11422. return 253; /* muls.ad.hl */
  11423. break;
  11424. case 14:
  11425. if (Field_r_Slot_inst_get (insn) == 0 &&
  11426. Field_t3_Slot_inst_get (insn) == 0 &&
  11427. Field_tlo_Slot_inst_get (insn) == 0)
  11428. return 254; /* muls.ad.lh */
  11429. break;
  11430. case 15:
  11431. if (Field_r_Slot_inst_get (insn) == 0 &&
  11432. Field_t3_Slot_inst_get (insn) == 0 &&
  11433. Field_tlo_Slot_inst_get (insn) == 0)
  11434. return 255; /* muls.ad.hh */
  11435. break;
  11436. }
  11437. break;
  11438. case 4:
  11439. switch (Field_op1_Slot_inst_get (insn))
  11440. {
  11441. case 8:
  11442. if (Field_r3_Slot_inst_get (insn) == 0)
  11443. return 273; /* mula.da.ll.ldinc */
  11444. break;
  11445. case 9:
  11446. if (Field_r3_Slot_inst_get (insn) == 0)
  11447. return 275; /* mula.da.hl.ldinc */
  11448. break;
  11449. case 10:
  11450. if (Field_r3_Slot_inst_get (insn) == 0)
  11451. return 277; /* mula.da.lh.ldinc */
  11452. break;
  11453. case 11:
  11454. if (Field_r3_Slot_inst_get (insn) == 0)
  11455. return 279; /* mula.da.hh.ldinc */
  11456. break;
  11457. }
  11458. break;
  11459. case 5:
  11460. switch (Field_op1_Slot_inst_get (insn))
  11461. {
  11462. case 8:
  11463. if (Field_r3_Slot_inst_get (insn) == 0)
  11464. return 272; /* mula.da.ll.lddec */
  11465. break;
  11466. case 9:
  11467. if (Field_r3_Slot_inst_get (insn) == 0)
  11468. return 274; /* mula.da.hl.lddec */
  11469. break;
  11470. case 10:
  11471. if (Field_r3_Slot_inst_get (insn) == 0)
  11472. return 276; /* mula.da.lh.lddec */
  11473. break;
  11474. case 11:
  11475. if (Field_r3_Slot_inst_get (insn) == 0)
  11476. return 278; /* mula.da.hh.lddec */
  11477. break;
  11478. }
  11479. break;
  11480. case 6:
  11481. switch (Field_op1_Slot_inst_get (insn))
  11482. {
  11483. case 4:
  11484. if (Field_s_Slot_inst_get (insn) == 0 &&
  11485. Field_w_Slot_inst_get (insn) == 0 &&
  11486. Field_r3_Slot_inst_get (insn) == 0)
  11487. return 232; /* mul.da.ll */
  11488. break;
  11489. case 5:
  11490. if (Field_s_Slot_inst_get (insn) == 0 &&
  11491. Field_w_Slot_inst_get (insn) == 0 &&
  11492. Field_r3_Slot_inst_get (insn) == 0)
  11493. return 233; /* mul.da.hl */
  11494. break;
  11495. case 6:
  11496. if (Field_s_Slot_inst_get (insn) == 0 &&
  11497. Field_w_Slot_inst_get (insn) == 0 &&
  11498. Field_r3_Slot_inst_get (insn) == 0)
  11499. return 234; /* mul.da.lh */
  11500. break;
  11501. case 7:
  11502. if (Field_s_Slot_inst_get (insn) == 0 &&
  11503. Field_w_Slot_inst_get (insn) == 0 &&
  11504. Field_r3_Slot_inst_get (insn) == 0)
  11505. return 235; /* mul.da.hh */
  11506. break;
  11507. case 8:
  11508. if (Field_s_Slot_inst_get (insn) == 0 &&
  11509. Field_w_Slot_inst_get (insn) == 0 &&
  11510. Field_r3_Slot_inst_get (insn) == 0)
  11511. return 256; /* mula.da.ll */
  11512. break;
  11513. case 9:
  11514. if (Field_s_Slot_inst_get (insn) == 0 &&
  11515. Field_w_Slot_inst_get (insn) == 0 &&
  11516. Field_r3_Slot_inst_get (insn) == 0)
  11517. return 257; /* mula.da.hl */
  11518. break;
  11519. case 10:
  11520. if (Field_s_Slot_inst_get (insn) == 0 &&
  11521. Field_w_Slot_inst_get (insn) == 0 &&
  11522. Field_r3_Slot_inst_get (insn) == 0)
  11523. return 258; /* mula.da.lh */
  11524. break;
  11525. case 11:
  11526. if (Field_s_Slot_inst_get (insn) == 0 &&
  11527. Field_w_Slot_inst_get (insn) == 0 &&
  11528. Field_r3_Slot_inst_get (insn) == 0)
  11529. return 259; /* mula.da.hh */
  11530. break;
  11531. case 12:
  11532. if (Field_s_Slot_inst_get (insn) == 0 &&
  11533. Field_w_Slot_inst_get (insn) == 0 &&
  11534. Field_r3_Slot_inst_get (insn) == 0)
  11535. return 260; /* muls.da.ll */
  11536. break;
  11537. case 13:
  11538. if (Field_s_Slot_inst_get (insn) == 0 &&
  11539. Field_w_Slot_inst_get (insn) == 0 &&
  11540. Field_r3_Slot_inst_get (insn) == 0)
  11541. return 261; /* muls.da.hl */
  11542. break;
  11543. case 14:
  11544. if (Field_s_Slot_inst_get (insn) == 0 &&
  11545. Field_w_Slot_inst_get (insn) == 0 &&
  11546. Field_r3_Slot_inst_get (insn) == 0)
  11547. return 262; /* muls.da.lh */
  11548. break;
  11549. case 15:
  11550. if (Field_s_Slot_inst_get (insn) == 0 &&
  11551. Field_w_Slot_inst_get (insn) == 0 &&
  11552. Field_r3_Slot_inst_get (insn) == 0)
  11553. return 263; /* muls.da.hh */
  11554. break;
  11555. }
  11556. break;
  11557. case 7:
  11558. switch (Field_op1_Slot_inst_get (insn))
  11559. {
  11560. case 0:
  11561. if (Field_r_Slot_inst_get (insn) == 0)
  11562. return 224; /* umul.aa.ll */
  11563. break;
  11564. case 1:
  11565. if (Field_r_Slot_inst_get (insn) == 0)
  11566. return 225; /* umul.aa.hl */
  11567. break;
  11568. case 2:
  11569. if (Field_r_Slot_inst_get (insn) == 0)
  11570. return 226; /* umul.aa.lh */
  11571. break;
  11572. case 3:
  11573. if (Field_r_Slot_inst_get (insn) == 0)
  11574. return 227; /* umul.aa.hh */
  11575. break;
  11576. case 4:
  11577. if (Field_r_Slot_inst_get (insn) == 0)
  11578. return 220; /* mul.aa.ll */
  11579. break;
  11580. case 5:
  11581. if (Field_r_Slot_inst_get (insn) == 0)
  11582. return 221; /* mul.aa.hl */
  11583. break;
  11584. case 6:
  11585. if (Field_r_Slot_inst_get (insn) == 0)
  11586. return 222; /* mul.aa.lh */
  11587. break;
  11588. case 7:
  11589. if (Field_r_Slot_inst_get (insn) == 0)
  11590. return 223; /* mul.aa.hh */
  11591. break;
  11592. case 8:
  11593. if (Field_r_Slot_inst_get (insn) == 0)
  11594. return 240; /* mula.aa.ll */
  11595. break;
  11596. case 9:
  11597. if (Field_r_Slot_inst_get (insn) == 0)
  11598. return 241; /* mula.aa.hl */
  11599. break;
  11600. case 10:
  11601. if (Field_r_Slot_inst_get (insn) == 0)
  11602. return 242; /* mula.aa.lh */
  11603. break;
  11604. case 11:
  11605. if (Field_r_Slot_inst_get (insn) == 0)
  11606. return 243; /* mula.aa.hh */
  11607. break;
  11608. case 12:
  11609. if (Field_r_Slot_inst_get (insn) == 0)
  11610. return 244; /* muls.aa.ll */
  11611. break;
  11612. case 13:
  11613. if (Field_r_Slot_inst_get (insn) == 0)
  11614. return 245; /* muls.aa.hl */
  11615. break;
  11616. case 14:
  11617. if (Field_r_Slot_inst_get (insn) == 0)
  11618. return 246; /* muls.aa.lh */
  11619. break;
  11620. case 15:
  11621. if (Field_r_Slot_inst_get (insn) == 0)
  11622. return 247; /* muls.aa.hh */
  11623. break;
  11624. }
  11625. break;
  11626. case 8:
  11627. if (Field_op1_Slot_inst_get (insn) == 0 &&
  11628. Field_t_Slot_inst_get (insn) == 0 &&
  11629. Field_rhi_Slot_inst_get (insn) == 0)
  11630. return 289; /* ldinc */
  11631. break;
  11632. case 9:
  11633. if (Field_op1_Slot_inst_get (insn) == 0 &&
  11634. Field_t_Slot_inst_get (insn) == 0 &&
  11635. Field_rhi_Slot_inst_get (insn) == 0)
  11636. return 288; /* lddec */
  11637. break;
  11638. }
  11639. break;
  11640. case 5:
  11641. switch (Field_n_Slot_inst_get (insn))
  11642. {
  11643. case 0:
  11644. return 76; /* call0 */
  11645. case 1:
  11646. return 7; /* call4 */
  11647. case 2:
  11648. return 6; /* call8 */
  11649. case 3:
  11650. return 5; /* call12 */
  11651. }
  11652. break;
  11653. case 6:
  11654. switch (Field_n_Slot_inst_get (insn))
  11655. {
  11656. case 0:
  11657. return 80; /* j */
  11658. case 1:
  11659. switch (Field_m_Slot_inst_get (insn))
  11660. {
  11661. case 0:
  11662. return 72; /* beqz */
  11663. case 1:
  11664. return 73; /* bnez */
  11665. case 2:
  11666. return 75; /* bltz */
  11667. case 3:
  11668. return 74; /* bgez */
  11669. }
  11670. break;
  11671. case 2:
  11672. switch (Field_m_Slot_inst_get (insn))
  11673. {
  11674. case 0:
  11675. return 52; /* beqi */
  11676. case 1:
  11677. return 53; /* bnei */
  11678. case 2:
  11679. return 55; /* blti */
  11680. case 3:
  11681. return 54; /* bgei */
  11682. }
  11683. break;
  11684. case 3:
  11685. switch (Field_m_Slot_inst_get (insn))
  11686. {
  11687. case 0:
  11688. return 11; /* entry */
  11689. case 1:
  11690. switch (Field_r_Slot_inst_get (insn))
  11691. {
  11692. case 8:
  11693. return 87; /* loop */
  11694. case 9:
  11695. return 88; /* loopnez */
  11696. case 10:
  11697. return 89; /* loopgtz */
  11698. }
  11699. break;
  11700. case 2:
  11701. return 59; /* bltui */
  11702. case 3:
  11703. return 58; /* bgeui */
  11704. }
  11705. break;
  11706. }
  11707. break;
  11708. case 7:
  11709. switch (Field_r_Slot_inst_get (insn))
  11710. {
  11711. case 0:
  11712. return 67; /* bnone */
  11713. case 1:
  11714. return 60; /* beq */
  11715. case 2:
  11716. return 63; /* blt */
  11717. case 3:
  11718. return 65; /* bltu */
  11719. case 4:
  11720. return 68; /* ball */
  11721. case 5:
  11722. return 70; /* bbc */
  11723. case 6:
  11724. case 7:
  11725. return 56; /* bbci */
  11726. case 8:
  11727. return 66; /* bany */
  11728. case 9:
  11729. return 61; /* bne */
  11730. case 10:
  11731. return 62; /* bge */
  11732. case 11:
  11733. return 64; /* bgeu */
  11734. case 12:
  11735. return 69; /* bnall */
  11736. case 13:
  11737. return 71; /* bbs */
  11738. case 14:
  11739. case 15:
  11740. return 57; /* bbsi */
  11741. }
  11742. break;
  11743. }
  11744. return XTENSA_UNDEFINED;
  11745. }
  11746. static int
  11747. Slot_inst16b_decode (const xtensa_insnbuf insn)
  11748. {
  11749. switch (Field_op0_Slot_inst16b_get (insn))
  11750. {
  11751. case 12:
  11752. switch (Field_i_Slot_inst16b_get (insn))
  11753. {
  11754. case 0:
  11755. return 33; /* movi.n */
  11756. case 1:
  11757. switch (Field_z_Slot_inst16b_get (insn))
  11758. {
  11759. case 0:
  11760. return 28; /* beqz.n */
  11761. case 1:
  11762. return 29; /* bnez.n */
  11763. }
  11764. break;
  11765. }
  11766. break;
  11767. case 13:
  11768. switch (Field_r_Slot_inst16b_get (insn))
  11769. {
  11770. case 0:
  11771. return 32; /* mov.n */
  11772. case 15:
  11773. switch (Field_t_Slot_inst16b_get (insn))
  11774. {
  11775. case 0:
  11776. return 35; /* ret.n */
  11777. case 1:
  11778. return 15; /* retw.n */
  11779. case 2:
  11780. return 319; /* break.n */
  11781. case 3:
  11782. if (Field_s_Slot_inst16b_get (insn) == 0)
  11783. return 34; /* nop.n */
  11784. break;
  11785. case 6:
  11786. if (Field_s_Slot_inst16b_get (insn) == 0)
  11787. return 30; /* ill.n */
  11788. break;
  11789. }
  11790. break;
  11791. }
  11792. break;
  11793. }
  11794. return XTENSA_UNDEFINED;
  11795. }
  11796. static int
  11797. Slot_inst16a_decode (const xtensa_insnbuf insn)
  11798. {
  11799. switch (Field_op0_Slot_inst16a_get (insn))
  11800. {
  11801. case 8:
  11802. return 31; /* l32i.n */
  11803. case 9:
  11804. return 36; /* s32i.n */
  11805. case 10:
  11806. return 26; /* add.n */
  11807. case 11:
  11808. return 27; /* addi.n */
  11809. }
  11810. return XTENSA_UNDEFINED;
  11811. }
  11812. /* Instruction slots. */
  11813. static void
  11814. Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
  11815. xtensa_insnbuf slotbuf)
  11816. {
  11817. slotbuf[0] = (insn[0] & 0xffffff);
  11818. }
  11819. static void
  11820. Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
  11821. const xtensa_insnbuf slotbuf)
  11822. {
  11823. insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
  11824. }
  11825. static void
  11826. Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
  11827. xtensa_insnbuf slotbuf)
  11828. {
  11829. slotbuf[0] = (insn[0] & 0xffff);
  11830. }
  11831. static void
  11832. Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
  11833. const xtensa_insnbuf slotbuf)
  11834. {
  11835. insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
  11836. }
  11837. static void
  11838. Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
  11839. xtensa_insnbuf slotbuf)
  11840. {
  11841. slotbuf[0] = (insn[0] & 0xffff);
  11842. }
  11843. static void
  11844. Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
  11845. const xtensa_insnbuf slotbuf)
  11846. {
  11847. insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
  11848. }
  11849. static xtensa_get_field_fn
  11850. Slot_inst_get_field_fns[] = {
  11851. Field_t_Slot_inst_get,
  11852. Field_bbi4_Slot_inst_get,
  11853. Field_bbi_Slot_inst_get,
  11854. Field_imm12_Slot_inst_get,
  11855. Field_imm8_Slot_inst_get,
  11856. Field_s_Slot_inst_get,
  11857. Field_imm12b_Slot_inst_get,
  11858. Field_imm16_Slot_inst_get,
  11859. Field_m_Slot_inst_get,
  11860. Field_n_Slot_inst_get,
  11861. Field_offset_Slot_inst_get,
  11862. Field_op0_Slot_inst_get,
  11863. Field_op1_Slot_inst_get,
  11864. Field_op2_Slot_inst_get,
  11865. Field_r_Slot_inst_get,
  11866. Field_sa4_Slot_inst_get,
  11867. Field_sae4_Slot_inst_get,
  11868. Field_sae_Slot_inst_get,
  11869. Field_sal_Slot_inst_get,
  11870. Field_sargt_Slot_inst_get,
  11871. Field_sas4_Slot_inst_get,
  11872. Field_sas_Slot_inst_get,
  11873. Field_sr_Slot_inst_get,
  11874. Field_st_Slot_inst_get,
  11875. Field_thi3_Slot_inst_get,
  11876. Field_imm4_Slot_inst_get,
  11877. Field_mn_Slot_inst_get,
  11878. 0,
  11879. 0,
  11880. 0,
  11881. 0,
  11882. 0,
  11883. 0,
  11884. 0,
  11885. 0,
  11886. Field_r3_Slot_inst_get,
  11887. Field_rbit2_Slot_inst_get,
  11888. Field_rhi_Slot_inst_get,
  11889. Field_t3_Slot_inst_get,
  11890. Field_tbit2_Slot_inst_get,
  11891. Field_tlo_Slot_inst_get,
  11892. Field_w_Slot_inst_get,
  11893. Field_y_Slot_inst_get,
  11894. Field_x_Slot_inst_get,
  11895. Field_xt_wbr15_imm_Slot_inst_get,
  11896. Field_xt_wbr18_imm_Slot_inst_get,
  11897. Field_bitindex_Slot_inst_get,
  11898. Field_s3to1_Slot_inst_get,
  11899. Implicit_Field_ar0_get,
  11900. Implicit_Field_ar4_get,
  11901. Implicit_Field_ar8_get,
  11902. Implicit_Field_ar12_get,
  11903. Implicit_Field_mr0_get,
  11904. Implicit_Field_mr1_get,
  11905. Implicit_Field_mr2_get,
  11906. Implicit_Field_mr3_get
  11907. };
  11908. static xtensa_set_field_fn
  11909. Slot_inst_set_field_fns[] = {
  11910. Field_t_Slot_inst_set,
  11911. Field_bbi4_Slot_inst_set,
  11912. Field_bbi_Slot_inst_set,
  11913. Field_imm12_Slot_inst_set,
  11914. Field_imm8_Slot_inst_set,
  11915. Field_s_Slot_inst_set,
  11916. Field_imm12b_Slot_inst_set,
  11917. Field_imm16_Slot_inst_set,
  11918. Field_m_Slot_inst_set,
  11919. Field_n_Slot_inst_set,
  11920. Field_offset_Slot_inst_set,
  11921. Field_op0_Slot_inst_set,
  11922. Field_op1_Slot_inst_set,
  11923. Field_op2_Slot_inst_set,
  11924. Field_r_Slot_inst_set,
  11925. Field_sa4_Slot_inst_set,
  11926. Field_sae4_Slot_inst_set,
  11927. Field_sae_Slot_inst_set,
  11928. Field_sal_Slot_inst_set,
  11929. Field_sargt_Slot_inst_set,
  11930. Field_sas4_Slot_inst_set,
  11931. Field_sas_Slot_inst_set,
  11932. Field_sr_Slot_inst_set,
  11933. Field_st_Slot_inst_set,
  11934. Field_thi3_Slot_inst_set,
  11935. Field_imm4_Slot_inst_set,
  11936. Field_mn_Slot_inst_set,
  11937. 0,
  11938. 0,
  11939. 0,
  11940. 0,
  11941. 0,
  11942. 0,
  11943. 0,
  11944. 0,
  11945. Field_r3_Slot_inst_set,
  11946. Field_rbit2_Slot_inst_set,
  11947. Field_rhi_Slot_inst_set,
  11948. Field_t3_Slot_inst_set,
  11949. Field_tbit2_Slot_inst_set,
  11950. Field_tlo_Slot_inst_set,
  11951. Field_w_Slot_inst_set,
  11952. Field_y_Slot_inst_set,
  11953. Field_x_Slot_inst_set,
  11954. Field_xt_wbr15_imm_Slot_inst_set,
  11955. Field_xt_wbr18_imm_Slot_inst_set,
  11956. Field_bitindex_Slot_inst_set,
  11957. Field_s3to1_Slot_inst_set,
  11958. Implicit_Field_set,
  11959. Implicit_Field_set,
  11960. Implicit_Field_set,
  11961. Implicit_Field_set,
  11962. Implicit_Field_set,
  11963. Implicit_Field_set,
  11964. Implicit_Field_set,
  11965. Implicit_Field_set
  11966. };
  11967. static xtensa_get_field_fn
  11968. Slot_inst16a_get_field_fns[] = {
  11969. Field_t_Slot_inst16a_get,
  11970. 0,
  11971. 0,
  11972. 0,
  11973. 0,
  11974. Field_s_Slot_inst16a_get,
  11975. 0,
  11976. 0,
  11977. 0,
  11978. 0,
  11979. 0,
  11980. Field_op0_Slot_inst16a_get,
  11981. 0,
  11982. 0,
  11983. Field_r_Slot_inst16a_get,
  11984. 0,
  11985. 0,
  11986. 0,
  11987. 0,
  11988. 0,
  11989. 0,
  11990. 0,
  11991. Field_sr_Slot_inst16a_get,
  11992. Field_st_Slot_inst16a_get,
  11993. 0,
  11994. Field_imm4_Slot_inst16a_get,
  11995. 0,
  11996. Field_i_Slot_inst16a_get,
  11997. Field_imm6lo_Slot_inst16a_get,
  11998. Field_imm6hi_Slot_inst16a_get,
  11999. Field_imm7lo_Slot_inst16a_get,
  12000. Field_imm7hi_Slot_inst16a_get,
  12001. Field_z_Slot_inst16a_get,
  12002. Field_imm6_Slot_inst16a_get,
  12003. Field_imm7_Slot_inst16a_get,
  12004. 0,
  12005. 0,
  12006. 0,
  12007. 0,
  12008. 0,
  12009. 0,
  12010. 0,
  12011. 0,
  12012. 0,
  12013. 0,
  12014. 0,
  12015. Field_bitindex_Slot_inst16a_get,
  12016. Field_s3to1_Slot_inst16a_get,
  12017. Implicit_Field_ar0_get,
  12018. Implicit_Field_ar4_get,
  12019. Implicit_Field_ar8_get,
  12020. Implicit_Field_ar12_get,
  12021. Implicit_Field_mr0_get,
  12022. Implicit_Field_mr1_get,
  12023. Implicit_Field_mr2_get,
  12024. Implicit_Field_mr3_get
  12025. };
  12026. static xtensa_set_field_fn
  12027. Slot_inst16a_set_field_fns[] = {
  12028. Field_t_Slot_inst16a_set,
  12029. 0,
  12030. 0,
  12031. 0,
  12032. 0,
  12033. Field_s_Slot_inst16a_set,
  12034. 0,
  12035. 0,
  12036. 0,
  12037. 0,
  12038. 0,
  12039. Field_op0_Slot_inst16a_set,
  12040. 0,
  12041. 0,
  12042. Field_r_Slot_inst16a_set,
  12043. 0,
  12044. 0,
  12045. 0,
  12046. 0,
  12047. 0,
  12048. 0,
  12049. 0,
  12050. Field_sr_Slot_inst16a_set,
  12051. Field_st_Slot_inst16a_set,
  12052. 0,
  12053. Field_imm4_Slot_inst16a_set,
  12054. 0,
  12055. Field_i_Slot_inst16a_set,
  12056. Field_imm6lo_Slot_inst16a_set,
  12057. Field_imm6hi_Slot_inst16a_set,
  12058. Field_imm7lo_Slot_inst16a_set,
  12059. Field_imm7hi_Slot_inst16a_set,
  12060. Field_z_Slot_inst16a_set,
  12061. Field_imm6_Slot_inst16a_set,
  12062. Field_imm7_Slot_inst16a_set,
  12063. 0,
  12064. 0,
  12065. 0,
  12066. 0,
  12067. 0,
  12068. 0,
  12069. 0,
  12070. 0,
  12071. 0,
  12072. 0,
  12073. 0,
  12074. Field_bitindex_Slot_inst16a_set,
  12075. Field_s3to1_Slot_inst16a_set,
  12076. Implicit_Field_set,
  12077. Implicit_Field_set,
  12078. Implicit_Field_set,
  12079. Implicit_Field_set,
  12080. Implicit_Field_set,
  12081. Implicit_Field_set,
  12082. Implicit_Field_set,
  12083. Implicit_Field_set
  12084. };
  12085. static xtensa_get_field_fn
  12086. Slot_inst16b_get_field_fns[] = {
  12087. Field_t_Slot_inst16b_get,
  12088. 0,
  12089. 0,
  12090. 0,
  12091. 0,
  12092. Field_s_Slot_inst16b_get,
  12093. 0,
  12094. 0,
  12095. 0,
  12096. 0,
  12097. 0,
  12098. Field_op0_Slot_inst16b_get,
  12099. 0,
  12100. 0,
  12101. Field_r_Slot_inst16b_get,
  12102. 0,
  12103. 0,
  12104. 0,
  12105. 0,
  12106. 0,
  12107. 0,
  12108. 0,
  12109. Field_sr_Slot_inst16b_get,
  12110. Field_st_Slot_inst16b_get,
  12111. 0,
  12112. Field_imm4_Slot_inst16b_get,
  12113. 0,
  12114. Field_i_Slot_inst16b_get,
  12115. Field_imm6lo_Slot_inst16b_get,
  12116. Field_imm6hi_Slot_inst16b_get,
  12117. Field_imm7lo_Slot_inst16b_get,
  12118. Field_imm7hi_Slot_inst16b_get,
  12119. Field_z_Slot_inst16b_get,
  12120. Field_imm6_Slot_inst16b_get,
  12121. Field_imm7_Slot_inst16b_get,
  12122. 0,
  12123. 0,
  12124. 0,
  12125. 0,
  12126. 0,
  12127. 0,
  12128. 0,
  12129. 0,
  12130. 0,
  12131. 0,
  12132. 0,
  12133. Field_bitindex_Slot_inst16b_get,
  12134. Field_s3to1_Slot_inst16b_get,
  12135. Implicit_Field_ar0_get,
  12136. Implicit_Field_ar4_get,
  12137. Implicit_Field_ar8_get,
  12138. Implicit_Field_ar12_get,
  12139. Implicit_Field_mr0_get,
  12140. Implicit_Field_mr1_get,
  12141. Implicit_Field_mr2_get,
  12142. Implicit_Field_mr3_get
  12143. };
  12144. static xtensa_set_field_fn
  12145. Slot_inst16b_set_field_fns[] = {
  12146. Field_t_Slot_inst16b_set,
  12147. 0,
  12148. 0,
  12149. 0,
  12150. 0,
  12151. Field_s_Slot_inst16b_set,
  12152. 0,
  12153. 0,
  12154. 0,
  12155. 0,
  12156. 0,
  12157. Field_op0_Slot_inst16b_set,
  12158. 0,
  12159. 0,
  12160. Field_r_Slot_inst16b_set,
  12161. 0,
  12162. 0,
  12163. 0,
  12164. 0,
  12165. 0,
  12166. 0,
  12167. 0,
  12168. Field_sr_Slot_inst16b_set,
  12169. Field_st_Slot_inst16b_set,
  12170. 0,
  12171. Field_imm4_Slot_inst16b_set,
  12172. 0,
  12173. Field_i_Slot_inst16b_set,
  12174. Field_imm6lo_Slot_inst16b_set,
  12175. Field_imm6hi_Slot_inst16b_set,
  12176. Field_imm7lo_Slot_inst16b_set,
  12177. Field_imm7hi_Slot_inst16b_set,
  12178. Field_z_Slot_inst16b_set,
  12179. Field_imm6_Slot_inst16b_set,
  12180. Field_imm7_Slot_inst16b_set,
  12181. 0,
  12182. 0,
  12183. 0,
  12184. 0,
  12185. 0,
  12186. 0,
  12187. 0,
  12188. 0,
  12189. 0,
  12190. 0,
  12191. 0,
  12192. Field_bitindex_Slot_inst16b_set,
  12193. Field_s3to1_Slot_inst16b_set,
  12194. Implicit_Field_set,
  12195. Implicit_Field_set,
  12196. Implicit_Field_set,
  12197. Implicit_Field_set,
  12198. Implicit_Field_set,
  12199. Implicit_Field_set,
  12200. Implicit_Field_set,
  12201. Implicit_Field_set
  12202. };
  12203. static xtensa_slot_internal slots[] = {
  12204. { "Inst", "x24", 0,
  12205. Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
  12206. Slot_inst_get_field_fns, Slot_inst_set_field_fns,
  12207. Slot_inst_decode, "nop" },
  12208. { "Inst16a", "x16a", 0,
  12209. Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
  12210. Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
  12211. Slot_inst16a_decode, "" },
  12212. { "Inst16b", "x16b", 0,
  12213. Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
  12214. Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
  12215. Slot_inst16b_decode, "nop.n" }
  12216. };
  12217. /* Instruction formats. */
  12218. static void
  12219. Format_x24_encode (xtensa_insnbuf insn)
  12220. {
  12221. insn[0] = 0;
  12222. }
  12223. static void
  12224. Format_x16a_encode (xtensa_insnbuf insn)
  12225. {
  12226. insn[0] = 0x8;
  12227. }
  12228. static void
  12229. Format_x16b_encode (xtensa_insnbuf insn)
  12230. {
  12231. insn[0] = 0xc;
  12232. }
  12233. static int Format_x24_slots[] = { 0 };
  12234. static int Format_x16a_slots[] = { 1 };
  12235. static int Format_x16b_slots[] = { 2 };
  12236. static xtensa_format_internal formats[] = {
  12237. { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
  12238. { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
  12239. { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
  12240. };
  12241. static int
  12242. format_decoder (const xtensa_insnbuf insn)
  12243. {
  12244. if ((insn[0] & 0x8) == 0)
  12245. return 0; /* x24 */
  12246. if ((insn[0] & 0xc) == 0x8)
  12247. return 1; /* x16a */
  12248. if ((insn[0] & 0xe) == 0xc)
  12249. return 2; /* x16b */
  12250. return -1;
  12251. }
  12252. static int length_table[16] = {
  12253. 3,
  12254. 3,
  12255. 3,
  12256. 3,
  12257. 3,
  12258. 3,
  12259. 3,
  12260. 3,
  12261. 2,
  12262. 2,
  12263. 2,
  12264. 2,
  12265. 2,
  12266. 2,
  12267. -1,
  12268. -1
  12269. };
  12270. static int
  12271. length_decoder (const unsigned char *insn)
  12272. {
  12273. int op0 = insn[0] & 0xf;
  12274. return length_table[op0];
  12275. }
  12276. /* Top-level ISA structure. */
  12277. xtensa_isa_internal xtensa_modules = {
  12278. 0 /* little-endian */,
  12279. 3 /* insn_size */, 0,
  12280. 3, formats, format_decoder, length_decoder,
  12281. 3, slots,
  12282. 56 /* num_fields */,
  12283. 93, operands,
  12284. 320, iclasses,
  12285. 446, opcodes, 0,
  12286. 2, regfiles,
  12287. NUM_STATES, states, 0,
  12288. NUM_SYSREGS, sysregs, 0,
  12289. { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
  12290. 1, interfaces, 0,
  12291. 0, funcUnits, 0
  12292. };