translate.c 90 KB

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  1. /*
  2. * CRIS emulation for qemu: main translation routines.
  3. *
  4. * Copyright (c) 2008 AXIS Communications AB
  5. * Written by Edgar E. Iglesias.
  6. *
  7. * This library is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU Lesser General Public
  9. * License as published by the Free Software Foundation; either
  10. * version 2 of the License, or (at your option) any later version.
  11. *
  12. * This library is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * Lesser General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU Lesser General Public
  18. * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19. */
  20. /*
  21. * FIXME:
  22. * The condition code translation is in need of attention.
  23. */
  24. #include "qemu/osdep.h"
  25. #include "cpu.h"
  26. #include "disas/disas.h"
  27. #include "exec/exec-all.h"
  28. #include "tcg/tcg-op.h"
  29. #include "exec/helper-proto.h"
  30. #include "mmu.h"
  31. #include "exec/cpu_ldst.h"
  32. #include "exec/translator.h"
  33. #include "crisv32-decode.h"
  34. #include "qemu/qemu-print.h"
  35. #include "exec/helper-gen.h"
  36. #include "trace-tcg.h"
  37. #include "exec/log.h"
  38. #define DISAS_CRIS 0
  39. #if DISAS_CRIS
  40. # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
  41. #else
  42. # define LOG_DIS(...) do { } while (0)
  43. #endif
  44. #define D(x)
  45. #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
  46. #define BUG_ON(x) ({if (x) BUG();})
  47. /* is_jmp field values */
  48. #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
  49. #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
  50. #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
  51. #define DISAS_SWI DISAS_TARGET_3
  52. /* Used by the decoder. */
  53. #define EXTRACT_FIELD(src, start, end) \
  54. (((src) >> start) & ((1 << (end - start + 1)) - 1))
  55. #define CC_MASK_NZ 0xc
  56. #define CC_MASK_NZV 0xe
  57. #define CC_MASK_NZVC 0xf
  58. #define CC_MASK_RNZV 0x10e
  59. static TCGv cpu_R[16];
  60. static TCGv cpu_PR[16];
  61. static TCGv cc_x;
  62. static TCGv cc_src;
  63. static TCGv cc_dest;
  64. static TCGv cc_result;
  65. static TCGv cc_op;
  66. static TCGv cc_size;
  67. static TCGv cc_mask;
  68. static TCGv env_btaken;
  69. static TCGv env_btarget;
  70. static TCGv env_pc;
  71. #include "exec/gen-icount.h"
  72. /* This is the state at translation time. */
  73. typedef struct DisasContext {
  74. CRISCPU *cpu;
  75. target_ulong pc, ppc;
  76. /* Decoder. */
  77. unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
  78. uint32_t ir;
  79. uint32_t opcode;
  80. unsigned int op1;
  81. unsigned int op2;
  82. unsigned int zsize, zzsize;
  83. unsigned int mode;
  84. unsigned int postinc;
  85. unsigned int size;
  86. unsigned int src;
  87. unsigned int dst;
  88. unsigned int cond;
  89. int update_cc;
  90. int cc_op;
  91. int cc_size;
  92. uint32_t cc_mask;
  93. int cc_size_uptodate; /* -1 invalid or last written value. */
  94. int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
  95. int flags_uptodate; /* Whether or not $ccs is up-to-date. */
  96. int flagx_known; /* Whether or not flags_x has the x flag known at
  97. translation time. */
  98. int flags_x;
  99. int clear_x; /* Clear x after this insn? */
  100. int clear_prefix; /* Clear prefix after this insn? */
  101. int clear_locked_irq; /* Clear the irq lockout. */
  102. int cpustate_changed;
  103. unsigned int tb_flags; /* tb dependent flags. */
  104. int is_jmp;
  105. #define JMP_NOJMP 0
  106. #define JMP_DIRECT 1
  107. #define JMP_DIRECT_CC 2
  108. #define JMP_INDIRECT 3
  109. int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
  110. uint32_t jmp_pc;
  111. int delayed_branch;
  112. struct TranslationBlock *tb;
  113. int singlestep_enabled;
  114. } DisasContext;
  115. static void gen_BUG(DisasContext *dc, const char *file, int line)
  116. {
  117. cpu_abort(CPU(dc->cpu), "%s:%d pc=%x\n", file, line, dc->pc);
  118. }
  119. static const char *regnames_v32[] =
  120. {
  121. "$r0", "$r1", "$r2", "$r3",
  122. "$r4", "$r5", "$r6", "$r7",
  123. "$r8", "$r9", "$r10", "$r11",
  124. "$r12", "$r13", "$sp", "$acr",
  125. };
  126. static const char *pregnames_v32[] =
  127. {
  128. "$bz", "$vr", "$pid", "$srs",
  129. "$wz", "$exs", "$eda", "$mof",
  130. "$dz", "$ebp", "$erp", "$srp",
  131. "$nrp", "$ccs", "$usp", "$spc",
  132. };
  133. /* We need this table to handle preg-moves with implicit width. */
  134. static int preg_sizes[] = {
  135. 1, /* bz. */
  136. 1, /* vr. */
  137. 4, /* pid. */
  138. 1, /* srs. */
  139. 2, /* wz. */
  140. 4, 4, 4,
  141. 4, 4, 4, 4,
  142. 4, 4, 4, 4,
  143. };
  144. #define t_gen_mov_TN_env(tn, member) \
  145. tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
  146. #define t_gen_mov_env_TN(member, tn) \
  147. tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
  148. static inline void t_gen_mov_TN_preg(TCGv tn, int r)
  149. {
  150. assert(r >= 0 && r <= 15);
  151. if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
  152. tcg_gen_mov_tl(tn, tcg_const_tl(0));
  153. } else if (r == PR_VR) {
  154. tcg_gen_mov_tl(tn, tcg_const_tl(32));
  155. } else {
  156. tcg_gen_mov_tl(tn, cpu_PR[r]);
  157. }
  158. }
  159. static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
  160. {
  161. assert(r >= 0 && r <= 15);
  162. if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
  163. return;
  164. } else if (r == PR_SRS) {
  165. tcg_gen_andi_tl(cpu_PR[r], tn, 3);
  166. } else {
  167. if (r == PR_PID) {
  168. gen_helper_tlb_flush_pid(cpu_env, tn);
  169. }
  170. if (dc->tb_flags & S_FLAG && r == PR_SPC) {
  171. gen_helper_spc_write(cpu_env, tn);
  172. } else if (r == PR_CCS) {
  173. dc->cpustate_changed = 1;
  174. }
  175. tcg_gen_mov_tl(cpu_PR[r], tn);
  176. }
  177. }
  178. /* Sign extend at translation time. */
  179. static int sign_extend(unsigned int val, unsigned int width)
  180. {
  181. int sval;
  182. /* LSL. */
  183. val <<= 31 - width;
  184. sval = val;
  185. /* ASR. */
  186. sval >>= 31 - width;
  187. return sval;
  188. }
  189. static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
  190. unsigned int size, unsigned int sign)
  191. {
  192. int r;
  193. switch (size) {
  194. case 4:
  195. {
  196. r = cpu_ldl_code(env, addr);
  197. break;
  198. }
  199. case 2:
  200. {
  201. if (sign) {
  202. r = cpu_ldsw_code(env, addr);
  203. } else {
  204. r = cpu_lduw_code(env, addr);
  205. }
  206. break;
  207. }
  208. case 1:
  209. {
  210. if (sign) {
  211. r = cpu_ldsb_code(env, addr);
  212. } else {
  213. r = cpu_ldub_code(env, addr);
  214. }
  215. break;
  216. }
  217. default:
  218. cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
  219. break;
  220. }
  221. return r;
  222. }
  223. static void cris_lock_irq(DisasContext *dc)
  224. {
  225. dc->clear_locked_irq = 0;
  226. t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
  227. }
  228. static inline void t_gen_raise_exception(uint32_t index)
  229. {
  230. TCGv_i32 tmp = tcg_const_i32(index);
  231. gen_helper_raise_exception(cpu_env, tmp);
  232. tcg_temp_free_i32(tmp);
  233. }
  234. static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
  235. {
  236. TCGv t0, t_31;
  237. t0 = tcg_temp_new();
  238. t_31 = tcg_const_tl(31);
  239. tcg_gen_shl_tl(d, a, b);
  240. tcg_gen_sub_tl(t0, t_31, b);
  241. tcg_gen_sar_tl(t0, t0, t_31);
  242. tcg_gen_and_tl(t0, t0, d);
  243. tcg_gen_xor_tl(d, d, t0);
  244. tcg_temp_free(t0);
  245. tcg_temp_free(t_31);
  246. }
  247. static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
  248. {
  249. TCGv t0, t_31;
  250. t0 = tcg_temp_new();
  251. t_31 = tcg_temp_new();
  252. tcg_gen_shr_tl(d, a, b);
  253. tcg_gen_movi_tl(t_31, 31);
  254. tcg_gen_sub_tl(t0, t_31, b);
  255. tcg_gen_sar_tl(t0, t0, t_31);
  256. tcg_gen_and_tl(t0, t0, d);
  257. tcg_gen_xor_tl(d, d, t0);
  258. tcg_temp_free(t0);
  259. tcg_temp_free(t_31);
  260. }
  261. static void t_gen_asr(TCGv d, TCGv a, TCGv b)
  262. {
  263. TCGv t0, t_31;
  264. t0 = tcg_temp_new();
  265. t_31 = tcg_temp_new();
  266. tcg_gen_sar_tl(d, a, b);
  267. tcg_gen_movi_tl(t_31, 31);
  268. tcg_gen_sub_tl(t0, t_31, b);
  269. tcg_gen_sar_tl(t0, t0, t_31);
  270. tcg_gen_or_tl(d, d, t0);
  271. tcg_temp_free(t0);
  272. tcg_temp_free(t_31);
  273. }
  274. static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
  275. {
  276. TCGv t = tcg_temp_new();
  277. /*
  278. * d <<= 1
  279. * if (d >= s)
  280. * d -= s;
  281. */
  282. tcg_gen_shli_tl(d, a, 1);
  283. tcg_gen_sub_tl(t, d, b);
  284. tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d);
  285. tcg_temp_free(t);
  286. }
  287. static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
  288. {
  289. TCGv t;
  290. /*
  291. * d <<= 1
  292. * if (n)
  293. * d += s;
  294. */
  295. t = tcg_temp_new();
  296. tcg_gen_shli_tl(d, a, 1);
  297. tcg_gen_shli_tl(t, ccs, 31 - 3);
  298. tcg_gen_sari_tl(t, t, 31);
  299. tcg_gen_and_tl(t, t, b);
  300. tcg_gen_add_tl(d, d, t);
  301. tcg_temp_free(t);
  302. }
  303. /* Extended arithmetics on CRIS. */
  304. static inline void t_gen_add_flag(TCGv d, int flag)
  305. {
  306. TCGv c;
  307. c = tcg_temp_new();
  308. t_gen_mov_TN_preg(c, PR_CCS);
  309. /* Propagate carry into d. */
  310. tcg_gen_andi_tl(c, c, 1 << flag);
  311. if (flag) {
  312. tcg_gen_shri_tl(c, c, flag);
  313. }
  314. tcg_gen_add_tl(d, d, c);
  315. tcg_temp_free(c);
  316. }
  317. static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
  318. {
  319. if (dc->flagx_known) {
  320. if (dc->flags_x) {
  321. TCGv c;
  322. c = tcg_temp_new();
  323. t_gen_mov_TN_preg(c, PR_CCS);
  324. /* C flag is already at bit 0. */
  325. tcg_gen_andi_tl(c, c, C_FLAG);
  326. tcg_gen_add_tl(d, d, c);
  327. tcg_temp_free(c);
  328. }
  329. } else {
  330. TCGv x, c;
  331. x = tcg_temp_new();
  332. c = tcg_temp_new();
  333. t_gen_mov_TN_preg(x, PR_CCS);
  334. tcg_gen_mov_tl(c, x);
  335. /* Propagate carry into d if X is set. Branch free. */
  336. tcg_gen_andi_tl(c, c, C_FLAG);
  337. tcg_gen_andi_tl(x, x, X_FLAG);
  338. tcg_gen_shri_tl(x, x, 4);
  339. tcg_gen_and_tl(x, x, c);
  340. tcg_gen_add_tl(d, d, x);
  341. tcg_temp_free(x);
  342. tcg_temp_free(c);
  343. }
  344. }
  345. static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
  346. {
  347. if (dc->flagx_known) {
  348. if (dc->flags_x) {
  349. TCGv c;
  350. c = tcg_temp_new();
  351. t_gen_mov_TN_preg(c, PR_CCS);
  352. /* C flag is already at bit 0. */
  353. tcg_gen_andi_tl(c, c, C_FLAG);
  354. tcg_gen_sub_tl(d, d, c);
  355. tcg_temp_free(c);
  356. }
  357. } else {
  358. TCGv x, c;
  359. x = tcg_temp_new();
  360. c = tcg_temp_new();
  361. t_gen_mov_TN_preg(x, PR_CCS);
  362. tcg_gen_mov_tl(c, x);
  363. /* Propagate carry into d if X is set. Branch free. */
  364. tcg_gen_andi_tl(c, c, C_FLAG);
  365. tcg_gen_andi_tl(x, x, X_FLAG);
  366. tcg_gen_shri_tl(x, x, 4);
  367. tcg_gen_and_tl(x, x, c);
  368. tcg_gen_sub_tl(d, d, x);
  369. tcg_temp_free(x);
  370. tcg_temp_free(c);
  371. }
  372. }
  373. /* Swap the two bytes within each half word of the s operand.
  374. T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
  375. static inline void t_gen_swapb(TCGv d, TCGv s)
  376. {
  377. TCGv t, org_s;
  378. t = tcg_temp_new();
  379. org_s = tcg_temp_new();
  380. /* d and s may refer to the same object. */
  381. tcg_gen_mov_tl(org_s, s);
  382. tcg_gen_shli_tl(t, org_s, 8);
  383. tcg_gen_andi_tl(d, t, 0xff00ff00);
  384. tcg_gen_shri_tl(t, org_s, 8);
  385. tcg_gen_andi_tl(t, t, 0x00ff00ff);
  386. tcg_gen_or_tl(d, d, t);
  387. tcg_temp_free(t);
  388. tcg_temp_free(org_s);
  389. }
  390. /* Swap the halfwords of the s operand. */
  391. static inline void t_gen_swapw(TCGv d, TCGv s)
  392. {
  393. TCGv t;
  394. /* d and s refer the same object. */
  395. t = tcg_temp_new();
  396. tcg_gen_mov_tl(t, s);
  397. tcg_gen_shli_tl(d, t, 16);
  398. tcg_gen_shri_tl(t, t, 16);
  399. tcg_gen_or_tl(d, d, t);
  400. tcg_temp_free(t);
  401. }
  402. /* Reverse the within each byte.
  403. T0 = (((T0 << 7) & 0x80808080) |
  404. ((T0 << 5) & 0x40404040) |
  405. ((T0 << 3) & 0x20202020) |
  406. ((T0 << 1) & 0x10101010) |
  407. ((T0 >> 1) & 0x08080808) |
  408. ((T0 >> 3) & 0x04040404) |
  409. ((T0 >> 5) & 0x02020202) |
  410. ((T0 >> 7) & 0x01010101));
  411. */
  412. static inline void t_gen_swapr(TCGv d, TCGv s)
  413. {
  414. struct {
  415. int shift; /* LSL when positive, LSR when negative. */
  416. uint32_t mask;
  417. } bitrev[] = {
  418. {7, 0x80808080},
  419. {5, 0x40404040},
  420. {3, 0x20202020},
  421. {1, 0x10101010},
  422. {-1, 0x08080808},
  423. {-3, 0x04040404},
  424. {-5, 0x02020202},
  425. {-7, 0x01010101}
  426. };
  427. int i;
  428. TCGv t, org_s;
  429. /* d and s refer the same object. */
  430. t = tcg_temp_new();
  431. org_s = tcg_temp_new();
  432. tcg_gen_mov_tl(org_s, s);
  433. tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
  434. tcg_gen_andi_tl(d, t, bitrev[0].mask);
  435. for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
  436. if (bitrev[i].shift >= 0) {
  437. tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
  438. } else {
  439. tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
  440. }
  441. tcg_gen_andi_tl(t, t, bitrev[i].mask);
  442. tcg_gen_or_tl(d, d, t);
  443. }
  444. tcg_temp_free(t);
  445. tcg_temp_free(org_s);
  446. }
  447. static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
  448. {
  449. TCGLabel *l1 = gen_new_label();
  450. /* Conditional jmp. */
  451. tcg_gen_mov_tl(env_pc, pc_false);
  452. tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
  453. tcg_gen_mov_tl(env_pc, pc_true);
  454. gen_set_label(l1);
  455. }
  456. static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
  457. {
  458. #ifndef CONFIG_USER_ONLY
  459. return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
  460. (dc->ppc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
  461. #else
  462. return true;
  463. #endif
  464. }
  465. static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
  466. {
  467. if (use_goto_tb(dc, dest)) {
  468. tcg_gen_goto_tb(n);
  469. tcg_gen_movi_tl(env_pc, dest);
  470. tcg_gen_exit_tb(dc->tb, n);
  471. } else {
  472. tcg_gen_movi_tl(env_pc, dest);
  473. tcg_gen_exit_tb(NULL, 0);
  474. }
  475. }
  476. static inline void cris_clear_x_flag(DisasContext *dc)
  477. {
  478. if (dc->flagx_known && dc->flags_x) {
  479. dc->flags_uptodate = 0;
  480. }
  481. dc->flagx_known = 1;
  482. dc->flags_x = 0;
  483. }
  484. static void cris_flush_cc_state(DisasContext *dc)
  485. {
  486. if (dc->cc_size_uptodate != dc->cc_size) {
  487. tcg_gen_movi_tl(cc_size, dc->cc_size);
  488. dc->cc_size_uptodate = dc->cc_size;
  489. }
  490. tcg_gen_movi_tl(cc_op, dc->cc_op);
  491. tcg_gen_movi_tl(cc_mask, dc->cc_mask);
  492. }
  493. static void cris_evaluate_flags(DisasContext *dc)
  494. {
  495. if (dc->flags_uptodate) {
  496. return;
  497. }
  498. cris_flush_cc_state(dc);
  499. switch (dc->cc_op) {
  500. case CC_OP_MCP:
  501. gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
  502. cpu_PR[PR_CCS], cc_src,
  503. cc_dest, cc_result);
  504. break;
  505. case CC_OP_MULS:
  506. gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
  507. cpu_PR[PR_CCS], cc_result,
  508. cpu_PR[PR_MOF]);
  509. break;
  510. case CC_OP_MULU:
  511. gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
  512. cpu_PR[PR_CCS], cc_result,
  513. cpu_PR[PR_MOF]);
  514. break;
  515. case CC_OP_MOVE:
  516. case CC_OP_AND:
  517. case CC_OP_OR:
  518. case CC_OP_XOR:
  519. case CC_OP_ASR:
  520. case CC_OP_LSR:
  521. case CC_OP_LSL:
  522. switch (dc->cc_size) {
  523. case 4:
  524. gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
  525. cpu_env, cpu_PR[PR_CCS], cc_result);
  526. break;
  527. case 2:
  528. gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
  529. cpu_env, cpu_PR[PR_CCS], cc_result);
  530. break;
  531. default:
  532. gen_helper_evaluate_flags(cpu_env);
  533. break;
  534. }
  535. break;
  536. case CC_OP_FLAGS:
  537. /* live. */
  538. break;
  539. case CC_OP_SUB:
  540. case CC_OP_CMP:
  541. if (dc->cc_size == 4) {
  542. gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
  543. cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
  544. } else {
  545. gen_helper_evaluate_flags(cpu_env);
  546. }
  547. break;
  548. default:
  549. switch (dc->cc_size) {
  550. case 4:
  551. gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
  552. cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
  553. break;
  554. default:
  555. gen_helper_evaluate_flags(cpu_env);
  556. break;
  557. }
  558. break;
  559. }
  560. if (dc->flagx_known) {
  561. if (dc->flags_x) {
  562. tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
  563. } else if (dc->cc_op == CC_OP_FLAGS) {
  564. tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
  565. }
  566. }
  567. dc->flags_uptodate = 1;
  568. }
  569. static void cris_cc_mask(DisasContext *dc, unsigned int mask)
  570. {
  571. uint32_t ovl;
  572. if (!mask) {
  573. dc->update_cc = 0;
  574. return;
  575. }
  576. /* Check if we need to evaluate the condition codes due to
  577. CC overlaying. */
  578. ovl = (dc->cc_mask ^ mask) & ~mask;
  579. if (ovl) {
  580. /* TODO: optimize this case. It trigs all the time. */
  581. cris_evaluate_flags(dc);
  582. }
  583. dc->cc_mask = mask;
  584. dc->update_cc = 1;
  585. }
  586. static void cris_update_cc_op(DisasContext *dc, int op, int size)
  587. {
  588. dc->cc_op = op;
  589. dc->cc_size = size;
  590. dc->flags_uptodate = 0;
  591. }
  592. static inline void cris_update_cc_x(DisasContext *dc)
  593. {
  594. /* Save the x flag state at the time of the cc snapshot. */
  595. if (dc->flagx_known) {
  596. if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
  597. return;
  598. }
  599. tcg_gen_movi_tl(cc_x, dc->flags_x);
  600. dc->cc_x_uptodate = 2 | dc->flags_x;
  601. } else {
  602. tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
  603. dc->cc_x_uptodate = 1;
  604. }
  605. }
  606. /* Update cc prior to executing ALU op. Needs source operands untouched. */
  607. static void cris_pre_alu_update_cc(DisasContext *dc, int op,
  608. TCGv dst, TCGv src, int size)
  609. {
  610. if (dc->update_cc) {
  611. cris_update_cc_op(dc, op, size);
  612. tcg_gen_mov_tl(cc_src, src);
  613. if (op != CC_OP_MOVE
  614. && op != CC_OP_AND
  615. && op != CC_OP_OR
  616. && op != CC_OP_XOR
  617. && op != CC_OP_ASR
  618. && op != CC_OP_LSR
  619. && op != CC_OP_LSL) {
  620. tcg_gen_mov_tl(cc_dest, dst);
  621. }
  622. cris_update_cc_x(dc);
  623. }
  624. }
  625. /* Update cc after executing ALU op. needs the result. */
  626. static inline void cris_update_result(DisasContext *dc, TCGv res)
  627. {
  628. if (dc->update_cc) {
  629. tcg_gen_mov_tl(cc_result, res);
  630. }
  631. }
  632. /* Returns one if the write back stage should execute. */
  633. static void cris_alu_op_exec(DisasContext *dc, int op,
  634. TCGv dst, TCGv a, TCGv b, int size)
  635. {
  636. /* Emit the ALU insns. */
  637. switch (op) {
  638. case CC_OP_ADD:
  639. tcg_gen_add_tl(dst, a, b);
  640. /* Extended arithmetics. */
  641. t_gen_addx_carry(dc, dst);
  642. break;
  643. case CC_OP_ADDC:
  644. tcg_gen_add_tl(dst, a, b);
  645. t_gen_add_flag(dst, 0); /* C_FLAG. */
  646. break;
  647. case CC_OP_MCP:
  648. tcg_gen_add_tl(dst, a, b);
  649. t_gen_add_flag(dst, 8); /* R_FLAG. */
  650. break;
  651. case CC_OP_SUB:
  652. tcg_gen_sub_tl(dst, a, b);
  653. /* Extended arithmetics. */
  654. t_gen_subx_carry(dc, dst);
  655. break;
  656. case CC_OP_MOVE:
  657. tcg_gen_mov_tl(dst, b);
  658. break;
  659. case CC_OP_OR:
  660. tcg_gen_or_tl(dst, a, b);
  661. break;
  662. case CC_OP_AND:
  663. tcg_gen_and_tl(dst, a, b);
  664. break;
  665. case CC_OP_XOR:
  666. tcg_gen_xor_tl(dst, a, b);
  667. break;
  668. case CC_OP_LSL:
  669. t_gen_lsl(dst, a, b);
  670. break;
  671. case CC_OP_LSR:
  672. t_gen_lsr(dst, a, b);
  673. break;
  674. case CC_OP_ASR:
  675. t_gen_asr(dst, a, b);
  676. break;
  677. case CC_OP_NEG:
  678. tcg_gen_neg_tl(dst, b);
  679. /* Extended arithmetics. */
  680. t_gen_subx_carry(dc, dst);
  681. break;
  682. case CC_OP_LZ:
  683. tcg_gen_clzi_tl(dst, b, TARGET_LONG_BITS);
  684. break;
  685. case CC_OP_MULS:
  686. tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
  687. break;
  688. case CC_OP_MULU:
  689. tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
  690. break;
  691. case CC_OP_DSTEP:
  692. t_gen_cris_dstep(dst, a, b);
  693. break;
  694. case CC_OP_MSTEP:
  695. t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
  696. break;
  697. case CC_OP_BOUND:
  698. tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b);
  699. break;
  700. case CC_OP_CMP:
  701. tcg_gen_sub_tl(dst, a, b);
  702. /* Extended arithmetics. */
  703. t_gen_subx_carry(dc, dst);
  704. break;
  705. default:
  706. qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n");
  707. BUG();
  708. break;
  709. }
  710. if (size == 1) {
  711. tcg_gen_andi_tl(dst, dst, 0xff);
  712. } else if (size == 2) {
  713. tcg_gen_andi_tl(dst, dst, 0xffff);
  714. }
  715. }
  716. static void cris_alu(DisasContext *dc, int op,
  717. TCGv d, TCGv op_a, TCGv op_b, int size)
  718. {
  719. TCGv tmp;
  720. int writeback;
  721. writeback = 1;
  722. if (op == CC_OP_CMP) {
  723. tmp = tcg_temp_new();
  724. writeback = 0;
  725. } else if (size == 4) {
  726. tmp = d;
  727. writeback = 0;
  728. } else {
  729. tmp = tcg_temp_new();
  730. }
  731. cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
  732. cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
  733. cris_update_result(dc, tmp);
  734. /* Writeback. */
  735. if (writeback) {
  736. if (size == 1) {
  737. tcg_gen_andi_tl(d, d, ~0xff);
  738. } else {
  739. tcg_gen_andi_tl(d, d, ~0xffff);
  740. }
  741. tcg_gen_or_tl(d, d, tmp);
  742. }
  743. if (tmp != d) {
  744. tcg_temp_free(tmp);
  745. }
  746. }
  747. static int arith_cc(DisasContext *dc)
  748. {
  749. if (dc->update_cc) {
  750. switch (dc->cc_op) {
  751. case CC_OP_ADDC: return 1;
  752. case CC_OP_ADD: return 1;
  753. case CC_OP_SUB: return 1;
  754. case CC_OP_DSTEP: return 1;
  755. case CC_OP_LSL: return 1;
  756. case CC_OP_LSR: return 1;
  757. case CC_OP_ASR: return 1;
  758. case CC_OP_CMP: return 1;
  759. case CC_OP_NEG: return 1;
  760. case CC_OP_OR: return 1;
  761. case CC_OP_AND: return 1;
  762. case CC_OP_XOR: return 1;
  763. case CC_OP_MULU: return 1;
  764. case CC_OP_MULS: return 1;
  765. default:
  766. return 0;
  767. }
  768. }
  769. return 0;
  770. }
  771. static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
  772. {
  773. int arith_opt, move_opt;
  774. /* TODO: optimize more condition codes. */
  775. /*
  776. * If the flags are live, we've gotta look into the bits of CCS.
  777. * Otherwise, if we just did an arithmetic operation we try to
  778. * evaluate the condition code faster.
  779. *
  780. * When this function is done, T0 should be non-zero if the condition
  781. * code is true.
  782. */
  783. arith_opt = arith_cc(dc) && !dc->flags_uptodate;
  784. move_opt = (dc->cc_op == CC_OP_MOVE);
  785. switch (cond) {
  786. case CC_EQ:
  787. if ((arith_opt || move_opt)
  788. && dc->cc_x_uptodate != (2 | X_FLAG)) {
  789. tcg_gen_setcond_tl(TCG_COND_EQ, cc,
  790. cc_result, tcg_const_tl(0));
  791. } else {
  792. cris_evaluate_flags(dc);
  793. tcg_gen_andi_tl(cc,
  794. cpu_PR[PR_CCS], Z_FLAG);
  795. }
  796. break;
  797. case CC_NE:
  798. if ((arith_opt || move_opt)
  799. && dc->cc_x_uptodate != (2 | X_FLAG)) {
  800. tcg_gen_mov_tl(cc, cc_result);
  801. } else {
  802. cris_evaluate_flags(dc);
  803. tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
  804. Z_FLAG);
  805. tcg_gen_andi_tl(cc, cc, Z_FLAG);
  806. }
  807. break;
  808. case CC_CS:
  809. cris_evaluate_flags(dc);
  810. tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
  811. break;
  812. case CC_CC:
  813. cris_evaluate_flags(dc);
  814. tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
  815. tcg_gen_andi_tl(cc, cc, C_FLAG);
  816. break;
  817. case CC_VS:
  818. cris_evaluate_flags(dc);
  819. tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
  820. break;
  821. case CC_VC:
  822. cris_evaluate_flags(dc);
  823. tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
  824. V_FLAG);
  825. tcg_gen_andi_tl(cc, cc, V_FLAG);
  826. break;
  827. case CC_PL:
  828. if (arith_opt || move_opt) {
  829. int bits = 31;
  830. if (dc->cc_size == 1) {
  831. bits = 7;
  832. } else if (dc->cc_size == 2) {
  833. bits = 15;
  834. }
  835. tcg_gen_shri_tl(cc, cc_result, bits);
  836. tcg_gen_xori_tl(cc, cc, 1);
  837. } else {
  838. cris_evaluate_flags(dc);
  839. tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
  840. N_FLAG);
  841. tcg_gen_andi_tl(cc, cc, N_FLAG);
  842. }
  843. break;
  844. case CC_MI:
  845. if (arith_opt || move_opt) {
  846. int bits = 31;
  847. if (dc->cc_size == 1) {
  848. bits = 7;
  849. } else if (dc->cc_size == 2) {
  850. bits = 15;
  851. }
  852. tcg_gen_shri_tl(cc, cc_result, bits);
  853. tcg_gen_andi_tl(cc, cc, 1);
  854. } else {
  855. cris_evaluate_flags(dc);
  856. tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
  857. N_FLAG);
  858. }
  859. break;
  860. case CC_LS:
  861. cris_evaluate_flags(dc);
  862. tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
  863. C_FLAG | Z_FLAG);
  864. break;
  865. case CC_HI:
  866. cris_evaluate_flags(dc);
  867. {
  868. TCGv tmp;
  869. tmp = tcg_temp_new();
  870. tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
  871. C_FLAG | Z_FLAG);
  872. /* Overlay the C flag on top of the Z. */
  873. tcg_gen_shli_tl(cc, tmp, 2);
  874. tcg_gen_and_tl(cc, tmp, cc);
  875. tcg_gen_andi_tl(cc, cc, Z_FLAG);
  876. tcg_temp_free(tmp);
  877. }
  878. break;
  879. case CC_GE:
  880. cris_evaluate_flags(dc);
  881. /* Overlay the V flag on top of the N. */
  882. tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
  883. tcg_gen_xor_tl(cc,
  884. cpu_PR[PR_CCS], cc);
  885. tcg_gen_andi_tl(cc, cc, N_FLAG);
  886. tcg_gen_xori_tl(cc, cc, N_FLAG);
  887. break;
  888. case CC_LT:
  889. cris_evaluate_flags(dc);
  890. /* Overlay the V flag on top of the N. */
  891. tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
  892. tcg_gen_xor_tl(cc,
  893. cpu_PR[PR_CCS], cc);
  894. tcg_gen_andi_tl(cc, cc, N_FLAG);
  895. break;
  896. case CC_GT:
  897. cris_evaluate_flags(dc);
  898. {
  899. TCGv n, z;
  900. n = tcg_temp_new();
  901. z = tcg_temp_new();
  902. /* To avoid a shift we overlay everything on
  903. the V flag. */
  904. tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
  905. tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
  906. /* invert Z. */
  907. tcg_gen_xori_tl(z, z, 2);
  908. tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
  909. tcg_gen_xori_tl(n, n, 2);
  910. tcg_gen_and_tl(cc, z, n);
  911. tcg_gen_andi_tl(cc, cc, 2);
  912. tcg_temp_free(n);
  913. tcg_temp_free(z);
  914. }
  915. break;
  916. case CC_LE:
  917. cris_evaluate_flags(dc);
  918. {
  919. TCGv n, z;
  920. n = tcg_temp_new();
  921. z = tcg_temp_new();
  922. /* To avoid a shift we overlay everything on
  923. the V flag. */
  924. tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
  925. tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
  926. tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
  927. tcg_gen_or_tl(cc, z, n);
  928. tcg_gen_andi_tl(cc, cc, 2);
  929. tcg_temp_free(n);
  930. tcg_temp_free(z);
  931. }
  932. break;
  933. case CC_P:
  934. cris_evaluate_flags(dc);
  935. tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
  936. break;
  937. case CC_A:
  938. tcg_gen_movi_tl(cc, 1);
  939. break;
  940. default:
  941. BUG();
  942. break;
  943. };
  944. }
  945. static void cris_store_direct_jmp(DisasContext *dc)
  946. {
  947. /* Store the direct jmp state into the cpu-state. */
  948. if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
  949. if (dc->jmp == JMP_DIRECT) {
  950. tcg_gen_movi_tl(env_btaken, 1);
  951. }
  952. tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
  953. dc->jmp = JMP_INDIRECT;
  954. }
  955. }
  956. static void cris_prepare_cc_branch (DisasContext *dc,
  957. int offset, int cond)
  958. {
  959. /* This helps us re-schedule the micro-code to insns in delay-slots
  960. before the actual jump. */
  961. dc->delayed_branch = 2;
  962. dc->jmp = JMP_DIRECT_CC;
  963. dc->jmp_pc = dc->pc + offset;
  964. gen_tst_cc(dc, env_btaken, cond);
  965. tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
  966. }
  967. /* jumps, when the dest is in a live reg for example. Direct should be set
  968. when the dest addr is constant to allow tb chaining. */
  969. static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
  970. {
  971. /* This helps us re-schedule the micro-code to insns in delay-slots
  972. before the actual jump. */
  973. dc->delayed_branch = 2;
  974. dc->jmp = type;
  975. if (type == JMP_INDIRECT) {
  976. tcg_gen_movi_tl(env_btaken, 1);
  977. }
  978. }
  979. static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
  980. {
  981. int mem_index = cpu_mmu_index(&dc->cpu->env, false);
  982. /* If we get a fault on a delayslot we must keep the jmp state in
  983. the cpu-state to be able to re-execute the jmp. */
  984. if (dc->delayed_branch == 1) {
  985. cris_store_direct_jmp(dc);
  986. }
  987. tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
  988. }
  989. static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
  990. unsigned int size, int sign)
  991. {
  992. int mem_index = cpu_mmu_index(&dc->cpu->env, false);
  993. /* If we get a fault on a delayslot we must keep the jmp state in
  994. the cpu-state to be able to re-execute the jmp. */
  995. if (dc->delayed_branch == 1) {
  996. cris_store_direct_jmp(dc);
  997. }
  998. tcg_gen_qemu_ld_tl(dst, addr, mem_index,
  999. MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
  1000. }
  1001. static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
  1002. unsigned int size)
  1003. {
  1004. int mem_index = cpu_mmu_index(&dc->cpu->env, false);
  1005. /* If we get a fault on a delayslot we must keep the jmp state in
  1006. the cpu-state to be able to re-execute the jmp. */
  1007. if (dc->delayed_branch == 1) {
  1008. cris_store_direct_jmp(dc);
  1009. }
  1010. /* Conditional writes. We only support the kind were X and P are known
  1011. at translation time. */
  1012. if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
  1013. dc->postinc = 0;
  1014. cris_evaluate_flags(dc);
  1015. tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
  1016. return;
  1017. }
  1018. tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
  1019. if (dc->flagx_known && dc->flags_x) {
  1020. cris_evaluate_flags(dc);
  1021. tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
  1022. }
  1023. }
  1024. static inline void t_gen_sext(TCGv d, TCGv s, int size)
  1025. {
  1026. if (size == 1) {
  1027. tcg_gen_ext8s_i32(d, s);
  1028. } else if (size == 2) {
  1029. tcg_gen_ext16s_i32(d, s);
  1030. } else {
  1031. tcg_gen_mov_tl(d, s);
  1032. }
  1033. }
  1034. static inline void t_gen_zext(TCGv d, TCGv s, int size)
  1035. {
  1036. if (size == 1) {
  1037. tcg_gen_ext8u_i32(d, s);
  1038. } else if (size == 2) {
  1039. tcg_gen_ext16u_i32(d, s);
  1040. } else {
  1041. tcg_gen_mov_tl(d, s);
  1042. }
  1043. }
  1044. #if DISAS_CRIS
  1045. static char memsize_char(int size)
  1046. {
  1047. switch (size) {
  1048. case 1: return 'b'; break;
  1049. case 2: return 'w'; break;
  1050. case 4: return 'd'; break;
  1051. default:
  1052. return 'x';
  1053. break;
  1054. }
  1055. }
  1056. #endif
  1057. static inline unsigned int memsize_z(DisasContext *dc)
  1058. {
  1059. return dc->zsize + 1;
  1060. }
  1061. static inline unsigned int memsize_zz(DisasContext *dc)
  1062. {
  1063. switch (dc->zzsize) {
  1064. case 0: return 1;
  1065. case 1: return 2;
  1066. default:
  1067. return 4;
  1068. }
  1069. }
  1070. static inline void do_postinc (DisasContext *dc, int size)
  1071. {
  1072. if (dc->postinc) {
  1073. tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
  1074. }
  1075. }
  1076. static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
  1077. int size, int s_ext, TCGv dst)
  1078. {
  1079. if (s_ext) {
  1080. t_gen_sext(dst, cpu_R[rs], size);
  1081. } else {
  1082. t_gen_zext(dst, cpu_R[rs], size);
  1083. }
  1084. }
  1085. /* Prepare T0 and T1 for a register alu operation.
  1086. s_ext decides if the operand1 should be sign-extended or zero-extended when
  1087. needed. */
  1088. static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
  1089. int size, int s_ext, TCGv dst, TCGv src)
  1090. {
  1091. dec_prep_move_r(dc, rs, rd, size, s_ext, src);
  1092. if (s_ext) {
  1093. t_gen_sext(dst, cpu_R[rd], size);
  1094. } else {
  1095. t_gen_zext(dst, cpu_R[rd], size);
  1096. }
  1097. }
  1098. static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
  1099. int s_ext, int memsize, TCGv dst)
  1100. {
  1101. unsigned int rs;
  1102. uint32_t imm;
  1103. int is_imm;
  1104. int insn_len = 2;
  1105. rs = dc->op1;
  1106. is_imm = rs == 15 && dc->postinc;
  1107. /* Load [$rs] onto T1. */
  1108. if (is_imm) {
  1109. insn_len = 2 + memsize;
  1110. if (memsize == 1) {
  1111. insn_len++;
  1112. }
  1113. imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
  1114. tcg_gen_movi_tl(dst, imm);
  1115. dc->postinc = 0;
  1116. } else {
  1117. cris_flush_cc_state(dc);
  1118. gen_load(dc, dst, cpu_R[rs], memsize, 0);
  1119. if (s_ext) {
  1120. t_gen_sext(dst, dst, memsize);
  1121. } else {
  1122. t_gen_zext(dst, dst, memsize);
  1123. }
  1124. }
  1125. return insn_len;
  1126. }
  1127. /* Prepare T0 and T1 for a memory + alu operation.
  1128. s_ext decides if the operand1 should be sign-extended or zero-extended when
  1129. needed. */
  1130. static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
  1131. int s_ext, int memsize, TCGv dst, TCGv src)
  1132. {
  1133. int insn_len;
  1134. insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
  1135. tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
  1136. return insn_len;
  1137. }
  1138. #if DISAS_CRIS
  1139. static const char *cc_name(int cc)
  1140. {
  1141. static const char *cc_names[16] = {
  1142. "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
  1143. "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
  1144. };
  1145. assert(cc < 16);
  1146. return cc_names[cc];
  1147. }
  1148. #endif
  1149. /* Start of insn decoders. */
  1150. static int dec_bccq(CPUCRISState *env, DisasContext *dc)
  1151. {
  1152. int32_t offset;
  1153. int sign;
  1154. uint32_t cond = dc->op2;
  1155. offset = EXTRACT_FIELD(dc->ir, 1, 7);
  1156. sign = EXTRACT_FIELD(dc->ir, 0, 0);
  1157. offset *= 2;
  1158. offset |= sign << 8;
  1159. offset = sign_extend(offset, 8);
  1160. LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
  1161. /* op2 holds the condition-code. */
  1162. cris_cc_mask(dc, 0);
  1163. cris_prepare_cc_branch(dc, offset, cond);
  1164. return 2;
  1165. }
  1166. static int dec_addoq(CPUCRISState *env, DisasContext *dc)
  1167. {
  1168. int32_t imm;
  1169. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
  1170. imm = sign_extend(dc->op1, 7);
  1171. LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
  1172. cris_cc_mask(dc, 0);
  1173. /* Fetch register operand, */
  1174. tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
  1175. return 2;
  1176. }
  1177. static int dec_addq(CPUCRISState *env, DisasContext *dc)
  1178. {
  1179. LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
  1180. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
  1181. cris_cc_mask(dc, CC_MASK_NZVC);
  1182. cris_alu(dc, CC_OP_ADD,
  1183. cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
  1184. return 2;
  1185. }
  1186. static int dec_moveq(CPUCRISState *env, DisasContext *dc)
  1187. {
  1188. uint32_t imm;
  1189. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
  1190. imm = sign_extend(dc->op1, 5);
  1191. LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
  1192. tcg_gen_movi_tl(cpu_R[dc->op2], imm);
  1193. return 2;
  1194. }
  1195. static int dec_subq(CPUCRISState *env, DisasContext *dc)
  1196. {
  1197. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
  1198. LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
  1199. cris_cc_mask(dc, CC_MASK_NZVC);
  1200. cris_alu(dc, CC_OP_SUB,
  1201. cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
  1202. return 2;
  1203. }
  1204. static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
  1205. {
  1206. uint32_t imm;
  1207. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
  1208. imm = sign_extend(dc->op1, 5);
  1209. LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
  1210. cris_cc_mask(dc, CC_MASK_NZVC);
  1211. cris_alu(dc, CC_OP_CMP,
  1212. cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
  1213. return 2;
  1214. }
  1215. static int dec_andq(CPUCRISState *env, DisasContext *dc)
  1216. {
  1217. uint32_t imm;
  1218. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
  1219. imm = sign_extend(dc->op1, 5);
  1220. LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
  1221. cris_cc_mask(dc, CC_MASK_NZ);
  1222. cris_alu(dc, CC_OP_AND,
  1223. cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
  1224. return 2;
  1225. }
  1226. static int dec_orq(CPUCRISState *env, DisasContext *dc)
  1227. {
  1228. uint32_t imm;
  1229. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
  1230. imm = sign_extend(dc->op1, 5);
  1231. LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
  1232. cris_cc_mask(dc, CC_MASK_NZ);
  1233. cris_alu(dc, CC_OP_OR,
  1234. cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
  1235. return 2;
  1236. }
  1237. static int dec_btstq(CPUCRISState *env, DisasContext *dc)
  1238. {
  1239. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
  1240. LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
  1241. cris_cc_mask(dc, CC_MASK_NZ);
  1242. cris_evaluate_flags(dc);
  1243. gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
  1244. tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
  1245. cris_alu(dc, CC_OP_MOVE,
  1246. cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
  1247. cris_update_cc_op(dc, CC_OP_FLAGS, 4);
  1248. dc->flags_uptodate = 1;
  1249. return 2;
  1250. }
  1251. static int dec_asrq(CPUCRISState *env, DisasContext *dc)
  1252. {
  1253. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
  1254. LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
  1255. cris_cc_mask(dc, CC_MASK_NZ);
  1256. tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
  1257. cris_alu(dc, CC_OP_MOVE,
  1258. cpu_R[dc->op2],
  1259. cpu_R[dc->op2], cpu_R[dc->op2], 4);
  1260. return 2;
  1261. }
  1262. static int dec_lslq(CPUCRISState *env, DisasContext *dc)
  1263. {
  1264. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
  1265. LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
  1266. cris_cc_mask(dc, CC_MASK_NZ);
  1267. tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
  1268. cris_alu(dc, CC_OP_MOVE,
  1269. cpu_R[dc->op2],
  1270. cpu_R[dc->op2], cpu_R[dc->op2], 4);
  1271. return 2;
  1272. }
  1273. static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
  1274. {
  1275. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
  1276. LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
  1277. cris_cc_mask(dc, CC_MASK_NZ);
  1278. tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
  1279. cris_alu(dc, CC_OP_MOVE,
  1280. cpu_R[dc->op2],
  1281. cpu_R[dc->op2], cpu_R[dc->op2], 4);
  1282. return 2;
  1283. }
  1284. static int dec_move_r(CPUCRISState *env, DisasContext *dc)
  1285. {
  1286. int size = memsize_zz(dc);
  1287. LOG_DIS("move.%c $r%u, $r%u\n",
  1288. memsize_char(size), dc->op1, dc->op2);
  1289. cris_cc_mask(dc, CC_MASK_NZ);
  1290. if (size == 4) {
  1291. dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
  1292. cris_cc_mask(dc, CC_MASK_NZ);
  1293. cris_update_cc_op(dc, CC_OP_MOVE, 4);
  1294. cris_update_cc_x(dc);
  1295. cris_update_result(dc, cpu_R[dc->op2]);
  1296. } else {
  1297. TCGv t0;
  1298. t0 = tcg_temp_new();
  1299. dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
  1300. cris_alu(dc, CC_OP_MOVE,
  1301. cpu_R[dc->op2],
  1302. cpu_R[dc->op2], t0, size);
  1303. tcg_temp_free(t0);
  1304. }
  1305. return 2;
  1306. }
  1307. static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
  1308. {
  1309. int cond = dc->op2;
  1310. LOG_DIS("s%s $r%u\n",
  1311. cc_name(cond), dc->op1);
  1312. gen_tst_cc(dc, cpu_R[dc->op1], cond);
  1313. tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0);
  1314. cris_cc_mask(dc, 0);
  1315. return 2;
  1316. }
  1317. static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
  1318. {
  1319. if (size == 4) {
  1320. t[0] = cpu_R[dc->op2];
  1321. t[1] = cpu_R[dc->op1];
  1322. } else {
  1323. t[0] = tcg_temp_new();
  1324. t[1] = tcg_temp_new();
  1325. }
  1326. }
  1327. static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
  1328. {
  1329. if (size != 4) {
  1330. tcg_temp_free(t[0]);
  1331. tcg_temp_free(t[1]);
  1332. }
  1333. }
  1334. static int dec_and_r(CPUCRISState *env, DisasContext *dc)
  1335. {
  1336. TCGv t[2];
  1337. int size = memsize_zz(dc);
  1338. LOG_DIS("and.%c $r%u, $r%u\n",
  1339. memsize_char(size), dc->op1, dc->op2);
  1340. cris_cc_mask(dc, CC_MASK_NZ);
  1341. cris_alu_alloc_temps(dc, size, t);
  1342. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1343. cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
  1344. cris_alu_free_temps(dc, size, t);
  1345. return 2;
  1346. }
  1347. static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
  1348. {
  1349. TCGv t0;
  1350. LOG_DIS("lz $r%u, $r%u\n",
  1351. dc->op1, dc->op2);
  1352. cris_cc_mask(dc, CC_MASK_NZ);
  1353. t0 = tcg_temp_new();
  1354. dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
  1355. cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
  1356. tcg_temp_free(t0);
  1357. return 2;
  1358. }
  1359. static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
  1360. {
  1361. TCGv t[2];
  1362. int size = memsize_zz(dc);
  1363. LOG_DIS("lsl.%c $r%u, $r%u\n",
  1364. memsize_char(size), dc->op1, dc->op2);
  1365. cris_cc_mask(dc, CC_MASK_NZ);
  1366. cris_alu_alloc_temps(dc, size, t);
  1367. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1368. tcg_gen_andi_tl(t[1], t[1], 63);
  1369. cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
  1370. cris_alu_alloc_temps(dc, size, t);
  1371. return 2;
  1372. }
  1373. static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
  1374. {
  1375. TCGv t[2];
  1376. int size = memsize_zz(dc);
  1377. LOG_DIS("lsr.%c $r%u, $r%u\n",
  1378. memsize_char(size), dc->op1, dc->op2);
  1379. cris_cc_mask(dc, CC_MASK_NZ);
  1380. cris_alu_alloc_temps(dc, size, t);
  1381. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1382. tcg_gen_andi_tl(t[1], t[1], 63);
  1383. cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
  1384. cris_alu_free_temps(dc, size, t);
  1385. return 2;
  1386. }
  1387. static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
  1388. {
  1389. TCGv t[2];
  1390. int size = memsize_zz(dc);
  1391. LOG_DIS("asr.%c $r%u, $r%u\n",
  1392. memsize_char(size), dc->op1, dc->op2);
  1393. cris_cc_mask(dc, CC_MASK_NZ);
  1394. cris_alu_alloc_temps(dc, size, t);
  1395. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
  1396. tcg_gen_andi_tl(t[1], t[1], 63);
  1397. cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
  1398. cris_alu_free_temps(dc, size, t);
  1399. return 2;
  1400. }
  1401. static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
  1402. {
  1403. TCGv t[2];
  1404. int size = memsize_zz(dc);
  1405. LOG_DIS("muls.%c $r%u, $r%u\n",
  1406. memsize_char(size), dc->op1, dc->op2);
  1407. cris_cc_mask(dc, CC_MASK_NZV);
  1408. cris_alu_alloc_temps(dc, size, t);
  1409. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
  1410. cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
  1411. cris_alu_free_temps(dc, size, t);
  1412. return 2;
  1413. }
  1414. static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
  1415. {
  1416. TCGv t[2];
  1417. int size = memsize_zz(dc);
  1418. LOG_DIS("mulu.%c $r%u, $r%u\n",
  1419. memsize_char(size), dc->op1, dc->op2);
  1420. cris_cc_mask(dc, CC_MASK_NZV);
  1421. cris_alu_alloc_temps(dc, size, t);
  1422. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1423. cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
  1424. cris_alu_alloc_temps(dc, size, t);
  1425. return 2;
  1426. }
  1427. static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
  1428. {
  1429. LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
  1430. cris_cc_mask(dc, CC_MASK_NZ);
  1431. cris_alu(dc, CC_OP_DSTEP,
  1432. cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
  1433. return 2;
  1434. }
  1435. static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
  1436. {
  1437. TCGv t[2];
  1438. int size = memsize_zz(dc);
  1439. LOG_DIS("xor.%c $r%u, $r%u\n",
  1440. memsize_char(size), dc->op1, dc->op2);
  1441. BUG_ON(size != 4); /* xor is dword. */
  1442. cris_cc_mask(dc, CC_MASK_NZ);
  1443. cris_alu_alloc_temps(dc, size, t);
  1444. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1445. cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
  1446. cris_alu_free_temps(dc, size, t);
  1447. return 2;
  1448. }
  1449. static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
  1450. {
  1451. TCGv l0;
  1452. int size = memsize_zz(dc);
  1453. LOG_DIS("bound.%c $r%u, $r%u\n",
  1454. memsize_char(size), dc->op1, dc->op2);
  1455. cris_cc_mask(dc, CC_MASK_NZ);
  1456. l0 = tcg_temp_local_new();
  1457. dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
  1458. cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
  1459. tcg_temp_free(l0);
  1460. return 2;
  1461. }
  1462. static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
  1463. {
  1464. TCGv t[2];
  1465. int size = memsize_zz(dc);
  1466. LOG_DIS("cmp.%c $r%u, $r%u\n",
  1467. memsize_char(size), dc->op1, dc->op2);
  1468. cris_cc_mask(dc, CC_MASK_NZVC);
  1469. cris_alu_alloc_temps(dc, size, t);
  1470. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1471. cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
  1472. cris_alu_free_temps(dc, size, t);
  1473. return 2;
  1474. }
  1475. static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
  1476. {
  1477. LOG_DIS("abs $r%u, $r%u\n",
  1478. dc->op1, dc->op2);
  1479. cris_cc_mask(dc, CC_MASK_NZ);
  1480. tcg_gen_abs_tl(cpu_R[dc->op2], cpu_R[dc->op1]);
  1481. cris_alu(dc, CC_OP_MOVE,
  1482. cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
  1483. return 2;
  1484. }
  1485. static int dec_add_r(CPUCRISState *env, DisasContext *dc)
  1486. {
  1487. TCGv t[2];
  1488. int size = memsize_zz(dc);
  1489. LOG_DIS("add.%c $r%u, $r%u\n",
  1490. memsize_char(size), dc->op1, dc->op2);
  1491. cris_cc_mask(dc, CC_MASK_NZVC);
  1492. cris_alu_alloc_temps(dc, size, t);
  1493. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1494. cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
  1495. cris_alu_free_temps(dc, size, t);
  1496. return 2;
  1497. }
  1498. static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
  1499. {
  1500. LOG_DIS("addc $r%u, $r%u\n",
  1501. dc->op1, dc->op2);
  1502. cris_evaluate_flags(dc);
  1503. /* Set for this insn. */
  1504. dc->flagx_known = 1;
  1505. dc->flags_x = X_FLAG;
  1506. cris_cc_mask(dc, CC_MASK_NZVC);
  1507. cris_alu(dc, CC_OP_ADDC,
  1508. cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
  1509. return 2;
  1510. }
  1511. static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
  1512. {
  1513. LOG_DIS("mcp $p%u, $r%u\n",
  1514. dc->op2, dc->op1);
  1515. cris_evaluate_flags(dc);
  1516. cris_cc_mask(dc, CC_MASK_RNZV);
  1517. cris_alu(dc, CC_OP_MCP,
  1518. cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
  1519. return 2;
  1520. }
  1521. #if DISAS_CRIS
  1522. static char * swapmode_name(int mode, char *modename) {
  1523. int i = 0;
  1524. if (mode & 8) {
  1525. modename[i++] = 'n';
  1526. }
  1527. if (mode & 4) {
  1528. modename[i++] = 'w';
  1529. }
  1530. if (mode & 2) {
  1531. modename[i++] = 'b';
  1532. }
  1533. if (mode & 1) {
  1534. modename[i++] = 'r';
  1535. }
  1536. modename[i++] = 0;
  1537. return modename;
  1538. }
  1539. #endif
  1540. static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
  1541. {
  1542. TCGv t0;
  1543. #if DISAS_CRIS
  1544. char modename[4];
  1545. #endif
  1546. LOG_DIS("swap%s $r%u\n",
  1547. swapmode_name(dc->op2, modename), dc->op1);
  1548. cris_cc_mask(dc, CC_MASK_NZ);
  1549. t0 = tcg_temp_new();
  1550. tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
  1551. if (dc->op2 & 8) {
  1552. tcg_gen_not_tl(t0, t0);
  1553. }
  1554. if (dc->op2 & 4) {
  1555. t_gen_swapw(t0, t0);
  1556. }
  1557. if (dc->op2 & 2) {
  1558. t_gen_swapb(t0, t0);
  1559. }
  1560. if (dc->op2 & 1) {
  1561. t_gen_swapr(t0, t0);
  1562. }
  1563. cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
  1564. tcg_temp_free(t0);
  1565. return 2;
  1566. }
  1567. static int dec_or_r(CPUCRISState *env, DisasContext *dc)
  1568. {
  1569. TCGv t[2];
  1570. int size = memsize_zz(dc);
  1571. LOG_DIS("or.%c $r%u, $r%u\n",
  1572. memsize_char(size), dc->op1, dc->op2);
  1573. cris_cc_mask(dc, CC_MASK_NZ);
  1574. cris_alu_alloc_temps(dc, size, t);
  1575. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1576. cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
  1577. cris_alu_free_temps(dc, size, t);
  1578. return 2;
  1579. }
  1580. static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
  1581. {
  1582. TCGv t0;
  1583. LOG_DIS("addi.%c $r%u, $r%u\n",
  1584. memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
  1585. cris_cc_mask(dc, 0);
  1586. t0 = tcg_temp_new();
  1587. tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
  1588. tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
  1589. tcg_temp_free(t0);
  1590. return 2;
  1591. }
  1592. static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
  1593. {
  1594. TCGv t0;
  1595. LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
  1596. memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
  1597. cris_cc_mask(dc, 0);
  1598. t0 = tcg_temp_new();
  1599. tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
  1600. tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
  1601. tcg_temp_free(t0);
  1602. return 2;
  1603. }
  1604. static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
  1605. {
  1606. TCGv t[2];
  1607. int size = memsize_zz(dc);
  1608. LOG_DIS("neg.%c $r%u, $r%u\n",
  1609. memsize_char(size), dc->op1, dc->op2);
  1610. cris_cc_mask(dc, CC_MASK_NZVC);
  1611. cris_alu_alloc_temps(dc, size, t);
  1612. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1613. cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
  1614. cris_alu_free_temps(dc, size, t);
  1615. return 2;
  1616. }
  1617. static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
  1618. {
  1619. LOG_DIS("btst $r%u, $r%u\n",
  1620. dc->op1, dc->op2);
  1621. cris_cc_mask(dc, CC_MASK_NZ);
  1622. cris_evaluate_flags(dc);
  1623. gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
  1624. cpu_R[dc->op1], cpu_PR[PR_CCS]);
  1625. cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
  1626. cpu_R[dc->op2], cpu_R[dc->op2], 4);
  1627. cris_update_cc_op(dc, CC_OP_FLAGS, 4);
  1628. dc->flags_uptodate = 1;
  1629. return 2;
  1630. }
  1631. static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
  1632. {
  1633. TCGv t[2];
  1634. int size = memsize_zz(dc);
  1635. LOG_DIS("sub.%c $r%u, $r%u\n",
  1636. memsize_char(size), dc->op1, dc->op2);
  1637. cris_cc_mask(dc, CC_MASK_NZVC);
  1638. cris_alu_alloc_temps(dc, size, t);
  1639. dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
  1640. cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
  1641. cris_alu_free_temps(dc, size, t);
  1642. return 2;
  1643. }
  1644. /* Zero extension. From size to dword. */
  1645. static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
  1646. {
  1647. TCGv t0;
  1648. int size = memsize_z(dc);
  1649. LOG_DIS("movu.%c $r%u, $r%u\n",
  1650. memsize_char(size),
  1651. dc->op1, dc->op2);
  1652. cris_cc_mask(dc, CC_MASK_NZ);
  1653. t0 = tcg_temp_new();
  1654. dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
  1655. cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
  1656. tcg_temp_free(t0);
  1657. return 2;
  1658. }
  1659. /* Sign extension. From size to dword. */
  1660. static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
  1661. {
  1662. TCGv t0;
  1663. int size = memsize_z(dc);
  1664. LOG_DIS("movs.%c $r%u, $r%u\n",
  1665. memsize_char(size),
  1666. dc->op1, dc->op2);
  1667. cris_cc_mask(dc, CC_MASK_NZ);
  1668. t0 = tcg_temp_new();
  1669. /* Size can only be qi or hi. */
  1670. t_gen_sext(t0, cpu_R[dc->op1], size);
  1671. cris_alu(dc, CC_OP_MOVE,
  1672. cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
  1673. tcg_temp_free(t0);
  1674. return 2;
  1675. }
  1676. /* zero extension. From size to dword. */
  1677. static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
  1678. {
  1679. TCGv t0;
  1680. int size = memsize_z(dc);
  1681. LOG_DIS("addu.%c $r%u, $r%u\n",
  1682. memsize_char(size),
  1683. dc->op1, dc->op2);
  1684. cris_cc_mask(dc, CC_MASK_NZVC);
  1685. t0 = tcg_temp_new();
  1686. /* Size can only be qi or hi. */
  1687. t_gen_zext(t0, cpu_R[dc->op1], size);
  1688. cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
  1689. tcg_temp_free(t0);
  1690. return 2;
  1691. }
  1692. /* Sign extension. From size to dword. */
  1693. static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
  1694. {
  1695. TCGv t0;
  1696. int size = memsize_z(dc);
  1697. LOG_DIS("adds.%c $r%u, $r%u\n",
  1698. memsize_char(size),
  1699. dc->op1, dc->op2);
  1700. cris_cc_mask(dc, CC_MASK_NZVC);
  1701. t0 = tcg_temp_new();
  1702. /* Size can only be qi or hi. */
  1703. t_gen_sext(t0, cpu_R[dc->op1], size);
  1704. cris_alu(dc, CC_OP_ADD,
  1705. cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
  1706. tcg_temp_free(t0);
  1707. return 2;
  1708. }
  1709. /* Zero extension. From size to dword. */
  1710. static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
  1711. {
  1712. TCGv t0;
  1713. int size = memsize_z(dc);
  1714. LOG_DIS("subu.%c $r%u, $r%u\n",
  1715. memsize_char(size),
  1716. dc->op1, dc->op2);
  1717. cris_cc_mask(dc, CC_MASK_NZVC);
  1718. t0 = tcg_temp_new();
  1719. /* Size can only be qi or hi. */
  1720. t_gen_zext(t0, cpu_R[dc->op1], size);
  1721. cris_alu(dc, CC_OP_SUB,
  1722. cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
  1723. tcg_temp_free(t0);
  1724. return 2;
  1725. }
  1726. /* Sign extension. From size to dword. */
  1727. static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
  1728. {
  1729. TCGv t0;
  1730. int size = memsize_z(dc);
  1731. LOG_DIS("subs.%c $r%u, $r%u\n",
  1732. memsize_char(size),
  1733. dc->op1, dc->op2);
  1734. cris_cc_mask(dc, CC_MASK_NZVC);
  1735. t0 = tcg_temp_new();
  1736. /* Size can only be qi or hi. */
  1737. t_gen_sext(t0, cpu_R[dc->op1], size);
  1738. cris_alu(dc, CC_OP_SUB,
  1739. cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
  1740. tcg_temp_free(t0);
  1741. return 2;
  1742. }
  1743. static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
  1744. {
  1745. uint32_t flags;
  1746. int set = (~dc->opcode >> 2) & 1;
  1747. flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
  1748. | EXTRACT_FIELD(dc->ir, 0, 3);
  1749. if (set && flags == 0) {
  1750. LOG_DIS("nop\n");
  1751. return 2;
  1752. } else if (!set && (flags & 0x20)) {
  1753. LOG_DIS("di\n");
  1754. } else {
  1755. LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
  1756. }
  1757. /* User space is not allowed to touch these. Silently ignore. */
  1758. if (dc->tb_flags & U_FLAG) {
  1759. flags &= ~(S_FLAG | I_FLAG | U_FLAG);
  1760. }
  1761. if (flags & X_FLAG) {
  1762. dc->flagx_known = 1;
  1763. if (set) {
  1764. dc->flags_x = X_FLAG;
  1765. } else {
  1766. dc->flags_x = 0;
  1767. }
  1768. }
  1769. /* Break the TB if any of the SPI flag changes. */
  1770. if (flags & (P_FLAG | S_FLAG)) {
  1771. tcg_gen_movi_tl(env_pc, dc->pc + 2);
  1772. dc->is_jmp = DISAS_UPDATE;
  1773. dc->cpustate_changed = 1;
  1774. }
  1775. /* For the I flag, only act on posedge. */
  1776. if ((flags & I_FLAG)) {
  1777. tcg_gen_movi_tl(env_pc, dc->pc + 2);
  1778. dc->is_jmp = DISAS_UPDATE;
  1779. dc->cpustate_changed = 1;
  1780. }
  1781. /* Simply decode the flags. */
  1782. cris_evaluate_flags(dc);
  1783. cris_update_cc_op(dc, CC_OP_FLAGS, 4);
  1784. cris_update_cc_x(dc);
  1785. tcg_gen_movi_tl(cc_op, dc->cc_op);
  1786. if (set) {
  1787. if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
  1788. /* Enter user mode. */
  1789. t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
  1790. tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
  1791. dc->cpustate_changed = 1;
  1792. }
  1793. tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
  1794. } else {
  1795. tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
  1796. }
  1797. dc->flags_uptodate = 1;
  1798. dc->clear_x = 0;
  1799. return 2;
  1800. }
  1801. static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
  1802. {
  1803. LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
  1804. cris_cc_mask(dc, 0);
  1805. gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
  1806. tcg_const_tl(dc->op1));
  1807. return 2;
  1808. }
  1809. static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
  1810. {
  1811. LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
  1812. cris_cc_mask(dc, 0);
  1813. gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
  1814. tcg_const_tl(dc->op2));
  1815. return 2;
  1816. }
  1817. static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
  1818. {
  1819. TCGv t[2];
  1820. LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
  1821. cris_cc_mask(dc, 0);
  1822. t[0] = tcg_temp_new();
  1823. if (dc->op2 == PR_CCS) {
  1824. cris_evaluate_flags(dc);
  1825. tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
  1826. if (dc->tb_flags & U_FLAG) {
  1827. t[1] = tcg_temp_new();
  1828. /* User space is not allowed to touch all flags. */
  1829. tcg_gen_andi_tl(t[0], t[0], 0x39f);
  1830. tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
  1831. tcg_gen_or_tl(t[0], t[1], t[0]);
  1832. tcg_temp_free(t[1]);
  1833. }
  1834. } else {
  1835. tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
  1836. }
  1837. t_gen_mov_preg_TN(dc, dc->op2, t[0]);
  1838. if (dc->op2 == PR_CCS) {
  1839. cris_update_cc_op(dc, CC_OP_FLAGS, 4);
  1840. dc->flags_uptodate = 1;
  1841. }
  1842. tcg_temp_free(t[0]);
  1843. return 2;
  1844. }
  1845. static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
  1846. {
  1847. TCGv t0;
  1848. LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
  1849. cris_cc_mask(dc, 0);
  1850. if (dc->op2 == PR_CCS) {
  1851. cris_evaluate_flags(dc);
  1852. }
  1853. if (dc->op2 == PR_DZ) {
  1854. tcg_gen_movi_tl(cpu_R[dc->op1], 0);
  1855. } else {
  1856. t0 = tcg_temp_new();
  1857. t_gen_mov_TN_preg(t0, dc->op2);
  1858. cris_alu(dc, CC_OP_MOVE,
  1859. cpu_R[dc->op1], cpu_R[dc->op1], t0,
  1860. preg_sizes[dc->op2]);
  1861. tcg_temp_free(t0);
  1862. }
  1863. return 2;
  1864. }
  1865. static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
  1866. {
  1867. int memsize = memsize_zz(dc);
  1868. int insn_len;
  1869. LOG_DIS("move.%c [$r%u%s, $r%u\n",
  1870. memsize_char(memsize),
  1871. dc->op1, dc->postinc ? "+]" : "]",
  1872. dc->op2);
  1873. if (memsize == 4) {
  1874. insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
  1875. cris_cc_mask(dc, CC_MASK_NZ);
  1876. cris_update_cc_op(dc, CC_OP_MOVE, 4);
  1877. cris_update_cc_x(dc);
  1878. cris_update_result(dc, cpu_R[dc->op2]);
  1879. } else {
  1880. TCGv t0;
  1881. t0 = tcg_temp_new();
  1882. insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
  1883. cris_cc_mask(dc, CC_MASK_NZ);
  1884. cris_alu(dc, CC_OP_MOVE,
  1885. cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
  1886. tcg_temp_free(t0);
  1887. }
  1888. do_postinc(dc, memsize);
  1889. return insn_len;
  1890. }
  1891. static inline void cris_alu_m_alloc_temps(TCGv *t)
  1892. {
  1893. t[0] = tcg_temp_new();
  1894. t[1] = tcg_temp_new();
  1895. }
  1896. static inline void cris_alu_m_free_temps(TCGv *t)
  1897. {
  1898. tcg_temp_free(t[0]);
  1899. tcg_temp_free(t[1]);
  1900. }
  1901. static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
  1902. {
  1903. TCGv t[2];
  1904. int memsize = memsize_z(dc);
  1905. int insn_len;
  1906. LOG_DIS("movs.%c [$r%u%s, $r%u\n",
  1907. memsize_char(memsize),
  1908. dc->op1, dc->postinc ? "+]" : "]",
  1909. dc->op2);
  1910. cris_alu_m_alloc_temps(t);
  1911. /* sign extend. */
  1912. insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
  1913. cris_cc_mask(dc, CC_MASK_NZ);
  1914. cris_alu(dc, CC_OP_MOVE,
  1915. cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
  1916. do_postinc(dc, memsize);
  1917. cris_alu_m_free_temps(t);
  1918. return insn_len;
  1919. }
  1920. static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
  1921. {
  1922. TCGv t[2];
  1923. int memsize = memsize_z(dc);
  1924. int insn_len;
  1925. LOG_DIS("addu.%c [$r%u%s, $r%u\n",
  1926. memsize_char(memsize),
  1927. dc->op1, dc->postinc ? "+]" : "]",
  1928. dc->op2);
  1929. cris_alu_m_alloc_temps(t);
  1930. /* sign extend. */
  1931. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  1932. cris_cc_mask(dc, CC_MASK_NZVC);
  1933. cris_alu(dc, CC_OP_ADD,
  1934. cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
  1935. do_postinc(dc, memsize);
  1936. cris_alu_m_free_temps(t);
  1937. return insn_len;
  1938. }
  1939. static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
  1940. {
  1941. TCGv t[2];
  1942. int memsize = memsize_z(dc);
  1943. int insn_len;
  1944. LOG_DIS("adds.%c [$r%u%s, $r%u\n",
  1945. memsize_char(memsize),
  1946. dc->op1, dc->postinc ? "+]" : "]",
  1947. dc->op2);
  1948. cris_alu_m_alloc_temps(t);
  1949. /* sign extend. */
  1950. insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
  1951. cris_cc_mask(dc, CC_MASK_NZVC);
  1952. cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
  1953. do_postinc(dc, memsize);
  1954. cris_alu_m_free_temps(t);
  1955. return insn_len;
  1956. }
  1957. static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
  1958. {
  1959. TCGv t[2];
  1960. int memsize = memsize_z(dc);
  1961. int insn_len;
  1962. LOG_DIS("subu.%c [$r%u%s, $r%u\n",
  1963. memsize_char(memsize),
  1964. dc->op1, dc->postinc ? "+]" : "]",
  1965. dc->op2);
  1966. cris_alu_m_alloc_temps(t);
  1967. /* sign extend. */
  1968. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  1969. cris_cc_mask(dc, CC_MASK_NZVC);
  1970. cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
  1971. do_postinc(dc, memsize);
  1972. cris_alu_m_free_temps(t);
  1973. return insn_len;
  1974. }
  1975. static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
  1976. {
  1977. TCGv t[2];
  1978. int memsize = memsize_z(dc);
  1979. int insn_len;
  1980. LOG_DIS("subs.%c [$r%u%s, $r%u\n",
  1981. memsize_char(memsize),
  1982. dc->op1, dc->postinc ? "+]" : "]",
  1983. dc->op2);
  1984. cris_alu_m_alloc_temps(t);
  1985. /* sign extend. */
  1986. insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
  1987. cris_cc_mask(dc, CC_MASK_NZVC);
  1988. cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
  1989. do_postinc(dc, memsize);
  1990. cris_alu_m_free_temps(t);
  1991. return insn_len;
  1992. }
  1993. static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
  1994. {
  1995. TCGv t[2];
  1996. int memsize = memsize_z(dc);
  1997. int insn_len;
  1998. LOG_DIS("movu.%c [$r%u%s, $r%u\n",
  1999. memsize_char(memsize),
  2000. dc->op1, dc->postinc ? "+]" : "]",
  2001. dc->op2);
  2002. cris_alu_m_alloc_temps(t);
  2003. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  2004. cris_cc_mask(dc, CC_MASK_NZ);
  2005. cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
  2006. do_postinc(dc, memsize);
  2007. cris_alu_m_free_temps(t);
  2008. return insn_len;
  2009. }
  2010. static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
  2011. {
  2012. TCGv t[2];
  2013. int memsize = memsize_z(dc);
  2014. int insn_len;
  2015. LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
  2016. memsize_char(memsize),
  2017. dc->op1, dc->postinc ? "+]" : "]",
  2018. dc->op2);
  2019. cris_alu_m_alloc_temps(t);
  2020. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  2021. cris_cc_mask(dc, CC_MASK_NZVC);
  2022. cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
  2023. do_postinc(dc, memsize);
  2024. cris_alu_m_free_temps(t);
  2025. return insn_len;
  2026. }
  2027. static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
  2028. {
  2029. TCGv t[2];
  2030. int memsize = memsize_z(dc);
  2031. int insn_len;
  2032. LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
  2033. memsize_char(memsize),
  2034. dc->op1, dc->postinc ? "+]" : "]",
  2035. dc->op2);
  2036. cris_alu_m_alloc_temps(t);
  2037. insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
  2038. cris_cc_mask(dc, CC_MASK_NZVC);
  2039. cris_alu(dc, CC_OP_CMP,
  2040. cpu_R[dc->op2], cpu_R[dc->op2], t[1],
  2041. memsize_zz(dc));
  2042. do_postinc(dc, memsize);
  2043. cris_alu_m_free_temps(t);
  2044. return insn_len;
  2045. }
  2046. static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
  2047. {
  2048. TCGv t[2];
  2049. int memsize = memsize_zz(dc);
  2050. int insn_len;
  2051. LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
  2052. memsize_char(memsize),
  2053. dc->op1, dc->postinc ? "+]" : "]",
  2054. dc->op2);
  2055. cris_alu_m_alloc_temps(t);
  2056. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  2057. cris_cc_mask(dc, CC_MASK_NZVC);
  2058. cris_alu(dc, CC_OP_CMP,
  2059. cpu_R[dc->op2], cpu_R[dc->op2], t[1],
  2060. memsize_zz(dc));
  2061. do_postinc(dc, memsize);
  2062. cris_alu_m_free_temps(t);
  2063. return insn_len;
  2064. }
  2065. static int dec_test_m(CPUCRISState *env, DisasContext *dc)
  2066. {
  2067. TCGv t[2];
  2068. int memsize = memsize_zz(dc);
  2069. int insn_len;
  2070. LOG_DIS("test.%c [$r%u%s] op2=%x\n",
  2071. memsize_char(memsize),
  2072. dc->op1, dc->postinc ? "+]" : "]",
  2073. dc->op2);
  2074. cris_evaluate_flags(dc);
  2075. cris_alu_m_alloc_temps(t);
  2076. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  2077. cris_cc_mask(dc, CC_MASK_NZ);
  2078. tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
  2079. cris_alu(dc, CC_OP_CMP,
  2080. cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
  2081. do_postinc(dc, memsize);
  2082. cris_alu_m_free_temps(t);
  2083. return insn_len;
  2084. }
  2085. static int dec_and_m(CPUCRISState *env, DisasContext *dc)
  2086. {
  2087. TCGv t[2];
  2088. int memsize = memsize_zz(dc);
  2089. int insn_len;
  2090. LOG_DIS("and.%c [$r%u%s, $r%u\n",
  2091. memsize_char(memsize),
  2092. dc->op1, dc->postinc ? "+]" : "]",
  2093. dc->op2);
  2094. cris_alu_m_alloc_temps(t);
  2095. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  2096. cris_cc_mask(dc, CC_MASK_NZ);
  2097. cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
  2098. do_postinc(dc, memsize);
  2099. cris_alu_m_free_temps(t);
  2100. return insn_len;
  2101. }
  2102. static int dec_add_m(CPUCRISState *env, DisasContext *dc)
  2103. {
  2104. TCGv t[2];
  2105. int memsize = memsize_zz(dc);
  2106. int insn_len;
  2107. LOG_DIS("add.%c [$r%u%s, $r%u\n",
  2108. memsize_char(memsize),
  2109. dc->op1, dc->postinc ? "+]" : "]",
  2110. dc->op2);
  2111. cris_alu_m_alloc_temps(t);
  2112. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  2113. cris_cc_mask(dc, CC_MASK_NZVC);
  2114. cris_alu(dc, CC_OP_ADD,
  2115. cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
  2116. do_postinc(dc, memsize);
  2117. cris_alu_m_free_temps(t);
  2118. return insn_len;
  2119. }
  2120. static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
  2121. {
  2122. TCGv t[2];
  2123. int memsize = memsize_zz(dc);
  2124. int insn_len;
  2125. LOG_DIS("add.%c [$r%u%s, $r%u\n",
  2126. memsize_char(memsize),
  2127. dc->op1, dc->postinc ? "+]" : "]",
  2128. dc->op2);
  2129. cris_alu_m_alloc_temps(t);
  2130. insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
  2131. cris_cc_mask(dc, 0);
  2132. cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
  2133. do_postinc(dc, memsize);
  2134. cris_alu_m_free_temps(t);
  2135. return insn_len;
  2136. }
  2137. static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
  2138. {
  2139. TCGv l[2];
  2140. int memsize = memsize_zz(dc);
  2141. int insn_len;
  2142. LOG_DIS("bound.%c [$r%u%s, $r%u\n",
  2143. memsize_char(memsize),
  2144. dc->op1, dc->postinc ? "+]" : "]",
  2145. dc->op2);
  2146. l[0] = tcg_temp_local_new();
  2147. l[1] = tcg_temp_local_new();
  2148. insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
  2149. cris_cc_mask(dc, CC_MASK_NZ);
  2150. cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
  2151. do_postinc(dc, memsize);
  2152. tcg_temp_free(l[0]);
  2153. tcg_temp_free(l[1]);
  2154. return insn_len;
  2155. }
  2156. static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
  2157. {
  2158. TCGv t[2];
  2159. int insn_len = 2;
  2160. LOG_DIS("addc [$r%u%s, $r%u\n",
  2161. dc->op1, dc->postinc ? "+]" : "]",
  2162. dc->op2);
  2163. cris_evaluate_flags(dc);
  2164. /* Set for this insn. */
  2165. dc->flagx_known = 1;
  2166. dc->flags_x = X_FLAG;
  2167. cris_alu_m_alloc_temps(t);
  2168. insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
  2169. cris_cc_mask(dc, CC_MASK_NZVC);
  2170. cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
  2171. do_postinc(dc, 4);
  2172. cris_alu_m_free_temps(t);
  2173. return insn_len;
  2174. }
  2175. static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
  2176. {
  2177. TCGv t[2];
  2178. int memsize = memsize_zz(dc);
  2179. int insn_len;
  2180. LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
  2181. memsize_char(memsize),
  2182. dc->op1, dc->postinc ? "+]" : "]",
  2183. dc->op2, dc->ir, dc->zzsize);
  2184. cris_alu_m_alloc_temps(t);
  2185. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  2186. cris_cc_mask(dc, CC_MASK_NZVC);
  2187. cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
  2188. do_postinc(dc, memsize);
  2189. cris_alu_m_free_temps(t);
  2190. return insn_len;
  2191. }
  2192. static int dec_or_m(CPUCRISState *env, DisasContext *dc)
  2193. {
  2194. TCGv t[2];
  2195. int memsize = memsize_zz(dc);
  2196. int insn_len;
  2197. LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
  2198. memsize_char(memsize),
  2199. dc->op1, dc->postinc ? "+]" : "]",
  2200. dc->op2, dc->pc);
  2201. cris_alu_m_alloc_temps(t);
  2202. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  2203. cris_cc_mask(dc, CC_MASK_NZ);
  2204. cris_alu(dc, CC_OP_OR,
  2205. cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
  2206. do_postinc(dc, memsize);
  2207. cris_alu_m_free_temps(t);
  2208. return insn_len;
  2209. }
  2210. static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
  2211. {
  2212. TCGv t[2];
  2213. int memsize = memsize_zz(dc);
  2214. int insn_len = 2;
  2215. LOG_DIS("move.%c [$r%u%s, $p%u\n",
  2216. memsize_char(memsize),
  2217. dc->op1,
  2218. dc->postinc ? "+]" : "]",
  2219. dc->op2);
  2220. cris_alu_m_alloc_temps(t);
  2221. insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
  2222. cris_cc_mask(dc, 0);
  2223. if (dc->op2 == PR_CCS) {
  2224. cris_evaluate_flags(dc);
  2225. if (dc->tb_flags & U_FLAG) {
  2226. /* User space is not allowed to touch all flags. */
  2227. tcg_gen_andi_tl(t[1], t[1], 0x39f);
  2228. tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
  2229. tcg_gen_or_tl(t[1], t[0], t[1]);
  2230. }
  2231. }
  2232. t_gen_mov_preg_TN(dc, dc->op2, t[1]);
  2233. do_postinc(dc, memsize);
  2234. cris_alu_m_free_temps(t);
  2235. return insn_len;
  2236. }
  2237. static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
  2238. {
  2239. TCGv t0;
  2240. int memsize;
  2241. memsize = preg_sizes[dc->op2];
  2242. LOG_DIS("move.%c $p%u, [$r%u%s\n",
  2243. memsize_char(memsize),
  2244. dc->op2, dc->op1, dc->postinc ? "+]" : "]");
  2245. /* prepare store. Address in T0, value in T1. */
  2246. if (dc->op2 == PR_CCS) {
  2247. cris_evaluate_flags(dc);
  2248. }
  2249. t0 = tcg_temp_new();
  2250. t_gen_mov_TN_preg(t0, dc->op2);
  2251. cris_flush_cc_state(dc);
  2252. gen_store(dc, cpu_R[dc->op1], t0, memsize);
  2253. tcg_temp_free(t0);
  2254. cris_cc_mask(dc, 0);
  2255. if (dc->postinc) {
  2256. tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
  2257. }
  2258. return 2;
  2259. }
  2260. static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
  2261. {
  2262. TCGv_i64 tmp[16];
  2263. TCGv tmp32;
  2264. TCGv addr;
  2265. int i;
  2266. int nr = dc->op2 + 1;
  2267. LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
  2268. dc->postinc ? "+]" : "]", dc->op2);
  2269. addr = tcg_temp_new();
  2270. /* There are probably better ways of doing this. */
  2271. cris_flush_cc_state(dc);
  2272. for (i = 0; i < (nr >> 1); i++) {
  2273. tmp[i] = tcg_temp_new_i64();
  2274. tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
  2275. gen_load64(dc, tmp[i], addr);
  2276. }
  2277. if (nr & 1) {
  2278. tmp32 = tcg_temp_new_i32();
  2279. tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
  2280. gen_load(dc, tmp32, addr, 4, 0);
  2281. } else {
  2282. tmp32 = NULL;
  2283. }
  2284. tcg_temp_free(addr);
  2285. for (i = 0; i < (nr >> 1); i++) {
  2286. tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]);
  2287. tcg_gen_shri_i64(tmp[i], tmp[i], 32);
  2288. tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
  2289. tcg_temp_free_i64(tmp[i]);
  2290. }
  2291. if (nr & 1) {
  2292. tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
  2293. tcg_temp_free(tmp32);
  2294. }
  2295. /* writeback the updated pointer value. */
  2296. if (dc->postinc) {
  2297. tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
  2298. }
  2299. /* gen_load might want to evaluate the previous insns flags. */
  2300. cris_cc_mask(dc, 0);
  2301. return 2;
  2302. }
  2303. static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
  2304. {
  2305. TCGv tmp;
  2306. TCGv addr;
  2307. int i;
  2308. LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
  2309. dc->postinc ? "+]" : "]");
  2310. cris_flush_cc_state(dc);
  2311. tmp = tcg_temp_new();
  2312. addr = tcg_temp_new();
  2313. tcg_gen_movi_tl(tmp, 4);
  2314. tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
  2315. for (i = 0; i <= dc->op2; i++) {
  2316. /* Displace addr. */
  2317. /* Perform the store. */
  2318. gen_store(dc, addr, cpu_R[i], 4);
  2319. tcg_gen_add_tl(addr, addr, tmp);
  2320. }
  2321. if (dc->postinc) {
  2322. tcg_gen_mov_tl(cpu_R[dc->op1], addr);
  2323. }
  2324. cris_cc_mask(dc, 0);
  2325. tcg_temp_free(tmp);
  2326. tcg_temp_free(addr);
  2327. return 2;
  2328. }
  2329. static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
  2330. {
  2331. int memsize;
  2332. memsize = memsize_zz(dc);
  2333. LOG_DIS("move.%c $r%u, [$r%u]\n",
  2334. memsize_char(memsize), dc->op2, dc->op1);
  2335. /* prepare store. */
  2336. cris_flush_cc_state(dc);
  2337. gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
  2338. if (dc->postinc) {
  2339. tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
  2340. }
  2341. cris_cc_mask(dc, 0);
  2342. return 2;
  2343. }
  2344. static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
  2345. {
  2346. LOG_DIS("lapcq %x, $r%u\n",
  2347. dc->pc + dc->op1*2, dc->op2);
  2348. cris_cc_mask(dc, 0);
  2349. tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
  2350. return 2;
  2351. }
  2352. static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
  2353. {
  2354. unsigned int rd;
  2355. int32_t imm;
  2356. int32_t pc;
  2357. rd = dc->op2;
  2358. cris_cc_mask(dc, 0);
  2359. imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
  2360. LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
  2361. pc = dc->pc;
  2362. pc += imm;
  2363. tcg_gen_movi_tl(cpu_R[rd], pc);
  2364. return 6;
  2365. }
  2366. /* Jump to special reg. */
  2367. static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
  2368. {
  2369. LOG_DIS("jump $p%u\n", dc->op2);
  2370. if (dc->op2 == PR_CCS) {
  2371. cris_evaluate_flags(dc);
  2372. }
  2373. t_gen_mov_TN_preg(env_btarget, dc->op2);
  2374. /* rete will often have low bit set to indicate delayslot. */
  2375. tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
  2376. cris_cc_mask(dc, 0);
  2377. cris_prepare_jmp(dc, JMP_INDIRECT);
  2378. return 2;
  2379. }
  2380. /* Jump and save. */
  2381. static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
  2382. {
  2383. LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
  2384. cris_cc_mask(dc, 0);
  2385. /* Store the return address in Pd. */
  2386. tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
  2387. if (dc->op2 > 15) {
  2388. abort();
  2389. }
  2390. t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
  2391. cris_prepare_jmp(dc, JMP_INDIRECT);
  2392. return 2;
  2393. }
  2394. static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
  2395. {
  2396. uint32_t imm;
  2397. imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
  2398. LOG_DIS("jas 0x%x\n", imm);
  2399. cris_cc_mask(dc, 0);
  2400. /* Store the return address in Pd. */
  2401. t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
  2402. dc->jmp_pc = imm;
  2403. cris_prepare_jmp(dc, JMP_DIRECT);
  2404. return 6;
  2405. }
  2406. static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
  2407. {
  2408. uint32_t imm;
  2409. imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
  2410. LOG_DIS("jasc 0x%x\n", imm);
  2411. cris_cc_mask(dc, 0);
  2412. /* Store the return address in Pd. */
  2413. t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
  2414. dc->jmp_pc = imm;
  2415. cris_prepare_jmp(dc, JMP_DIRECT);
  2416. return 6;
  2417. }
  2418. static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
  2419. {
  2420. LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
  2421. cris_cc_mask(dc, 0);
  2422. /* Store the return address in Pd. */
  2423. tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
  2424. t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
  2425. cris_prepare_jmp(dc, JMP_INDIRECT);
  2426. return 2;
  2427. }
  2428. static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
  2429. {
  2430. int32_t offset;
  2431. uint32_t cond = dc->op2;
  2432. offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
  2433. LOG_DIS("b%s %d pc=%x dst=%x\n",
  2434. cc_name(cond), offset,
  2435. dc->pc, dc->pc + offset);
  2436. cris_cc_mask(dc, 0);
  2437. /* op2 holds the condition-code. */
  2438. cris_prepare_cc_branch(dc, offset, cond);
  2439. return 4;
  2440. }
  2441. static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
  2442. {
  2443. int32_t simm;
  2444. simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
  2445. LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
  2446. cris_cc_mask(dc, 0);
  2447. /* Store the return address in Pd. */
  2448. t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
  2449. dc->jmp_pc = dc->pc + simm;
  2450. cris_prepare_jmp(dc, JMP_DIRECT);
  2451. return 6;
  2452. }
  2453. static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
  2454. {
  2455. int32_t simm;
  2456. simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
  2457. LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
  2458. cris_cc_mask(dc, 0);
  2459. /* Store the return address in Pd. */
  2460. t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
  2461. dc->jmp_pc = dc->pc + simm;
  2462. cris_prepare_jmp(dc, JMP_DIRECT);
  2463. return 6;
  2464. }
  2465. static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
  2466. {
  2467. cris_cc_mask(dc, 0);
  2468. if (dc->op2 == 15) {
  2469. tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
  2470. -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
  2471. tcg_gen_movi_tl(env_pc, dc->pc + 2);
  2472. t_gen_raise_exception(EXCP_HLT);
  2473. return 2;
  2474. }
  2475. switch (dc->op2 & 7) {
  2476. case 2:
  2477. /* rfe. */
  2478. LOG_DIS("rfe\n");
  2479. cris_evaluate_flags(dc);
  2480. gen_helper_rfe(cpu_env);
  2481. dc->is_jmp = DISAS_UPDATE;
  2482. break;
  2483. case 5:
  2484. /* rfn. */
  2485. LOG_DIS("rfn\n");
  2486. cris_evaluate_flags(dc);
  2487. gen_helper_rfn(cpu_env);
  2488. dc->is_jmp = DISAS_UPDATE;
  2489. break;
  2490. case 6:
  2491. LOG_DIS("break %d\n", dc->op1);
  2492. cris_evaluate_flags(dc);
  2493. /* break. */
  2494. tcg_gen_movi_tl(env_pc, dc->pc + 2);
  2495. /* Breaks start at 16 in the exception vector. */
  2496. t_gen_mov_env_TN(trap_vector,
  2497. tcg_const_tl(dc->op1 + 16));
  2498. t_gen_raise_exception(EXCP_BREAK);
  2499. dc->is_jmp = DISAS_UPDATE;
  2500. break;
  2501. default:
  2502. printf("op2=%x\n", dc->op2);
  2503. BUG();
  2504. break;
  2505. }
  2506. return 2;
  2507. }
  2508. static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
  2509. {
  2510. return 2;
  2511. }
  2512. static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
  2513. {
  2514. return 2;
  2515. }
  2516. static int dec_null(CPUCRISState *env, DisasContext *dc)
  2517. {
  2518. printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
  2519. dc->pc, dc->opcode, dc->op1, dc->op2);
  2520. fflush(NULL);
  2521. BUG();
  2522. return 2;
  2523. }
  2524. static struct decoder_info {
  2525. struct {
  2526. uint32_t bits;
  2527. uint32_t mask;
  2528. };
  2529. int (*dec)(CPUCRISState *env, DisasContext *dc);
  2530. } decinfo[] = {
  2531. /* Order matters here. */
  2532. {DEC_MOVEQ, dec_moveq},
  2533. {DEC_BTSTQ, dec_btstq},
  2534. {DEC_CMPQ, dec_cmpq},
  2535. {DEC_ADDOQ, dec_addoq},
  2536. {DEC_ADDQ, dec_addq},
  2537. {DEC_SUBQ, dec_subq},
  2538. {DEC_ANDQ, dec_andq},
  2539. {DEC_ORQ, dec_orq},
  2540. {DEC_ASRQ, dec_asrq},
  2541. {DEC_LSLQ, dec_lslq},
  2542. {DEC_LSRQ, dec_lsrq},
  2543. {DEC_BCCQ, dec_bccq},
  2544. {DEC_BCC_IM, dec_bcc_im},
  2545. {DEC_JAS_IM, dec_jas_im},
  2546. {DEC_JAS_R, dec_jas_r},
  2547. {DEC_JASC_IM, dec_jasc_im},
  2548. {DEC_JASC_R, dec_jasc_r},
  2549. {DEC_BAS_IM, dec_bas_im},
  2550. {DEC_BASC_IM, dec_basc_im},
  2551. {DEC_JUMP_P, dec_jump_p},
  2552. {DEC_LAPC_IM, dec_lapc_im},
  2553. {DEC_LAPCQ, dec_lapcq},
  2554. {DEC_RFE_ETC, dec_rfe_etc},
  2555. {DEC_ADDC_MR, dec_addc_mr},
  2556. {DEC_MOVE_MP, dec_move_mp},
  2557. {DEC_MOVE_PM, dec_move_pm},
  2558. {DEC_MOVEM_MR, dec_movem_mr},
  2559. {DEC_MOVEM_RM, dec_movem_rm},
  2560. {DEC_MOVE_PR, dec_move_pr},
  2561. {DEC_SCC_R, dec_scc_r},
  2562. {DEC_SETF, dec_setclrf},
  2563. {DEC_CLEARF, dec_setclrf},
  2564. {DEC_MOVE_SR, dec_move_sr},
  2565. {DEC_MOVE_RP, dec_move_rp},
  2566. {DEC_SWAP_R, dec_swap_r},
  2567. {DEC_ABS_R, dec_abs_r},
  2568. {DEC_LZ_R, dec_lz_r},
  2569. {DEC_MOVE_RS, dec_move_rs},
  2570. {DEC_BTST_R, dec_btst_r},
  2571. {DEC_ADDC_R, dec_addc_r},
  2572. {DEC_DSTEP_R, dec_dstep_r},
  2573. {DEC_XOR_R, dec_xor_r},
  2574. {DEC_MCP_R, dec_mcp_r},
  2575. {DEC_CMP_R, dec_cmp_r},
  2576. {DEC_ADDI_R, dec_addi_r},
  2577. {DEC_ADDI_ACR, dec_addi_acr},
  2578. {DEC_ADD_R, dec_add_r},
  2579. {DEC_SUB_R, dec_sub_r},
  2580. {DEC_ADDU_R, dec_addu_r},
  2581. {DEC_ADDS_R, dec_adds_r},
  2582. {DEC_SUBU_R, dec_subu_r},
  2583. {DEC_SUBS_R, dec_subs_r},
  2584. {DEC_LSL_R, dec_lsl_r},
  2585. {DEC_AND_R, dec_and_r},
  2586. {DEC_OR_R, dec_or_r},
  2587. {DEC_BOUND_R, dec_bound_r},
  2588. {DEC_ASR_R, dec_asr_r},
  2589. {DEC_LSR_R, dec_lsr_r},
  2590. {DEC_MOVU_R, dec_movu_r},
  2591. {DEC_MOVS_R, dec_movs_r},
  2592. {DEC_NEG_R, dec_neg_r},
  2593. {DEC_MOVE_R, dec_move_r},
  2594. {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
  2595. {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
  2596. {DEC_MULS_R, dec_muls_r},
  2597. {DEC_MULU_R, dec_mulu_r},
  2598. {DEC_ADDU_M, dec_addu_m},
  2599. {DEC_ADDS_M, dec_adds_m},
  2600. {DEC_SUBU_M, dec_subu_m},
  2601. {DEC_SUBS_M, dec_subs_m},
  2602. {DEC_CMPU_M, dec_cmpu_m},
  2603. {DEC_CMPS_M, dec_cmps_m},
  2604. {DEC_MOVU_M, dec_movu_m},
  2605. {DEC_MOVS_M, dec_movs_m},
  2606. {DEC_CMP_M, dec_cmp_m},
  2607. {DEC_ADDO_M, dec_addo_m},
  2608. {DEC_BOUND_M, dec_bound_m},
  2609. {DEC_ADD_M, dec_add_m},
  2610. {DEC_SUB_M, dec_sub_m},
  2611. {DEC_AND_M, dec_and_m},
  2612. {DEC_OR_M, dec_or_m},
  2613. {DEC_MOVE_RM, dec_move_rm},
  2614. {DEC_TEST_M, dec_test_m},
  2615. {DEC_MOVE_MR, dec_move_mr},
  2616. {{0, 0}, dec_null}
  2617. };
  2618. static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
  2619. {
  2620. int insn_len = 2;
  2621. int i;
  2622. /* Load a halfword onto the instruction register. */
  2623. dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
  2624. /* Now decode it. */
  2625. dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
  2626. dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
  2627. dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
  2628. dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
  2629. dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
  2630. dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
  2631. /* Large switch for all insns. */
  2632. for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
  2633. if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
  2634. insn_len = decinfo[i].dec(env, dc);
  2635. break;
  2636. }
  2637. }
  2638. #if !defined(CONFIG_USER_ONLY)
  2639. /* Single-stepping ? */
  2640. if (dc->tb_flags & S_FLAG) {
  2641. TCGLabel *l1 = gen_new_label();
  2642. tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
  2643. /* We treat SPC as a break with an odd trap vector. */
  2644. cris_evaluate_flags(dc);
  2645. t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
  2646. tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
  2647. tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
  2648. t_gen_raise_exception(EXCP_BREAK);
  2649. gen_set_label(l1);
  2650. }
  2651. #endif
  2652. return insn_len;
  2653. }
  2654. #include "translate_v10.c.inc"
  2655. /*
  2656. * Delay slots on QEMU/CRIS.
  2657. *
  2658. * If an exception hits on a delayslot, the core will let ERP (the Exception
  2659. * Return Pointer) point to the branch (the previous) insn and set the lsb to
  2660. * to give SW a hint that the exception actually hit on the dslot.
  2661. *
  2662. * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
  2663. * the core and any jmp to an odd addresses will mask off that lsb. It is
  2664. * simply there to let sw know there was an exception on a dslot.
  2665. *
  2666. * When the software returns from an exception, the branch will re-execute.
  2667. * On QEMU care needs to be taken when a branch+delayslot sequence is broken
  2668. * and the branch and delayslot don't share pages.
  2669. *
  2670. * The TB contaning the branch insn will set up env->btarget and evaluate
  2671. * env->btaken. When the translation loop exits we will note that the branch
  2672. * sequence is broken and let env->dslot be the size of the branch insn (those
  2673. * vary in length).
  2674. *
  2675. * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
  2676. * set). It will also expect to have env->dslot setup with the size of the
  2677. * delay slot so that env->pc - env->dslot point to the branch insn. This TB
  2678. * will execute the dslot and take the branch, either to btarget or just one
  2679. * insn ahead.
  2680. *
  2681. * When exceptions occur, we check for env->dslot in do_interrupt to detect
  2682. * broken branch sequences and setup $erp accordingly (i.e let it point to the
  2683. * branch and set lsb). Then env->dslot gets cleared so that the exception
  2684. * handler can enter. When returning from exceptions (jump $erp) the lsb gets
  2685. * masked off and we will reexecute the branch insn.
  2686. *
  2687. */
  2688. /* generate intermediate code for basic block 'tb'. */
  2689. void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
  2690. {
  2691. CPUCRISState *env = cs->env_ptr;
  2692. uint32_t pc_start;
  2693. unsigned int insn_len;
  2694. struct DisasContext ctx;
  2695. struct DisasContext *dc = &ctx;
  2696. uint32_t page_start;
  2697. target_ulong npc;
  2698. int num_insns;
  2699. if (env->pregs[PR_VR] == 32) {
  2700. dc->decoder = crisv32_decoder;
  2701. dc->clear_locked_irq = 0;
  2702. } else {
  2703. dc->decoder = crisv10_decoder;
  2704. dc->clear_locked_irq = 1;
  2705. }
  2706. /* Odd PC indicates that branch is rexecuting due to exception in the
  2707. * delayslot, like in real hw.
  2708. */
  2709. pc_start = tb->pc & ~1;
  2710. dc->cpu = env_archcpu(env);
  2711. dc->tb = tb;
  2712. dc->is_jmp = DISAS_NEXT;
  2713. dc->ppc = pc_start;
  2714. dc->pc = pc_start;
  2715. dc->singlestep_enabled = cs->singlestep_enabled;
  2716. dc->flags_uptodate = 1;
  2717. dc->flagx_known = 1;
  2718. dc->flags_x = tb->flags & X_FLAG;
  2719. dc->cc_x_uptodate = 0;
  2720. dc->cc_mask = 0;
  2721. dc->update_cc = 0;
  2722. dc->clear_prefix = 0;
  2723. cris_update_cc_op(dc, CC_OP_FLAGS, 4);
  2724. dc->cc_size_uptodate = -1;
  2725. /* Decode TB flags. */
  2726. dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
  2727. | X_FLAG | PFIX_FLAG);
  2728. dc->delayed_branch = !!(tb->flags & 7);
  2729. if (dc->delayed_branch) {
  2730. dc->jmp = JMP_INDIRECT;
  2731. } else {
  2732. dc->jmp = JMP_NOJMP;
  2733. }
  2734. dc->cpustate_changed = 0;
  2735. page_start = pc_start & TARGET_PAGE_MASK;
  2736. num_insns = 0;
  2737. gen_tb_start(tb);
  2738. do {
  2739. tcg_gen_insn_start(dc->delayed_branch == 1
  2740. ? dc->ppc | 1 : dc->pc);
  2741. num_insns++;
  2742. if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
  2743. cris_evaluate_flags(dc);
  2744. tcg_gen_movi_tl(env_pc, dc->pc);
  2745. t_gen_raise_exception(EXCP_DEBUG);
  2746. dc->is_jmp = DISAS_UPDATE;
  2747. /* The address covered by the breakpoint must be included in
  2748. [tb->pc, tb->pc + tb->size) in order to for it to be
  2749. properly cleared -- thus we increment the PC here so that
  2750. the logic setting tb->size below does the right thing. */
  2751. dc->pc += 2;
  2752. break;
  2753. }
  2754. /* Pretty disas. */
  2755. LOG_DIS("%8.8x:\t", dc->pc);
  2756. if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
  2757. gen_io_start();
  2758. }
  2759. dc->clear_x = 1;
  2760. insn_len = dc->decoder(env, dc);
  2761. dc->ppc = dc->pc;
  2762. dc->pc += insn_len;
  2763. if (dc->clear_x) {
  2764. cris_clear_x_flag(dc);
  2765. }
  2766. /* Check for delayed branches here. If we do it before
  2767. actually generating any host code, the simulator will just
  2768. loop doing nothing for on this program location. */
  2769. if (dc->delayed_branch) {
  2770. dc->delayed_branch--;
  2771. if (dc->delayed_branch == 0) {
  2772. if (tb->flags & 7) {
  2773. t_gen_mov_env_TN(dslot, tcg_const_tl(0));
  2774. }
  2775. if (dc->cpustate_changed || !dc->flagx_known
  2776. || (dc->flags_x != (tb->flags & X_FLAG))) {
  2777. cris_store_direct_jmp(dc);
  2778. }
  2779. if (dc->clear_locked_irq) {
  2780. dc->clear_locked_irq = 0;
  2781. t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
  2782. }
  2783. if (dc->jmp == JMP_DIRECT_CC) {
  2784. TCGLabel *l1 = gen_new_label();
  2785. cris_evaluate_flags(dc);
  2786. /* Conditional jmp. */
  2787. tcg_gen_brcondi_tl(TCG_COND_EQ,
  2788. env_btaken, 0, l1);
  2789. gen_goto_tb(dc, 1, dc->jmp_pc);
  2790. gen_set_label(l1);
  2791. gen_goto_tb(dc, 0, dc->pc);
  2792. dc->is_jmp = DISAS_TB_JUMP;
  2793. dc->jmp = JMP_NOJMP;
  2794. } else if (dc->jmp == JMP_DIRECT) {
  2795. cris_evaluate_flags(dc);
  2796. gen_goto_tb(dc, 0, dc->jmp_pc);
  2797. dc->is_jmp = DISAS_TB_JUMP;
  2798. dc->jmp = JMP_NOJMP;
  2799. } else {
  2800. t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
  2801. dc->is_jmp = DISAS_JUMP;
  2802. }
  2803. break;
  2804. }
  2805. }
  2806. /* If we are rexecuting a branch due to exceptions on
  2807. delay slots don't break. */
  2808. if (!(tb->pc & 1) && cs->singlestep_enabled) {
  2809. break;
  2810. }
  2811. } while (!dc->is_jmp && !dc->cpustate_changed
  2812. && !tcg_op_buf_full()
  2813. && !singlestep
  2814. && (dc->pc - page_start < TARGET_PAGE_SIZE)
  2815. && num_insns < max_insns);
  2816. if (dc->clear_locked_irq) {
  2817. t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
  2818. }
  2819. npc = dc->pc;
  2820. /* Force an update if the per-tb cpu state has changed. */
  2821. if (dc->is_jmp == DISAS_NEXT
  2822. && (dc->cpustate_changed || !dc->flagx_known
  2823. || (dc->flags_x != (tb->flags & X_FLAG)))) {
  2824. dc->is_jmp = DISAS_UPDATE;
  2825. tcg_gen_movi_tl(env_pc, npc);
  2826. }
  2827. /* Broken branch+delayslot sequence. */
  2828. if (dc->delayed_branch == 1) {
  2829. /* Set env->dslot to the size of the branch insn. */
  2830. t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
  2831. cris_store_direct_jmp(dc);
  2832. }
  2833. cris_evaluate_flags(dc);
  2834. if (unlikely(cs->singlestep_enabled)) {
  2835. if (dc->is_jmp == DISAS_NEXT) {
  2836. tcg_gen_movi_tl(env_pc, npc);
  2837. }
  2838. t_gen_raise_exception(EXCP_DEBUG);
  2839. } else {
  2840. switch (dc->is_jmp) {
  2841. case DISAS_NEXT:
  2842. gen_goto_tb(dc, 1, npc);
  2843. break;
  2844. default:
  2845. case DISAS_JUMP:
  2846. case DISAS_UPDATE:
  2847. /* indicate that the hash table must be used
  2848. to find the next TB */
  2849. tcg_gen_exit_tb(NULL, 0);
  2850. break;
  2851. case DISAS_SWI:
  2852. case DISAS_TB_JUMP:
  2853. /* nothing more to generate */
  2854. break;
  2855. }
  2856. }
  2857. gen_tb_end(tb, num_insns);
  2858. tb->size = dc->pc - pc_start;
  2859. tb->icount = num_insns;
  2860. #ifdef DEBUG_DISAS
  2861. #if !DISAS_CRIS
  2862. if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
  2863. && qemu_log_in_addr_range(pc_start)) {
  2864. FILE *logfile = qemu_log_lock();
  2865. qemu_log("--------------\n");
  2866. qemu_log("IN: %s\n", lookup_symbol(pc_start));
  2867. log_target_disas(cs, pc_start, dc->pc - pc_start);
  2868. qemu_log_unlock(logfile);
  2869. }
  2870. #endif
  2871. #endif
  2872. }
  2873. void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags)
  2874. {
  2875. CRISCPU *cpu = CRIS_CPU(cs);
  2876. CPUCRISState *env = &cpu->env;
  2877. const char **regnames;
  2878. const char **pregnames;
  2879. int i;
  2880. if (!env) {
  2881. return;
  2882. }
  2883. if (env->pregs[PR_VR] < 32) {
  2884. pregnames = pregnames_v10;
  2885. regnames = regnames_v10;
  2886. } else {
  2887. pregnames = pregnames_v32;
  2888. regnames = regnames_v32;
  2889. }
  2890. qemu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
  2891. "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
  2892. env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
  2893. env->cc_op,
  2894. env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
  2895. for (i = 0; i < 16; i++) {
  2896. qemu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
  2897. if ((i + 1) % 4 == 0) {
  2898. qemu_fprintf(f, "\n");
  2899. }
  2900. }
  2901. qemu_fprintf(f, "\nspecial regs:\n");
  2902. for (i = 0; i < 16; i++) {
  2903. qemu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
  2904. if ((i + 1) % 4 == 0) {
  2905. qemu_fprintf(f, "\n");
  2906. }
  2907. }
  2908. if (env->pregs[PR_VR] >= 32) {
  2909. uint32_t srs = env->pregs[PR_SRS];
  2910. qemu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
  2911. if (srs < ARRAY_SIZE(env->sregs)) {
  2912. for (i = 0; i < 16; i++) {
  2913. qemu_fprintf(f, "s%2.2d=%8.8x ",
  2914. i, env->sregs[srs][i]);
  2915. if ((i + 1) % 4 == 0) {
  2916. qemu_fprintf(f, "\n");
  2917. }
  2918. }
  2919. }
  2920. }
  2921. qemu_fprintf(f, "\n\n");
  2922. }
  2923. void cris_initialize_tcg(void)
  2924. {
  2925. int i;
  2926. cc_x = tcg_global_mem_new(cpu_env,
  2927. offsetof(CPUCRISState, cc_x), "cc_x");
  2928. cc_src = tcg_global_mem_new(cpu_env,
  2929. offsetof(CPUCRISState, cc_src), "cc_src");
  2930. cc_dest = tcg_global_mem_new(cpu_env,
  2931. offsetof(CPUCRISState, cc_dest),
  2932. "cc_dest");
  2933. cc_result = tcg_global_mem_new(cpu_env,
  2934. offsetof(CPUCRISState, cc_result),
  2935. "cc_result");
  2936. cc_op = tcg_global_mem_new(cpu_env,
  2937. offsetof(CPUCRISState, cc_op), "cc_op");
  2938. cc_size = tcg_global_mem_new(cpu_env,
  2939. offsetof(CPUCRISState, cc_size),
  2940. "cc_size");
  2941. cc_mask = tcg_global_mem_new(cpu_env,
  2942. offsetof(CPUCRISState, cc_mask),
  2943. "cc_mask");
  2944. env_pc = tcg_global_mem_new(cpu_env,
  2945. offsetof(CPUCRISState, pc),
  2946. "pc");
  2947. env_btarget = tcg_global_mem_new(cpu_env,
  2948. offsetof(CPUCRISState, btarget),
  2949. "btarget");
  2950. env_btaken = tcg_global_mem_new(cpu_env,
  2951. offsetof(CPUCRISState, btaken),
  2952. "btaken");
  2953. for (i = 0; i < 16; i++) {
  2954. cpu_R[i] = tcg_global_mem_new(cpu_env,
  2955. offsetof(CPUCRISState, regs[i]),
  2956. regnames_v32[i]);
  2957. }
  2958. for (i = 0; i < 16; i++) {
  2959. cpu_PR[i] = tcg_global_mem_new(cpu_env,
  2960. offsetof(CPUCRISState, pregs[i]),
  2961. pregnames_v32[i]);
  2962. }
  2963. }
  2964. void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb,
  2965. target_ulong *data)
  2966. {
  2967. env->pc = data[0];
  2968. }