digic-timer.c 4.3 KB

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  1. /*
  2. * QEMU model of the Canon DIGIC timer block.
  3. *
  4. * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
  5. *
  6. * This model is based on reverse engineering efforts
  7. * made by CHDK (http://chdk.wikia.com) and
  8. * Magic Lantern (http://www.magiclantern.fm) projects
  9. * contributors.
  10. *
  11. * See "Timer/Clock Module" docs here:
  12. * http://magiclantern.wikia.com/wiki/Register_Map
  13. *
  14. * The QEMU model of the OSTimer in PKUnity SoC by Guan Xuetao
  15. * is used as a template.
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License as published by
  19. * the Free Software Foundation; either version 2 of the License, or
  20. * (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. */
  28. #include "qemu/osdep.h"
  29. #include "hw/sysbus.h"
  30. #include "hw/ptimer.h"
  31. #include "qemu/main-loop.h"
  32. #include "qemu/log.h"
  33. #include "hw/timer/digic-timer.h"
  34. static const VMStateDescription vmstate_digic_timer = {
  35. .name = "digic.timer",
  36. .version_id = 1,
  37. .minimum_version_id = 1,
  38. .fields = (VMStateField[]) {
  39. VMSTATE_PTIMER(ptimer, DigicTimerState),
  40. VMSTATE_UINT32(control, DigicTimerState),
  41. VMSTATE_UINT32(relvalue, DigicTimerState),
  42. VMSTATE_END_OF_LIST()
  43. }
  44. };
  45. static void digic_timer_reset(DeviceState *dev)
  46. {
  47. DigicTimerState *s = DIGIC_TIMER(dev);
  48. ptimer_stop(s->ptimer);
  49. s->control = 0;
  50. s->relvalue = 0;
  51. }
  52. static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size)
  53. {
  54. DigicTimerState *s = opaque;
  55. uint64_t ret = 0;
  56. switch (offset) {
  57. case DIGIC_TIMER_CONTROL:
  58. ret = s->control;
  59. break;
  60. case DIGIC_TIMER_RELVALUE:
  61. ret = s->relvalue;
  62. break;
  63. case DIGIC_TIMER_VALUE:
  64. ret = ptimer_get_count(s->ptimer) & 0xffff;
  65. break;
  66. default:
  67. qemu_log_mask(LOG_UNIMP,
  68. "digic-timer: read access to unknown register 0x"
  69. TARGET_FMT_plx, offset);
  70. }
  71. return ret;
  72. }
  73. static void digic_timer_write(void *opaque, hwaddr offset,
  74. uint64_t value, unsigned size)
  75. {
  76. DigicTimerState *s = opaque;
  77. switch (offset) {
  78. case DIGIC_TIMER_CONTROL:
  79. if (value & DIGIC_TIMER_CONTROL_RST) {
  80. digic_timer_reset((DeviceState *)s);
  81. break;
  82. }
  83. if (value & DIGIC_TIMER_CONTROL_EN) {
  84. ptimer_run(s->ptimer, 0);
  85. }
  86. s->control = (uint32_t)value;
  87. break;
  88. case DIGIC_TIMER_RELVALUE:
  89. s->relvalue = extract32(value, 0, 16);
  90. ptimer_set_limit(s->ptimer, s->relvalue, 1);
  91. break;
  92. case DIGIC_TIMER_VALUE:
  93. break;
  94. default:
  95. qemu_log_mask(LOG_UNIMP,
  96. "digic-timer: read access to unknown register 0x"
  97. TARGET_FMT_plx, offset);
  98. }
  99. }
  100. static const MemoryRegionOps digic_timer_ops = {
  101. .read = digic_timer_read,
  102. .write = digic_timer_write,
  103. .impl = {
  104. .min_access_size = 4,
  105. .max_access_size = 4,
  106. },
  107. .endianness = DEVICE_NATIVE_ENDIAN,
  108. };
  109. static void digic_timer_init(Object *obj)
  110. {
  111. DigicTimerState *s = DIGIC_TIMER(obj);
  112. s->ptimer = ptimer_init(NULL);
  113. /*
  114. * FIXME: there is no documentation on Digic timer
  115. * frequency setup so let it always run at 1 MHz
  116. */
  117. ptimer_set_freq(s->ptimer, 1 * 1000 * 1000);
  118. memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s,
  119. TYPE_DIGIC_TIMER, 0x100);
  120. sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
  121. }
  122. static void digic_timer_class_init(ObjectClass *klass, void *class_data)
  123. {
  124. DeviceClass *dc = DEVICE_CLASS(klass);
  125. dc->reset = digic_timer_reset;
  126. dc->vmsd = &vmstate_digic_timer;
  127. }
  128. static const TypeInfo digic_timer_info = {
  129. .name = TYPE_DIGIC_TIMER,
  130. .parent = TYPE_SYS_BUS_DEVICE,
  131. .instance_size = sizeof(DigicTimerState),
  132. .instance_init = digic_timer_init,
  133. .class_init = digic_timer_class_init,
  134. };
  135. static void digic_timer_register_type(void)
  136. {
  137. type_register_static(&digic_timer_info);
  138. }
  139. type_init(digic_timer_register_type)