 Stefan Hajnoczi
|
65cb7129f4
Merge tag 'exec-20241220' of https://github.com/philmd/qemu into staging
|
há 8 meses atrás |
 Philippe Mathieu-Daudé
|
32cad1ffb8
include: Rename sysemu/ -> system/
|
há 8 meses atrás |
 Jim Shu
|
d3592955af
hw/riscv: Add a new struct RISCVBootInfo
|
há 9 meses atrás |
 Bernhard Beschow
|
982447cc78
hw: Remove unused inclusion of hw/char/serial.h
|
há 11 meses atrás |
 Román Cárdenas
|
a7472560ca
riscv: Fix SiFive E CLINT clock frequency
|
há 1 ano atrás |
 Tommy Wu
|
82193640c4
hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.
|
há 2 anos atrás |
 Daniel Henrique Barboza
|
487d73fc47
hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
|
há 2 anos atrás |
|
Daniel Henrique Barboza
|
62c5bc348e
hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()
|
há 2 anos atrás |
|
Daniel Henrique Barboza
|
60c1f05e36
hw/riscv/boot.c: use MachineState in riscv_load_kernel()
|
há 2 anos atrás |
 Tsukasa OI
|
91a3387dc4
hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
|
há 3 anos atrás |
 Alistair Francis
|
8f972e5b4b
hw/riscv: Use error_fatal for SoC realisation
|
há 3 anos atrás |
 Bin Meng
|
e2b3ef7544
hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
|
há 3 anos atrás |
 Anup Patel
|
b8fb878aa2
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
|
há 4 anos atrás |
|
Anup Patel
|
cc63a18282
hw/intc: Rename sifive_clint sources to riscv_aclint sources
|
há 4 anos atrás |
|
Alistair Francis
|
f436ecc315
hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
|
há 4 anos atrás |
 Peter Maydell
|
7f4c520dac
arch_init.h: Don't include arch_init.h unnecessarily
|
há 4 anos atrás |
|
Bin Meng
|
3de70cec77
hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
|
há 4 anos atrás |
 Thomas Huth
|
ee86213aa3
Do not include exec/address-spaces.h if it's not really necessary
|
há 4 anos atrás |
|
Thomas Huth
|
19f4ed3652
hw: Do not include qemu/log.h if it is not necessary
|
há 4 anos atrás |
 Bin Meng
|
732612856a
hw/riscv: Drop 'struct MemmapEntry'
|
há 4 anos atrás |
|
Alistair Francis
|
38bc4e34f2
hw/riscv: Load the kernel after the firmware
|
há 4 anos atrás |
 Eduardo Habkost
|
fabbcbd953
sifive_e: Register "revb" as class property
|
há 4 anos atrás |
|
Eduardo Habkost
|
5488f2760a
sifive_e: Rename memmap enum constants
|
há 5 anos atrás |
|
Bin Meng
|
b609b7e319
hw/riscv: Move sifive_uart model to hw/char
|
há 5 anos atrás |
|
Bin Meng
|
84fcf3c151
hw/riscv: Move sifive_plic model to hw/intc
|
há 5 anos atrás |
|
Bin Meng
|
406fafd5d0
hw/riscv: Move sifive_clint model to hw/intc
|
há 5 anos atrás |
|
Bin Meng
|
89ece6f76f
hw/riscv: Move sifive_e_prci model to hw/misc
|
há 5 anos atrás |
|
Bin Meng
|
a47ef6e93a
hw/riscv: clint: Avoid using hard-coded timebase frequency
|
há 5 anos atrás |
|
Bin Meng
|
73f6ed97ac
target/riscv: cpu: Set reset vector based on the configured property value
|
há 5 anos atrás |
|
Anup Patel
|
c9270e10a5
hw/riscv: Allow creating multiple instances of PLIC
|
há 5 anos atrás |
