 Zhuang, Siwei (Data61, Kensington NSW)
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6478dd745d
hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()
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5 年之前 |
 Alistair Francis
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fc41ae230e
riscv/sifive_u: Add the start-in-flash property
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5 年之前 |
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Alistair Francis
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687caef13d
riscv/sifive_u: Manually define the machine
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5 年之前 |
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Alistair Francis
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1b3a230870
riscv/sifive_u: Add QSPI memory region
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5 年之前 |
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Alistair Francis
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a6902ef0e3
riscv/sifive_u: Add L2-LIM cache memory
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5 年之前 |
 Bin Meng
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c3a28b5d04
riscv: sifive_u: Add ethernet0 to the aliases node
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6 年之前 |
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Bin Meng
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7ae05377b8
riscv: hw: Drop "clock-frequency" property of cpu nodes
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6 年之前 |
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Bin Meng
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d372e7486f
riscv: sifive_u: Update model and compatible strings in device tree
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6 年之前 |
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Bin Meng
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81e94379f7
riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
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6 年之前 |
|
Bin Meng
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7b6bb66f02
riscv: sifive_u: Fix broken GEM support
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6 年之前 |
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Bin Meng
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5461c4fefe
riscv: sifive_u: Instantiate OTP memory with a serial number
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6 年之前 |
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Bin Meng
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5f7134d3b3
riscv: sifive_u: Change UART node name in device tree
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6 年之前 |
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Bin Meng
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4b55bc2b5f
riscv: sifive_u: Update UART base addresses and IRQs
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6 年之前 |
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Bin Meng
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806c64b7b0
riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
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6 年之前 |
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Bin Meng
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af14c84041
riscv: sifive_u: Add PRCI block to the SoC
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6 年之前 |
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Bin Meng
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e1724d09a6
riscv: sifive_u: Generate hfclk and rtcclk nodes
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6 年之前 |
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Bin Meng
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ef965ce239
riscv: sifive_u: Update PLIC hart topology configuration string
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6 年之前 |
|
Bin Meng
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ecdfe393b6
riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
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6 年之前 |
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Bin Meng
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f3d47d5804
riscv: sifive_u: Set the minimum number of cpus to 2
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6 年之前 |
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Bin Meng
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9baa9f7c9f
riscv: sifive_u: Remove the unnecessary include of prci header
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6 年之前 |
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Bin Meng
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9f79638ec5
riscv: hw: Change create_fdt() to return void
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6 年之前 |
|
Bin Meng
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b179685b6a
riscv: hw: Remove not needed PLIC properties in device tree
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6 年之前 |
|
Bin Meng
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04e7edd108
riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
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6 年之前 |
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Bin Meng
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24e398d06b
riscv: hw: Remove superfluous "linux, phandle" property
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6 年之前 |
 Guenter Roeck
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04ece4f820
riscv: sifive_u: Fix clock-names property for ethernet node
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6 年之前 |
|
Guenter Roeck
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44e6dcd30a
riscv: sivive_u: Add dummy serial clock and aliases entry for uart
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6 年之前 |
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Guenter Roeck
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0f8d446249
riscv: sifive_u: Add support for loading initrd
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6 年之前 |
 Markus Armbruster
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46517dd497
Include sysemu/sysemu.h a lot less
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6 年之前 |
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Markus Armbruster
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650d103d3e
Include hw/hw.h exactly where needed
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6 年之前 |
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Alistair Francis
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fdd1bda4b4
hw/riscv: Load OpenSBI as the default firmware
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6 年之前 |
