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@@ -670,7 +670,8 @@
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#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
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#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
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#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
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-#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID
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+#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
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+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DPC
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#define PCI_EXT_CAP_DSN_SIZEOF 12
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#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
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@@ -946,4 +947,21 @@
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#define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */
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#define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */
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+/* Downstream Port Containment */
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+#define PCI_EXP_DPC_CAP 4 /* DPC Capability */
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+#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */
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+#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */
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+#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */
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+#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
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+
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+#define PCI_EXP_DPC_CTL 6 /* DPC control */
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+#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 /* Enable trigger on ERR_NONFATAL message */
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+#define PCI_EXP_DPC_CTL_INT_EN 0x08 /* DPC Interrupt Enable */
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+
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+#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
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+#define PCI_EXP_DPC_STATUS_TRIGGER 0x01 /* Trigger Status */
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+#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 /* Interrupt Status */
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+
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+#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
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+
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#endif /* LINUX_PCI_REGS_H */
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