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@@ -313,8 +313,8 @@ static void increment_urc(CPUState * env)
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Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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Update the itlb from utlb if update is not 0
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*/
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-int find_itlb_entry(CPUState * env, target_ulong address,
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- int use_asid, int update)
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+static int find_itlb_entry(CPUState * env, target_ulong address,
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+ int use_asid, int update)
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{
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int e, n;
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@@ -344,7 +344,7 @@ int find_itlb_entry(CPUState * env, target_ulong address,
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/* Find utlb entry
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Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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-int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
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+static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
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{
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/* per utlb access */
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increment_urc(env);
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@@ -418,9 +418,9 @@ static int get_mmu_address(CPUState * env, target_ulong * physical,
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return n;
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}
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-int get_physical_address(CPUState * env, target_ulong * physical,
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- int *prot, target_ulong address,
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- int rw, int access_type)
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+static int get_physical_address(CPUState * env, target_ulong * physical,
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+ int *prot, target_ulong address,
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+ int rw, int access_type)
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{
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/* P1, P2 and P4 areas do not use translation */
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if ((address >= 0x80000000 && address < 0xc0000000) ||
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@@ -525,7 +525,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
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return physical;
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}
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-void cpu_load_tlb(CPUState * env)
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+void cpu_load_tlb(CPUSH4State * env)
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{
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int n = cpu_mmucr_urc(env->mmucr);
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tlb_t * entry = &env->utlb[n];
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