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@@ -338,15 +338,68 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
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}
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}
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+/*
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+ * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
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+ * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
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+ * Define the constants to build the cpu topology. Right now, TOPOEXT
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+ * feature is enabled only on EPYC. So, these constants are based on
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+ * EPYC supported configurations. We may need to handle the cases if
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+ * these values change in future.
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+ */
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+/* Maximum core complexes in a node */
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+#define MAX_CCX 2
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+/* Maximum cores in a core complex */
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+#define MAX_CORES_IN_CCX 4
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+/* Maximum cores in a node */
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+#define MAX_CORES_IN_NODE 8
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+/* Maximum nodes in a socket */
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+#define MAX_NODES_PER_SOCKET 4
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+
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+/*
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+ * Figure out the number of nodes required to build this config.
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+ * Max cores in a node is 8
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+ */
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+static int nodes_in_socket(int nr_cores)
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+{
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+ int nodes;
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+
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+ nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
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+
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+ /* Hardware does not support config with 3 nodes, return 4 in that case */
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+ return (nodes == 3) ? 4 : nodes;
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+}
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+
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+/*
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+ * Decide the number of cores in a core complex with the given nr_cores using
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+ * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
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+ * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
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+ * L3 cache is shared across all cores in a core complex. So, this will also
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+ * tell us how many cores are sharing the L3 cache.
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+ */
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+static int cores_in_core_complex(int nr_cores)
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+{
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+ int nodes;
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+
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+ /* Check if we can fit all the cores in one core complex */
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+ if (nr_cores <= MAX_CORES_IN_CCX) {
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+ return nr_cores;
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+ }
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+ /* Get the number of nodes required to build this config */
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+ nodes = nodes_in_socket(nr_cores);
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+
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+ /*
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+ * Divide the cores accros all the core complexes
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+ * Return rounded up value
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+ */
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+ return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
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+}
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+
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/* Encode cache info for CPUID[8000001D] */
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-static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
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- X86CPUTopoInfo *topo_info,
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- uint32_t *eax, uint32_t *ebx,
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- uint32_t *ecx, uint32_t *edx)
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+static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
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+ uint32_t *eax, uint32_t *ebx,
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+ uint32_t *ecx, uint32_t *edx)
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{
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uint32_t l3_cores;
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- unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
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-
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assert(cache->size == cache->line_size * cache->associativity *
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cache->partitions * cache->sets);
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@@ -355,13 +408,10 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
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/* L3 is shared among multiple cores */
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if (cache->level == 3) {
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- l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
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- topo_info->cores_per_die *
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- topo_info->threads_per_core),
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- nodes);
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- *eax |= (l3_cores - 1) << 14;
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+ l3_cores = cores_in_core_complex(cs->nr_cores);
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+ *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
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} else {
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- *eax |= ((topo_info->threads_per_core - 1) << 14);
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+ *eax |= ((cs->nr_threads - 1) << 14);
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}
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assert(cache->line_size > 0);
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@@ -381,17 +431,55 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
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(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
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}
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+/* Data structure to hold the configuration info for a given core index */
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+struct core_topology {
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+ /* core complex id of the current core index */
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+ int ccx_id;
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+ /*
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+ * Adjusted core index for this core in the topology
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+ * This can be 0,1,2,3 with max 4 cores in a core complex
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+ */
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+ int core_id;
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+ /* Node id for this core index */
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+ int node_id;
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+ /* Number of nodes in this config */
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+ int num_nodes;
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+};
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+
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+/*
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+ * Build the configuration closely match the EPYC hardware. Using the EPYC
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+ * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
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+ * right now. This could change in future.
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+ * nr_cores : Total number of cores in the config
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+ * core_id : Core index of the current CPU
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+ * topo : Data structure to hold all the config info for this core index
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+ */
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+static void build_core_topology(int nr_cores, int core_id,
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+ struct core_topology *topo)
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+{
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+ int nodes, cores_in_ccx;
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+
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+ /* First get the number of nodes required */
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+ nodes = nodes_in_socket(nr_cores);
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+
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+ cores_in_ccx = cores_in_core_complex(nr_cores);
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+
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+ topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
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+ topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
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+ topo->core_id = core_id % cores_in_ccx;
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+ topo->num_nodes = nodes;
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+}
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+
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/* Encode cache info for CPUID[8000001E] */
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-static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
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+static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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- X86CPUTopoIDs topo_ids = {0};
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- unsigned long nodes = MAX(topo_info->nodes_per_pkg, 1);
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+ struct core_topology topo = {0};
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+ unsigned long nodes;
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int shift;
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- x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids);
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-
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+ build_core_topology(cs->nr_cores, cpu->core_id, &topo);
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*eax = cpu->apic_id;
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/*
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* CPUID_Fn8000001E_EBX
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@@ -408,8 +496,12 @@ static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
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* 3 Core complex id
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* 1:0 Core id
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*/
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- *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id << 3) |
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- (topo_ids.core_id);
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+ if (cs->nr_threads - 1) {
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+ *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
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+ (topo.ccx_id << 2) | topo.core_id;
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+ } else {
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+ *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
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+ }
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/*
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* CPUID_Fn8000001E_ECX
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* 31:11 Reserved
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@@ -418,8 +510,9 @@ static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
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* 2 Socket id
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* 1:0 Node id
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*/
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- if (nodes <= 4) {
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- *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.node_id;
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+ if (topo.num_nodes <= 4) {
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+ *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
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+ topo.node_id;
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} else {
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/*
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* Node id fix up. Actual hardware supports up to 4 nodes. But with
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@@ -434,10 +527,10 @@ static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
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* number of nodes. find_last_bit returns last set bit(0 based). Left
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* shift(+1) the socket id to represent all the nodes.
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*/
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- nodes -= 1;
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+ nodes = topo.num_nodes - 1;
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shift = find_last_bit(&nodes, 8);
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- *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) |
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- topo_ids.node_id;
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+ *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
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+ topo.node_id;
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}
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*edx = 0;
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}
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@@ -1638,10 +1731,6 @@ typedef struct X86CPUDefinition {
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FeatureWordArray features;
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const char *model_id;
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CPUCaches *cache_info;
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-
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- /* Use AMD EPYC encoding for apic id */
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- bool use_epyc_apic_id_encoding;
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-
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/*
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* Definitions for alternative versions of CPU model.
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* List is terminated by item with version == 0.
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@@ -1683,18 +1772,6 @@ static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition
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return def->versions ?: default_version_list;
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}
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-bool cpu_x86_use_epyc_apic_id_encoding(const char *cpu_type)
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-{
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- X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(cpu_type));
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-
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- assert(xcc);
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- if (xcc->model && xcc->model->cpudef) {
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- return xcc->model->cpudef->use_epyc_apic_id_encoding;
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- } else {
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- return false;
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- }
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-}
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-
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static CPUCaches epyc_cache_info = {
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.l1d_cache = &(CPUCacheInfo) {
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.type = DATA_CACHE,
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@@ -3995,7 +4072,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
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.xlevel = 0x8000001E,
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.model_id = "AMD EPYC Processor",
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.cache_info = &epyc_cache_info,
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- .use_epyc_apic_id_encoding = 1,
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.versions = (X86CPUVersionDefinition[]) {
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{ .version = 1 },
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{
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@@ -4123,7 +4199,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
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.xlevel = 0x8000001E,
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.model_id = "AMD EPYC-Rome Processor",
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.cache_info = &epyc_rome_cache_info,
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- .use_epyc_apic_id_encoding = 1,
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},
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};
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@@ -4872,6 +4947,7 @@ static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
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new->value = g_strdup("type");
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*next = new;
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next = &new->next;
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+ error_free(err);
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}
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x86_cpu_filter_features(xc, false);
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@@ -5489,7 +5565,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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uint32_t signature[3];
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X86CPUTopoInfo topo_info;
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- topo_info.nodes_per_pkg = env->nr_nodes;
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topo_info.dies_per_pkg = env->nr_dies;
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topo_info.cores_per_die = cs->nr_cores;
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topo_info.threads_per_core = cs->nr_threads;
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@@ -5678,7 +5753,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
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break;
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case 1:
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- *eax = env->pkg_offset;
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+ *eax = apicid_pkg_offset(&topo_info);
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*ebx = cs->nr_cores * cs->nr_threads;
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*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
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break;
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@@ -5712,7 +5787,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
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break;
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case 2:
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- *eax = env->pkg_offset;
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+ *eax = apicid_pkg_offset(&topo_info);
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*ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
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*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
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break;
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@@ -5889,11 +5964,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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/*
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* Bits 15:12 is "The number of bits in the initial
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* Core::X86::Apic::ApicId[ApicId] value that indicate
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- * thread ID within a package". This is already stored at
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- * CPUX86State::pkg_offset.
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+ * thread ID within a package".
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* Bits 7:0 is "The number of threads in the package is NC+1"
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*/
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- *ecx = (env->pkg_offset << 12) |
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+ *ecx = (apicid_pkg_offset(&topo_info) << 12) |
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((cs->nr_cores * cs->nr_threads) - 1);
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} else {
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*ecx = 0;
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@@ -5921,20 +5995,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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}
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switch (count) {
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case 0: /* L1 dcache info */
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- encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
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- &topo_info, eax, ebx, ecx, edx);
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+ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
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+ eax, ebx, ecx, edx);
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break;
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case 1: /* L1 icache info */
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- encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
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- &topo_info, eax, ebx, ecx, edx);
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+ encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
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+ eax, ebx, ecx, edx);
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break;
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case 2: /* L2 cache info */
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- encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
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- &topo_info, eax, ebx, ecx, edx);
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+ encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
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+ eax, ebx, ecx, edx);
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break;
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case 3: /* L3 cache info */
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- encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
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- &topo_info, eax, ebx, ecx, edx);
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+ encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
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+ eax, ebx, ecx, edx);
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break;
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default: /* end of info */
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*eax = *ebx = *ecx = *edx = 0;
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@@ -5943,7 +6017,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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case 0x8000001E:
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assert(cpu->core_id <= 255);
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- encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx);
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+ encode_topo_cpuid8000001e(cs, cpu,
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+ eax, ebx, ecx, edx);
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break;
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case 0xC0000000:
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*eax = env->cpuid_xlevel2;
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@@ -6949,7 +7024,6 @@ static void x86_cpu_initfn(Object *obj)
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FeatureWord w;
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env->nr_dies = 1;
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- env->nr_nodes = 1;
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cpu_set_cpustate_pointers(cpu);
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object_property_add(obj, "family", "int",
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Peter Maydell