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@@ -25,8 +25,8 @@
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void cpu_loop(CPUMBState *env)
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void cpu_loop(CPUMBState *env)
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{
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{
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+ int trapnr, ret, si_code, sig;
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CPUState *cs = env_cpu(env);
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CPUState *cs = env_cpu(env);
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- int trapnr, ret, si_code;
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while (1) {
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while (1) {
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cpu_exec_start(cs);
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cpu_exec_start(cs);
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@@ -76,6 +76,7 @@ void cpu_loop(CPUMBState *env)
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env->iflags &= ~(IMM_FLAG | D_FLAG);
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env->iflags &= ~(IMM_FLAG | D_FLAG);
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switch (env->esr & 31) {
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switch (env->esr & 31) {
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case ESR_EC_DIVZERO:
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case ESR_EC_DIVZERO:
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+ sig = TARGET_SIGFPE;
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si_code = TARGET_FPE_INTDIV;
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si_code = TARGET_FPE_INTDIV;
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break;
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break;
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case ESR_EC_FPU:
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case ESR_EC_FPU:
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@@ -84,6 +85,7 @@ void cpu_loop(CPUMBState *env)
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* if there's no recognized bit set. Possibly this
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* if there's no recognized bit set. Possibly this
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* implies that si_code is 0, but follow the structure.
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* implies that si_code is 0, but follow the structure.
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*/
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*/
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+ sig = TARGET_SIGFPE;
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si_code = env->fsr;
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si_code = env->fsr;
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if (si_code & FSR_IO) {
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if (si_code & FSR_IO) {
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si_code = TARGET_FPE_FLTINV;
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si_code = TARGET_FPE_FLTINV;
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@@ -97,13 +99,17 @@ void cpu_loop(CPUMBState *env)
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si_code = TARGET_FPE_FLTRES;
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si_code = TARGET_FPE_FLTRES;
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}
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}
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break;
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break;
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+ case ESR_EC_PRIVINSN:
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+ sig = SIGILL;
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+ si_code = ILL_PRVOPC;
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+ break;
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default:
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default:
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fprintf(stderr, "Unhandled hw-exception: 0x%x\n",
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fprintf(stderr, "Unhandled hw-exception: 0x%x\n",
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env->esr & ESR_EC_MASK);
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env->esr & ESR_EC_MASK);
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cpu_dump_state(cs, stderr, 0);
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cpu_dump_state(cs, stderr, 0);
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exit(EXIT_FAILURE);
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exit(EXIT_FAILURE);
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}
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}
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- force_sig_fault(TARGET_SIGFPE, si_code, env->pc);
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+ force_sig_fault(sig, si_code, env->pc);
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break;
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break;
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case EXCP_DEBUG:
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case EXCP_DEBUG:
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