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@@ -192,7 +192,6 @@ pub fn read(
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0
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0
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}
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}
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Ok(DR) => {
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Ok(DR) => {
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- // s->flags &= ~PL011_FLAG_RXFF;
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self.flags.set_receive_fifo_full(false);
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self.flags.set_receive_fifo_full(false);
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let c = self.read_fifo[self.read_pos];
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let c = self.read_fifo[self.read_pos];
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if self.read_count > 0 {
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if self.read_count > 0 {
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@@ -200,11 +199,9 @@ pub fn read(
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self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1);
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self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1);
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}
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}
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if self.read_count == 0 {
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if self.read_count == 0 {
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- // self.flags |= PL011_FLAG_RXFE;
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self.flags.set_receive_fifo_empty(true);
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self.flags.set_receive_fifo_empty(true);
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}
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}
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if self.read_count + 1 == self.read_trigger {
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if self.read_count + 1 == self.read_trigger {
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- //self.int_level &= ~ INT_RX;
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self.int_level &= !registers::INT_RX;
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self.int_level &= !registers::INT_RX;
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}
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}
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// Update error bits.
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// Update error bits.
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@@ -374,13 +371,6 @@ fn loopback_mdmctrl(&mut self) {
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* dealt with here.
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* dealt with here.
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*/
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*/
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- //fr = s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD |
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- // PL011_FLAG_DSR | PL011_FLAG_CTS);
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- //fr |= (cr & CR_OUT2) ? PL011_FLAG_RI : 0;
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- //fr |= (cr & CR_OUT1) ? PL011_FLAG_DCD : 0;
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- //fr |= (cr & CR_RTS) ? PL011_FLAG_CTS : 0;
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- //fr |= (cr & CR_DTR) ? PL011_FLAG_DSR : 0;
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- //
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self.flags.set_ring_indicator(self.control.out_2());
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self.flags.set_ring_indicator(self.control.out_2());
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self.flags.set_data_carrier_detect(self.control.out_1());
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self.flags.set_data_carrier_detect(self.control.out_1());
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self.flags.set_clear_to_send(self.control.request_to_send());
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self.flags.set_clear_to_send(self.control.request_to_send());
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@@ -391,10 +381,6 @@ fn loopback_mdmctrl(&mut self) {
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let mut il = self.int_level;
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let mut il = self.int_level;
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il &= !Interrupt::MS;
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il &= !Interrupt::MS;
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- //il |= (fr & PL011_FLAG_DSR) ? INT_DSR : 0;
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- //il |= (fr & PL011_FLAG_DCD) ? INT_DCD : 0;
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- //il |= (fr & PL011_FLAG_CTS) ? INT_CTS : 0;
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- //il |= (fr & PL011_FLAG_RI) ? INT_RI : 0;
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if self.flags.data_set_ready() {
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if self.flags.data_set_ready() {
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il |= Interrupt::DSR as u32;
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il |= Interrupt::DSR as u32;
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@@ -500,10 +486,8 @@ pub fn put_fifo(&mut self, value: c_uint) {
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let slot = (self.read_pos + self.read_count) & (depth - 1);
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let slot = (self.read_pos + self.read_count) & (depth - 1);
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self.read_fifo[slot] = value;
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self.read_fifo[slot] = value;
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self.read_count += 1;
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self.read_count += 1;
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- // s->flags &= ~PL011_FLAG_RXFE;
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self.flags.set_receive_fifo_empty(false);
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self.flags.set_receive_fifo_empty(false);
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if self.read_count == depth {
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if self.read_count == depth {
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- //s->flags |= PL011_FLAG_RXFF;
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self.flags.set_receive_fifo_full(true);
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self.flags.set_receive_fifo_full(true);
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}
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}
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