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@@ -2898,7 +2898,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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TCGType type = vecl + TCG_TYPE_V64;
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int insn, sub;
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- TCGArg a0, a1, a2;
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+ TCGArg a0, a1, a2, a3;
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a0 = args[0];
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a1 = args[1];
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@@ -3122,6 +3122,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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sub = 0xdd; /* orB!C */
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goto gen_simd_imm8;
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+ case INDEX_op_bitsel_vec:
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+ insn = OPC_VPTERNLOGQ;
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+ a3 = args[3];
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+ if (a0 == a1) {
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+ a1 = a2;
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+ a2 = a3;
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+ sub = 0xca; /* A?B:C */
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+ } else if (a0 == a2) {
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+ a2 = a3;
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+ sub = 0xe2; /* B?A:C */
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+ } else {
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+ tcg_out_mov(s, type, a0, a3);
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+ sub = 0xb8; /* B?C:A */
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+ }
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+ goto gen_simd_imm8;
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+
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gen_simd_imm8:
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tcg_debug_assert(insn != OPC_UD2);
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if (type == TCG_TYPE_V256) {
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@@ -3390,6 +3406,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_x86_vpshrdv_vec:
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return C_O1_I3(x, 0, x, x);
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+ case INDEX_op_bitsel_vec:
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case INDEX_op_x86_vpblendvb_vec:
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return C_O1_I3(x, x, x, x);
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@@ -3412,6 +3429,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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case INDEX_op_nor_vec:
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case INDEX_op_eqv_vec:
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case INDEX_op_not_vec:
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+ case INDEX_op_bitsel_vec:
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return 1;
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case INDEX_op_cmp_vec:
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case INDEX_op_cmpsel_vec:
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