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@@ -117,6 +117,10 @@ static void sys_cache_info(int *isize, int *dsize)
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* Architecture (+ OS) specific cache detection mechanisms.
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*/
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+#if defined(__powerpc__)
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+static bool have_coherent_icache;
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+#endif
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+
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#if defined(__aarch64__) && !defined(CONFIG_DARWIN)
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/* Apple does not expose CTR_EL0, so we must use system interfaces. */
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static uint64_t save_ctr_el0;
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@@ -156,6 +160,7 @@ static void arch_cache_info(int *isize, int *dsize)
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if (*dsize == 0) {
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*dsize = qemu_getauxval(AT_DCACHEBSIZE);
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}
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+ have_coherent_icache = qemu_getauxval(AT_HWCAP) & PPC_FEATURE_ICACHE_SNOOP;
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}
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#else
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@@ -298,8 +303,24 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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uintptr_t p, b, e;
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- size_t dsize = qemu_dcache_linesize;
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- size_t isize = qemu_icache_linesize;
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+ size_t dsize, isize;
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+
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+ /*
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+ * Some processors have coherent caches and support a simplified
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+ * flushing procedure. See
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+ * POWER9 UM, 4.6.2.2 Instruction Cache Block Invalidate (icbi)
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+ * https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
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+ */
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+ if (have_coherent_icache) {
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+ asm volatile ("sync\n\t"
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+ "icbi 0,%0\n\t"
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+ "isync"
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+ : : "r"(rx) : "memory");
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+ return;
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+ }
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+
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+ dsize = qemu_dcache_linesize;
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+ isize = qemu_icache_linesize;
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b = rw & ~(dsize - 1);
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e = (rw + len + dsize - 1) & ~(dsize - 1);
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