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+/*
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+ * Cadence SDHCI emulation
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+ *
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+ * Copyright (c) 2020 Wind River Systems, Inc.
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+ *
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+ * Author:
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+ * Bin Meng <bin.meng@windriver.com>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 or
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+ * (at your option) version 3 of the License.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "qemu/bitops.h"
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+#include "qemu/error-report.h"
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+#include "qemu/log.h"
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+#include "qapi/error.h"
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+#include "migration/vmstate.h"
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+#include "hw/irq.h"
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+#include "hw/sd/cadence_sdhci.h"
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+#include "sdhci-internal.h"
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+
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+/* HRS - Host Register Set (specific to Cadence) */
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+
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+#define CADENCE_SDHCI_HRS00 0x00 /* general information */
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+#define CADENCE_SDHCI_HRS00_SWR BIT(0)
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+#define CADENCE_SDHCI_HRS00_POR_VAL 0x00010000
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+
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+#define CADENCE_SDHCI_HRS04 0x10 /* PHY access port */
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+#define CADENCE_SDHCI_HRS04_WR BIT(24)
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+#define CADENCE_SDHCI_HRS04_RD BIT(25)
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+#define CADENCE_SDHCI_HRS04_ACK BIT(26)
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+
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+#define CADENCE_SDHCI_HRS06 0x18 /* eMMC control */
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+#define CADENCE_SDHCI_HRS06_TUNE_UP BIT(15)
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+
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+/* SRS - Slot Register Set (SDHCI-compatible) */
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+
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+#define CADENCE_SDHCI_SRS_BASE 0x200
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+
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+#define TO_REG(addr) ((addr) / sizeof(uint32_t))
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+
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+static void cadence_sdhci_instance_init(Object *obj)
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+{
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+ CadenceSDHCIState *s = CADENCE_SDHCI(obj);
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+
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+ object_initialize_child(OBJECT(s), "generic-sdhci",
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+ &s->sdhci, TYPE_SYSBUS_SDHCI);
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+}
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+
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+static void cadence_sdhci_reset(DeviceState *dev)
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+{
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+ CadenceSDHCIState *s = CADENCE_SDHCI(dev);
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+
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+ memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE);
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+ s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL;
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+
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+ device_cold_reset(DEVICE(&s->sdhci));
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+}
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+
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+static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
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+{
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+ CadenceSDHCIState *s = opaque;
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+ uint32_t val;
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+
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+ val = s->regs[TO_REG(addr)];
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+
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+ return (uint64_t)val;
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+}
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+
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+static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
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+ unsigned int size)
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+{
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+ CadenceSDHCIState *s = opaque;
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+ uint32_t val32 = (uint32_t)val;
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+
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+ switch (addr) {
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+ case CADENCE_SDHCI_HRS00:
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+ /*
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+ * The only writable bit is SWR (software reset) and it automatically
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+ * clears to zero, so essentially this register remains unchanged.
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+ */
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+ if (val32 & CADENCE_SDHCI_HRS00_SWR) {
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+ cadence_sdhci_reset(DEVICE(s));
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+ }
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+
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+ break;
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+ case CADENCE_SDHCI_HRS04:
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+ /*
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+ * Only emulate the ACK bit behavior when read or write transaction
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+ * are requested.
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+ */
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+ if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) {
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+ val32 |= CADENCE_SDHCI_HRS04_ACK;
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+ } else {
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+ val32 &= ~CADENCE_SDHCI_HRS04_ACK;
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+ }
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+
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+ s->regs[TO_REG(addr)] = val32;
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+ break;
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+ case CADENCE_SDHCI_HRS06:
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+ if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) {
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+ val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP;
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+ }
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+
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+ s->regs[TO_REG(addr)] = val32;
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+ break;
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+ default:
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+ s->regs[TO_REG(addr)] = val32;
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+ break;
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+ }
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+}
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+
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+static const MemoryRegionOps cadence_sdhci_ops = {
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+ .read = cadence_sdhci_read,
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+ .write = cadence_sdhci_write,
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+ .endianness = DEVICE_NATIVE_ENDIAN,
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+ .impl = {
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+ .min_access_size = 4,
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+ .max_access_size = 4,
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+ },
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+ .valid = {
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+ .min_access_size = 4,
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+ .max_access_size = 4,
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+ }
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+};
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+
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+static void cadence_sdhci_realize(DeviceState *dev, Error **errp)
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+{
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+ CadenceSDHCIState *s = CADENCE_SDHCI(dev);
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+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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+ SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci);
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+
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+ memory_region_init(&s->container, OBJECT(s),
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+ "cadence.sdhci-container", 0x1000);
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+ sysbus_init_mmio(sbd, &s->container);
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+
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+ memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops,
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+ s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE);
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+ memory_region_add_subregion(&s->container, 0, &s->iomem);
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+
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+ sysbus_realize(sbd_sdhci, errp);
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+ memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE,
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+ sysbus_mmio_get_region(sbd_sdhci, 0));
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+
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+ /* propagate irq and "sd-bus" from generic-sdhci */
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+ sysbus_pass_irq(sbd, sbd_sdhci);
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+ s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus");
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+}
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+
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+static const VMStateDescription vmstate_cadence_sdhci = {
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+ .name = TYPE_CADENCE_SDHCI,
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+ .version_id = 1,
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+ .fields = (VMStateField[]) {
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+ VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS),
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+ VMSTATE_END_OF_LIST(),
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+ },
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+};
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+
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+static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
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+{
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+ DeviceClass *dc = DEVICE_CLASS(classp);
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+
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+ dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)";
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+ dc->realize = cadence_sdhci_realize;
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+ dc->reset = cadence_sdhci_reset;
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+ dc->vmsd = &vmstate_cadence_sdhci;
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+}
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+
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+static TypeInfo cadence_sdhci_info = {
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+ .name = TYPE_CADENCE_SDHCI,
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+ .parent = TYPE_SYS_BUS_DEVICE,
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+ .instance_size = sizeof(CadenceSDHCIState),
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+ .instance_init = cadence_sdhci_instance_init,
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+ .class_init = cadence_sdhci_class_init,
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+};
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+
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+static void cadence_sdhci_register_types(void)
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+{
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+ type_register_static(&cadence_sdhci_info);
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+}
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+
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+type_init(cadence_sdhci_register_types)
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