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@@ -2141,7 +2141,7 @@ DISAS_INSN(fpu)
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break;
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case 5: /* OS_DOUBLE */
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tcg_gen_mov_i32(tmp32, AREG(insn, 0));
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- switch (insn >> 3) {
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+ switch ((insn >> 3) & 7) {
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case 2:
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case 3:
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case 4:
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@@ -2156,7 +2156,7 @@ DISAS_INSN(fpu)
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goto undef;
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}
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gen_store64(s, tmp32, src);
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- switch (insn >> 3) {
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+ switch ((insn >> 3) & 7) {
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case 3:
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tcg_gen_addi_i32(tmp32, tmp32, 8);
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tcg_gen_mov_i32(AREG(insn, 0), tmp32);
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@@ -2254,7 +2254,7 @@ DISAS_INSN(fpu)
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if (opsize == OS_DOUBLE) {
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tmp32 = tcg_temp_new_i32();
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tcg_gen_mov_i32(tmp32, AREG(insn, 0));
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- switch (insn >> 3) {
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+ switch ((insn >> 3) & 7) {
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case 2:
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case 3:
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case 4:
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@@ -2275,7 +2275,7 @@ DISAS_INSN(fpu)
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goto undef;
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}
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src = gen_load64(s, tmp32);
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- switch (insn >> 3) {
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+ switch ((insn >> 3) & 7) {
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case 3:
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tcg_gen_addi_i32(tmp32, tmp32, 8);
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tcg_gen_mov_i32(AREG(insn, 0), tmp32);
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