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@@ -9,6 +9,18 @@
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* (at your option) any later version.
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*/
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+/*
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+ * This is a model of the Serial Communication Controller (SCC)
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+ * block found in most MPS FPGA images.
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+ *
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+ * QEMU interface:
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+ * + sysbus MMIO region 0: the register bank
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+ * + QOM property "scc-cfg4": value of the read-only CFG4 register
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+ * + QOM property "scc-aid": value of the read-only SCC_AID register
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+ * + QOM property "scc-id": value of the read-only SCC_ID register
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+ * + QOM property array "oscclk": reset values of the OSCCLK registers
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+ * (which are accessed via the SYS_CFG channel provided by this device)
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+ */
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#ifndef MPS2_SCC_H
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#define MPS2_SCC_H
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