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@@ -100,7 +100,7 @@ static void rtas_ibm_query_pe_dma_window(PowerPCCPU *cpu,
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uint64_t buid;
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uint64_t buid;
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uint32_t avail, addr, pgmask = 0;
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uint32_t avail, addr, pgmask = 0;
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- if ((nargs != 3) || (nret != 5)) {
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+ if ((nargs != 3) || ((nret != 5) && (nret != 6))) {
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goto param_error_exit;
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goto param_error_exit;
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}
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}
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@@ -118,9 +118,20 @@ static void rtas_ibm_query_pe_dma_window(PowerPCCPU *cpu,
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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rtas_st(rets, 1, avail);
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rtas_st(rets, 1, avail);
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- rtas_st(rets, 2, 0x80000000); /* The largest window we can possibly have */
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- rtas_st(rets, 3, pgmask);
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- rtas_st(rets, 4, 0); /* DMA migration mask, not supported */
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+ if (nret == 6) {
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+ /*
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+ * Set the Max TCE number as 1<<(58-21) = 0x20.0000.0000
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+ * 1<<59 is the huge window start and 21 is 2M page shift.
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+ */
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+ rtas_st(rets, 2, 0x00000020);
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+ rtas_st(rets, 3, 0x00000000);
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+ rtas_st(rets, 4, pgmask);
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+ rtas_st(rets, 5, 0); /* DMA migration mask, not supported */
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+ } else {
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+ rtas_st(rets, 2, 0x80000000);
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+ rtas_st(rets, 3, pgmask);
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+ rtas_st(rets, 4, 0); /* DMA migration mask, not supported */
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+ }
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trace_spapr_iommu_ddw_query(buid, addr, avail, 0x80000000, pgmask);
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trace_spapr_iommu_ddw_query(buid, addr, avail, 0x80000000, pgmask);
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return;
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return;
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