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@@ -36,16 +36,7 @@
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#include "exec/address-spaces.h"
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#include "exec/address-spaces.h"
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#include "qapi/error.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/log.h"
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-
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-/* debug sabre */
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-//#define DEBUG_SABRE
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-
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-#ifdef DEBUG_SABRE
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-#define SABRE_DPRINTF(fmt, ...) \
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-do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0)
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-#else
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-#define SABRE_DPRINTF(fmt, ...)
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-#endif
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+#include "trace.h"
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/*
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/*
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* Chipset docs:
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* Chipset docs:
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@@ -69,8 +60,7 @@ do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0)
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static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
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static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
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{
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{
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- SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num);
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-
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+ trace_sabre_set_request(irq_num);
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s->irq_request = irq_num;
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s->irq_request = irq_num;
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qemu_set_irq(s->ivec_irqs[irq_num], 1);
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qemu_set_irq(s->ivec_irqs[irq_num], 1);
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}
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}
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@@ -108,7 +98,7 @@ static inline void sabre_check_irqs(SabreState *s)
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static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
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static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
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{
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{
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- SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
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+ trace_sabre_clear_request(irq_num);
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qemu_set_irq(s->ivec_irqs[irq_num], 0);
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qemu_set_irq(s->ivec_irqs[irq_num], 0);
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s->irq_request = NO_IRQ_REQUEST;
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s->irq_request = NO_IRQ_REQUEST;
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}
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}
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@@ -125,8 +115,7 @@ static void sabre_config_write(void *opaque, hwaddr addr,
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{
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{
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SabreState *s = opaque;
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SabreState *s = opaque;
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- SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
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- addr, val);
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+ trace_sabre_config_write(addr, val);
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switch (addr & 0xffff) {
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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case 0x30 ... 0x4f: /* DMA error registers */
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@@ -250,7 +239,7 @@ static uint64_t sabre_config_read(void *opaque,
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val = 0;
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val = 0;
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break;
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break;
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}
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}
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- SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
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+ trace_sabre_config_read(addr, val);
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return val;
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return val;
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}
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}
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@@ -267,8 +256,7 @@ static void sabre_pci_config_write(void *opaque, hwaddr addr,
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SabreState *s = opaque;
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SabreState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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- SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
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- addr, val);
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+ trace_sabre_pci_config_write(addr, val);
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pci_data_write(phb->bus, addr, val, size);
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pci_data_write(phb->bus, addr, val, size);
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}
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}
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@@ -280,7 +268,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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ret = pci_data_read(phb->bus, addr, size);
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ret = pci_data_read(phb->bus, addr, size);
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- SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
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+ trace_sabre_pci_config_read(addr, ret);
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return ret;
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return ret;
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}
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}
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@@ -318,7 +306,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
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{
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{
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SabreState *s = opaque;
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SabreState *s = opaque;
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- SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
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+ trace_sabre_pci_set_irq(irq_num, level);
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+
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/* PCI IRQ map onto the first 32 INO. */
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/* PCI IRQ map onto the first 32 INO. */
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if (irq_num < 32) {
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if (irq_num < 32) {
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if (level) {
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if (level) {
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@@ -332,8 +321,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
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} else {
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} else {
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/* OBIO IRQ map onto the next 32 INO. */
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/* OBIO IRQ map onto the next 32 INO. */
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if (level) {
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if (level) {
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- SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num,
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- level);
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+ trace_sabre_pci_set_obio_irq(irq_num, level);
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s->pci_irq_in |= 1ULL << irq_num;
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s->pci_irq_in |= 1ULL << irq_num;
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if ((s->irq_request == NO_IRQ_REQUEST)
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if ((s->irq_request == NO_IRQ_REQUEST)
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&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
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&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
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