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@@ -23,22 +23,6 @@
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#include "kvm.h"
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#include "qemu-barrier.h"
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-#if !defined(CONFIG_SOFTMMU)
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-#undef EAX
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-#undef ECX
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-#undef EDX
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-#undef EBX
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-#undef ESP
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-#undef EBP
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-#undef ESI
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-#undef EDI
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-#undef EIP
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-#include <signal.h>
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-#ifdef __linux__
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-#include <sys/ucontext.h>
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-#endif
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-#endif
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-
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#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
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// Work around ugly bugs in glibc that mangle global register contents
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#undef env
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@@ -48,7 +32,6 @@
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int tb_invalidated_flag;
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//#define CONFIG_DEBUG_EXEC
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-//#define DEBUG_SIGNAL
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int qemu_cpu_has_work(CPUState *env)
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{
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@@ -64,37 +47,17 @@ void cpu_loop_exit(void)
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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+#if defined(CONFIG_SOFTMMU)
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void cpu_resume_from_signal(CPUState *env1, void *puc)
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{
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-#if !defined(CONFIG_SOFTMMU)
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-#ifdef __linux__
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- struct ucontext *uc = puc;
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-#elif defined(__OpenBSD__)
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- struct sigcontext *uc = puc;
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-#endif
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-#endif
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-
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env = env1;
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/* XXX: restore cpu registers saved in host registers */
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-#if !defined(CONFIG_SOFTMMU)
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- if (puc) {
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- /* XXX: use siglongjmp ? */
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-#ifdef __linux__
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-#ifdef __ia64
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- sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
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-#else
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- sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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-#endif
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-#elif defined(__OpenBSD__)
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- sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
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-#endif
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- }
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-#endif
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env->exception_index = -1;
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longjmp(env->jmp_env, 1);
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}
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+#endif
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/* Execute the code without caching the generated code. An interpreter
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could be used if available. */
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@@ -360,10 +323,7 @@ int cpu_exec(CPUState *env1)
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if (unlikely(interrupt_request)) {
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if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
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/* Mask out external interrupts for this step. */
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- interrupt_request &= ~(CPU_INTERRUPT_HARD |
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- CPU_INTERRUPT_FIQ |
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- CPU_INTERRUPT_SMI |
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- CPU_INTERRUPT_NMI);
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+ interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
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}
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if (interrupt_request & CPU_INTERRUPT_DEBUG) {
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env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
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@@ -492,9 +452,6 @@ int cpu_exec(CPUState *env1)
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next_tb = 0;
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}
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}
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- } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
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- //do_interrupt(0, 0, 0, 0, 0);
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- env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
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}
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#elif defined(TARGET_ARM)
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if (interrupt_request & CPU_INTERRUPT_FIQ
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@@ -509,7 +466,7 @@ int cpu_exec(CPUState *env1)
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jump normally, then does the exception return when the
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CPU tries to execute code at the magic address.
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This will cause the magic PC value to be pushed to
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- the stack if an interrupt occured at the wrong time.
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+ the stack if an interrupt occurred at the wrong time.
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We avoid this by disabling interrupts when
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pc contains a magic address. */
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if (interrupt_request & CPU_INTERRUPT_HARD
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@@ -531,9 +488,36 @@ int cpu_exec(CPUState *env1)
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next_tb = 0;
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}
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#elif defined(TARGET_ALPHA)
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- if (interrupt_request & CPU_INTERRUPT_HARD) {
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- do_interrupt(env);
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- next_tb = 0;
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+ {
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+ int idx = -1;
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+ /* ??? This hard-codes the OSF/1 interrupt levels. */
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+ switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
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+ case 0 ... 3:
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+ if (interrupt_request & CPU_INTERRUPT_HARD) {
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+ idx = EXCP_DEV_INTERRUPT;
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+ }
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+ /* FALLTHRU */
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+ case 4:
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+ if (interrupt_request & CPU_INTERRUPT_TIMER) {
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+ idx = EXCP_CLK_INTERRUPT;
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+ }
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+ /* FALLTHRU */
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+ case 5:
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+ if (interrupt_request & CPU_INTERRUPT_SMP) {
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+ idx = EXCP_SMP_INTERRUPT;
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+ }
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+ /* FALLTHRU */
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+ case 6:
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+ if (interrupt_request & CPU_INTERRUPT_MCHK) {
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+ idx = EXCP_MCHK;
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+ }
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+ }
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+ if (idx >= 0) {
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+ env->exception_index = idx;
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+ env->error_code = 0;
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+ do_interrupt(env);
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+ next_tb = 0;
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+ }
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}
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#elif defined(TARGET_CRIS)
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if (interrupt_request & CPU_INTERRUPT_HARD
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@@ -569,7 +553,7 @@ int cpu_exec(CPUState *env1)
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next_tb = 0;
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}
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#endif
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- /* Don't use the cached interupt_request value,
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+ /* Don't use the cached interrupt_request value,
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do_interrupt may have updated the EXITTB flag. */
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if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
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env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
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@@ -709,593 +693,3 @@ int cpu_exec(CPUState *env1)
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cpu_single_env = NULL;
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return ret;
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}
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-
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-/* must only be called from the generated code as an exception can be
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- generated */
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-void tb_invalidate_page_range(target_ulong start, target_ulong end)
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-{
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- /* XXX: cannot enable it yet because it yields to MMU exception
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- where NIP != read address on PowerPC */
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-#if 0
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- target_ulong phys_addr;
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- phys_addr = get_phys_addr_code(env, start);
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- tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
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-#endif
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-}
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-
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-#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
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-
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-void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
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-{
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- CPUX86State *saved_env;
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-
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- saved_env = env;
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- env = s;
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- if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
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- selector &= 0xffff;
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- cpu_x86_load_seg_cache(env, seg_reg, selector,
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- (selector << 4), 0xffff, 0);
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- } else {
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- helper_load_seg(seg_reg, selector);
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- }
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- env = saved_env;
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-}
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-
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-void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
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-{
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- CPUX86State *saved_env;
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-
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- saved_env = env;
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- env = s;
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-
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- helper_fsave(ptr, data32);
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-
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- env = saved_env;
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-}
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-
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-void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
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-{
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- CPUX86State *saved_env;
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-
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- saved_env = env;
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- env = s;
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-
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- helper_frstor(ptr, data32);
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-
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- env = saved_env;
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-}
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-
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-#endif /* TARGET_I386 */
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-
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-#if !defined(CONFIG_SOFTMMU)
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-
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-#if defined(TARGET_I386)
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-#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
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-#else
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-#define EXCEPTION_ACTION cpu_loop_exit()
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-#endif
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-
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-/* 'pc' is the host PC at which the exception was raised. 'address' is
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- the effective address of the memory exception. 'is_write' is 1 if a
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- write caused the exception and otherwise 0'. 'old_set' is the
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- signal set which should be restored */
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-static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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- int is_write, sigset_t *old_set,
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- void *puc)
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-{
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- TranslationBlock *tb;
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- int ret;
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-
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- if (cpu_single_env)
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- env = cpu_single_env; /* XXX: find a correct solution for multithread */
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-#if defined(DEBUG_SIGNAL)
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- qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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- pc, address, is_write, *(unsigned long *)old_set);
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-#endif
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- /* XXX: locking issue */
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- if (is_write && page_unprotect(h2g(address), pc, puc)) {
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- return 1;
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- }
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-
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- /* see if it is an MMU fault */
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- ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
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- if (ret < 0)
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- return 0; /* not an MMU fault */
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- if (ret == 0)
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- return 1; /* the MMU fault was handled without causing real CPU fault */
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- /* now we have a real cpu fault */
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- tb = tb_find_pc(pc);
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- if (tb) {
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- /* the PC is inside the translated code. It means that we have
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- a virtual CPU fault */
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- cpu_restore_state(tb, env, pc);
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- }
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-
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- /* we restore the process signal mask as the sigreturn should
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- do it (XXX: use sigsetjmp) */
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- sigprocmask(SIG_SETMASK, old_set, NULL);
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- EXCEPTION_ACTION;
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-
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- /* never comes here */
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- return 1;
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-}
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-
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-#if defined(__i386__)
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-
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-#if defined(__APPLE__)
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-# include <sys/ucontext.h>
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-
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-# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
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-# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
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-# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
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-# define MASK_sig(context) ((context)->uc_sigmask)
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-#elif defined (__NetBSD__)
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-# include <ucontext.h>
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-
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-# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
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-# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
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-# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
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-# define MASK_sig(context) ((context)->uc_sigmask)
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-#elif defined (__FreeBSD__) || defined(__DragonFly__)
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-# include <ucontext.h>
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-
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-# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
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-# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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-# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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-# define MASK_sig(context) ((context)->uc_sigmask)
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-#elif defined(__OpenBSD__)
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-# define EIP_sig(context) ((context)->sc_eip)
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-# define TRAP_sig(context) ((context)->sc_trapno)
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-# define ERROR_sig(context) ((context)->sc_err)
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-# define MASK_sig(context) ((context)->sc_mask)
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-#else
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-# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
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-# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
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-# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
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-# define MASK_sig(context) ((context)->uc_sigmask)
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-#endif
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-
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-int cpu_signal_handler(int host_signum, void *pinfo,
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- void *puc)
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-{
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- siginfo_t *info = pinfo;
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-#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
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- ucontext_t *uc = puc;
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-#elif defined(__OpenBSD__)
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- struct sigcontext *uc = puc;
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-#else
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- struct ucontext *uc = puc;
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-#endif
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- unsigned long pc;
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- int trapno;
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-
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-#ifndef REG_EIP
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-/* for glibc 2.1 */
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-#define REG_EIP EIP
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-#define REG_ERR ERR
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-#define REG_TRAPNO TRAPNO
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-#endif
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- pc = EIP_sig(uc);
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- trapno = TRAP_sig(uc);
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- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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- trapno == 0xe ?
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- (ERROR_sig(uc) >> 1) & 1 : 0,
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- &MASK_sig(uc), puc);
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-}
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-
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-#elif defined(__x86_64__)
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-
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-#ifdef __NetBSD__
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-#define PC_sig(context) _UC_MACHINE_PC(context)
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-#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
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-#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
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-#define MASK_sig(context) ((context)->uc_sigmask)
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-#elif defined(__OpenBSD__)
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-#define PC_sig(context) ((context)->sc_rip)
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-#define TRAP_sig(context) ((context)->sc_trapno)
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-#define ERROR_sig(context) ((context)->sc_err)
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-#define MASK_sig(context) ((context)->sc_mask)
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-#elif defined (__FreeBSD__) || defined(__DragonFly__)
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-#include <ucontext.h>
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-
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-#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
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-#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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-#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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-#define MASK_sig(context) ((context)->uc_sigmask)
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-#else
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-#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
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-#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
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-#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
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-#define MASK_sig(context) ((context)->uc_sigmask)
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-#endif
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-
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-int cpu_signal_handler(int host_signum, void *pinfo,
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- void *puc)
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-{
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- siginfo_t *info = pinfo;
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- unsigned long pc;
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-#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
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- ucontext_t *uc = puc;
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-#elif defined(__OpenBSD__)
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- struct sigcontext *uc = puc;
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-#else
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- struct ucontext *uc = puc;
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-#endif
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-
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- pc = PC_sig(uc);
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- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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- TRAP_sig(uc) == 0xe ?
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- (ERROR_sig(uc) >> 1) & 1 : 0,
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- &MASK_sig(uc), puc);
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-}
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-
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-#elif defined(_ARCH_PPC)
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-
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-/***********************************************************************
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- * signal context platform-specific definitions
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- * From Wine
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- */
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-#ifdef linux
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-/* All Registers access - only for local access */
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-# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
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-/* Gpr Registers access */
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-# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
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-# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
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-# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
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-# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
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-# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
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-# define LR_sig(context) REG_sig(link, context) /* Link register */
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|
|
-# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
|
|
|
-/* Float Registers access */
|
|
|
-# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
|
|
|
-# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
|
|
|
-/* Exception Registers access */
|
|
|
-# define DAR_sig(context) REG_sig(dar, context)
|
|
|
-# define DSISR_sig(context) REG_sig(dsisr, context)
|
|
|
-# define TRAP_sig(context) REG_sig(trap, context)
|
|
|
-#endif /* linux */
|
|
|
-
|
|
|
-#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
|
|
|
-#include <ucontext.h>
|
|
|
-# define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
|
|
|
-# define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
|
|
|
-# define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
|
|
|
-# define XER_sig(context) ((context)->uc_mcontext.mc_xer)
|
|
|
-# define LR_sig(context) ((context)->uc_mcontext.mc_lr)
|
|
|
-# define CR_sig(context) ((context)->uc_mcontext.mc_cr)
|
|
|
-/* Exception Registers access */
|
|
|
-# define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
|
|
|
-# define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
|
|
|
-# define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
|
|
|
-#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
|
|
|
-
|
|
|
-#ifdef __APPLE__
|
|
|
-# include <sys/ucontext.h>
|
|
|
-typedef struct ucontext SIGCONTEXT;
|
|
|
-/* All Registers access - only for local access */
|
|
|
-# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
|
|
-# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
|
|
-# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
|
|
-# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
|
|
-/* Gpr Registers access */
|
|
|
-# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
|
|
|
-# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
|
|
|
-# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
|
|
|
-# define CTR_sig(context) REG_sig(ctr, context)
|
|
|
-# define XER_sig(context) REG_sig(xer, context) /* Link register */
|
|
|
-# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
|
|
|
-# define CR_sig(context) REG_sig(cr, context) /* Condition register */
|
|
|
-/* Float Registers access */
|
|
|
-# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
|
|
-# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
|
|
|
-/* Exception Registers access */
|
|
|
-# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
|
|
|
-# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
|
|
-# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
|
|
|
-#endif /* __APPLE__ */
|
|
|
-
|
|
|
-int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
- void *puc)
|
|
|
-{
|
|
|
- siginfo_t *info = pinfo;
|
|
|
-#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
|
|
|
- ucontext_t *uc = puc;
|
|
|
-#else
|
|
|
- struct ucontext *uc = puc;
|
|
|
-#endif
|
|
|
- unsigned long pc;
|
|
|
- int is_write;
|
|
|
-
|
|
|
- pc = IAR_sig(uc);
|
|
|
- is_write = 0;
|
|
|
-#if 0
|
|
|
- /* ppc 4xx case */
|
|
|
- if (DSISR_sig(uc) & 0x00800000)
|
|
|
- is_write = 1;
|
|
|
-#else
|
|
|
- if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
|
|
|
- is_write = 1;
|
|
|
-#endif
|
|
|
- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
- is_write, &uc->uc_sigmask, puc);
|
|
|
-}
|
|
|
-
|
|
|
-#elif defined(__alpha__)
|
|
|
-
|
|
|
-int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
- void *puc)
|
|
|
-{
|
|
|
- siginfo_t *info = pinfo;
|
|
|
- struct ucontext *uc = puc;
|
|
|
- uint32_t *pc = uc->uc_mcontext.sc_pc;
|
|
|
- uint32_t insn = *pc;
|
|
|
- int is_write = 0;
|
|
|
-
|
|
|
- /* XXX: need kernel patch to get write flag faster */
|
|
|
- switch (insn >> 26) {
|
|
|
- case 0x0d: // stw
|
|
|
- case 0x0e: // stb
|
|
|
- case 0x0f: // stq_u
|
|
|
- case 0x24: // stf
|
|
|
- case 0x25: // stg
|
|
|
- case 0x26: // sts
|
|
|
- case 0x27: // stt
|
|
|
- case 0x2c: // stl
|
|
|
- case 0x2d: // stq
|
|
|
- case 0x2e: // stl_c
|
|
|
- case 0x2f: // stq_c
|
|
|
- is_write = 1;
|
|
|
- }
|
|
|
-
|
|
|
- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
- is_write, &uc->uc_sigmask, puc);
|
|
|
-}
|
|
|
-#elif defined(__sparc__)
|
|
|
-
|
|
|
-int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
- void *puc)
|
|
|
-{
|
|
|
- siginfo_t *info = pinfo;
|
|
|
- int is_write;
|
|
|
- uint32_t insn;
|
|
|
-#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
|
|
|
- uint32_t *regs = (uint32_t *)(info + 1);
|
|
|
- void *sigmask = (regs + 20);
|
|
|
- /* XXX: is there a standard glibc define ? */
|
|
|
- unsigned long pc = regs[1];
|
|
|
-#else
|
|
|
-#ifdef __linux__
|
|
|
- struct sigcontext *sc = puc;
|
|
|
- unsigned long pc = sc->sigc_regs.tpc;
|
|
|
- void *sigmask = (void *)sc->sigc_mask;
|
|
|
-#elif defined(__OpenBSD__)
|
|
|
- struct sigcontext *uc = puc;
|
|
|
- unsigned long pc = uc->sc_pc;
|
|
|
- void *sigmask = (void *)(long)uc->sc_mask;
|
|
|
-#endif
|
|
|
-#endif
|
|
|
-
|
|
|
- /* XXX: need kernel patch to get write flag faster */
|
|
|
- is_write = 0;
|
|
|
- insn = *(uint32_t *)pc;
|
|
|
- if ((insn >> 30) == 3) {
|
|
|
- switch((insn >> 19) & 0x3f) {
|
|
|
- case 0x05: // stb
|
|
|
- case 0x15: // stba
|
|
|
- case 0x06: // sth
|
|
|
- case 0x16: // stha
|
|
|
- case 0x04: // st
|
|
|
- case 0x14: // sta
|
|
|
- case 0x07: // std
|
|
|
- case 0x17: // stda
|
|
|
- case 0x0e: // stx
|
|
|
- case 0x1e: // stxa
|
|
|
- case 0x24: // stf
|
|
|
- case 0x34: // stfa
|
|
|
- case 0x27: // stdf
|
|
|
- case 0x37: // stdfa
|
|
|
- case 0x26: // stqf
|
|
|
- case 0x36: // stqfa
|
|
|
- case 0x25: // stfsr
|
|
|
- case 0x3c: // casa
|
|
|
- case 0x3e: // casxa
|
|
|
- is_write = 1;
|
|
|
- break;
|
|
|
- }
|
|
|
- }
|
|
|
- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
- is_write, sigmask, NULL);
|
|
|
-}
|
|
|
-
|
|
|
-#elif defined(__arm__)
|
|
|
-
|
|
|
-int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
- void *puc)
|
|
|
-{
|
|
|
- siginfo_t *info = pinfo;
|
|
|
- struct ucontext *uc = puc;
|
|
|
- unsigned long pc;
|
|
|
- int is_write;
|
|
|
-
|
|
|
-#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
|
|
|
- pc = uc->uc_mcontext.gregs[R15];
|
|
|
-#else
|
|
|
- pc = uc->uc_mcontext.arm_pc;
|
|
|
-#endif
|
|
|
- /* XXX: compute is_write */
|
|
|
- is_write = 0;
|
|
|
- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
- is_write,
|
|
|
- &uc->uc_sigmask, puc);
|
|
|
-}
|
|
|
-
|
|
|
-#elif defined(__mc68000)
|
|
|
-
|
|
|
-int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
- void *puc)
|
|
|
-{
|
|
|
- siginfo_t *info = pinfo;
|
|
|
- struct ucontext *uc = puc;
|
|
|
- unsigned long pc;
|
|
|
- int is_write;
|
|
|
-
|
|
|
- pc = uc->uc_mcontext.gregs[16];
|
|
|
- /* XXX: compute is_write */
|
|
|
- is_write = 0;
|
|
|
- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
- is_write,
|
|
|
- &uc->uc_sigmask, puc);
|
|
|
-}
|
|
|
-
|
|
|
-#elif defined(__ia64)
|
|
|
-
|
|
|
-#ifndef __ISR_VALID
|
|
|
- /* This ought to be in <bits/siginfo.h>... */
|
|
|
-# define __ISR_VALID 1
|
|
|
-#endif
|
|
|
-
|
|
|
-int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
|
|
|
-{
|
|
|
- siginfo_t *info = pinfo;
|
|
|
- struct ucontext *uc = puc;
|
|
|
- unsigned long ip;
|
|
|
- int is_write = 0;
|
|
|
-
|
|
|
- ip = uc->uc_mcontext.sc_ip;
|
|
|
- switch (host_signum) {
|
|
|
- case SIGILL:
|
|
|
- case SIGFPE:
|
|
|
- case SIGSEGV:
|
|
|
- case SIGBUS:
|
|
|
- case SIGTRAP:
|
|
|
- if (info->si_code && (info->si_segvflags & __ISR_VALID))
|
|
|
- /* ISR.W (write-access) is bit 33: */
|
|
|
- is_write = (info->si_isr >> 33) & 1;
|
|
|
- break;
|
|
|
-
|
|
|
- default:
|
|
|
- break;
|
|
|
- }
|
|
|
- return handle_cpu_signal(ip, (unsigned long)info->si_addr,
|
|
|
- is_write,
|
|
|
- (sigset_t *)&uc->uc_sigmask, puc);
|
|
|
-}
|
|
|
-
|
|
|
-#elif defined(__s390__)
|
|
|
-
|
|
|
-int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
- void *puc)
|
|
|
-{
|
|
|
- siginfo_t *info = pinfo;
|
|
|
- struct ucontext *uc = puc;
|
|
|
- unsigned long pc;
|
|
|
- uint16_t *pinsn;
|
|
|
- int is_write = 0;
|
|
|
-
|
|
|
- pc = uc->uc_mcontext.psw.addr;
|
|
|
-
|
|
|
- /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
|
|
|
- of the normal 2 arguments. The 3rd argument contains the "int_code"
|
|
|
- from the hardware which does in fact contain the is_write value.
|
|
|
- The rt signal handler, as far as I can tell, does not give this value
|
|
|
- at all. Not that we could get to it from here even if it were. */
|
|
|
- /* ??? This is not even close to complete, since it ignores all
|
|
|
- of the read-modify-write instructions. */
|
|
|
- pinsn = (uint16_t *)pc;
|
|
|
- switch (pinsn[0] >> 8) {
|
|
|
- case 0x50: /* ST */
|
|
|
- case 0x42: /* STC */
|
|
|
- case 0x40: /* STH */
|
|
|
- is_write = 1;
|
|
|
- break;
|
|
|
- case 0xc4: /* RIL format insns */
|
|
|
- switch (pinsn[0] & 0xf) {
|
|
|
- case 0xf: /* STRL */
|
|
|
- case 0xb: /* STGRL */
|
|
|
- case 0x7: /* STHRL */
|
|
|
- is_write = 1;
|
|
|
- }
|
|
|
- break;
|
|
|
- case 0xe3: /* RXY format insns */
|
|
|
- switch (pinsn[2] & 0xff) {
|
|
|
- case 0x50: /* STY */
|
|
|
- case 0x24: /* STG */
|
|
|
- case 0x72: /* STCY */
|
|
|
- case 0x70: /* STHY */
|
|
|
- case 0x8e: /* STPQ */
|
|
|
- case 0x3f: /* STRVH */
|
|
|
- case 0x3e: /* STRV */
|
|
|
- case 0x2f: /* STRVG */
|
|
|
- is_write = 1;
|
|
|
- }
|
|
|
- break;
|
|
|
- }
|
|
|
- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
- is_write, &uc->uc_sigmask, puc);
|
|
|
-}
|
|
|
-
|
|
|
-#elif defined(__mips__)
|
|
|
-
|
|
|
-int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
- void *puc)
|
|
|
-{
|
|
|
- siginfo_t *info = pinfo;
|
|
|
- struct ucontext *uc = puc;
|
|
|
- greg_t pc = uc->uc_mcontext.pc;
|
|
|
- int is_write;
|
|
|
-
|
|
|
- /* XXX: compute is_write */
|
|
|
- is_write = 0;
|
|
|
- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
- is_write, &uc->uc_sigmask, puc);
|
|
|
-}
|
|
|
-
|
|
|
-#elif defined(__hppa__)
|
|
|
-
|
|
|
-int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
- void *puc)
|
|
|
-{
|
|
|
- struct siginfo *info = pinfo;
|
|
|
- struct ucontext *uc = puc;
|
|
|
- unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
|
|
|
- uint32_t insn = *(uint32_t *)pc;
|
|
|
- int is_write = 0;
|
|
|
-
|
|
|
- /* XXX: need kernel patch to get write flag faster. */
|
|
|
- switch (insn >> 26) {
|
|
|
- case 0x1a: /* STW */
|
|
|
- case 0x19: /* STH */
|
|
|
- case 0x18: /* STB */
|
|
|
- case 0x1b: /* STWM */
|
|
|
- is_write = 1;
|
|
|
- break;
|
|
|
-
|
|
|
- case 0x09: /* CSTWX, FSTWX, FSTWS */
|
|
|
- case 0x0b: /* CSTDX, FSTDX, FSTDS */
|
|
|
- /* Distinguish from coprocessor load ... */
|
|
|
- is_write = (insn >> 9) & 1;
|
|
|
- break;
|
|
|
-
|
|
|
- case 0x03:
|
|
|
- switch ((insn >> 6) & 15) {
|
|
|
- case 0xa: /* STWS */
|
|
|
- case 0x9: /* STHS */
|
|
|
- case 0x8: /* STBS */
|
|
|
- case 0xe: /* STWAS */
|
|
|
- case 0xc: /* STBYS */
|
|
|
- is_write = 1;
|
|
|
- }
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
- is_write, &uc->uc_sigmask, puc);
|
|
|
-}
|
|
|
-
|
|
|
-#else
|
|
|
-
|
|
|
-#error host CPU specific signal handler needed
|
|
|
-
|
|
|
-#endif
|
|
|
-
|
|
|
-#endif /* !defined(CONFIG_SOFTMMU) */
|