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@@ -311,6 +311,29 @@ static const mips_def_t mips_defs[] =
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
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.mmu_type = MMU_TYPE_R4000,
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},
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+ {
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+ .name = "74Kf",
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+ .CP0_PRid = 0x00019700,
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+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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+ (MMU_TYPE_R4000 << CP0C0_MT),
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+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
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+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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+ (1 << CP0C1_CA),
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+ .CP0_Config2 = MIPS_CONFIG2,
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+ .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
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+ .CP0_LLAddr_rw_bitmask = 0,
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+ .CP0_LLAddr_shift = 4,
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+ .SYNCI_Step = 32,
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+ .CCRes = 2,
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+ .CP0_Status_rw_bitmask = 0x3778FF1F,
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+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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+ .SEGBITS = 32,
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+ .PABITS = 32,
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+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
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+ .mmu_type = MMU_TYPE_R4000,
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+ },
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#if defined(TARGET_MIPS64)
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{
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.name = "R4000",
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@@ -484,6 +507,35 @@ static const mips_def_t mips_defs[] =
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.insn_flags = CPU_LOONGSON2F,
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.mmu_type = MMU_TYPE_R4000,
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},
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+ {
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+ /* A generic CPU providing MIPS64 ASE DSP 2 features.
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+ FIXME: Eventually this should be replaced by a real CPU model. */
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+ .name = "mips64dspr2",
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+ .CP0_PRid = 0x00010000,
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+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
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+ (MMU_TYPE_R4000 << CP0C0_MT),
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+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
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+ (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
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+ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
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+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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+ .CP0_Config2 = MIPS_CONFIG2,
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+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
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+ .CP0_LLAddr_rw_bitmask = 0,
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+ .CP0_LLAddr_shift = 0,
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+ .SYNCI_Step = 32,
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+ .CCRes = 2,
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+ .CP0_Status_rw_bitmask = 0x37FBFFFF,
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+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
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+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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+ (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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+ .SEGBITS = 42,
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+ /* The architectural limit is 59, but we have hardcoded 36 bit
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+ in some places...
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+ .PABITS = 59, */ /* the architectural limit */
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+ .PABITS = 36,
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+ .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
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+ .mmu_type = MMU_TYPE_R4000,
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+ },
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#endif
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};
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