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@@ -549,20 +549,28 @@ static const MemoryRegionOps tcx_stip_ops = {
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.read = tcx_stip_readl,
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.read = tcx_stip_readl,
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.write = tcx_stip_writel,
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.write = tcx_stip_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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- .valid = {
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+ .impl = {
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.min_access_size = 4,
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.min_access_size = 4,
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.max_access_size = 4,
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.max_access_size = 4,
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},
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},
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+ .valid = {
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+ .min_access_size = 4,
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+ .max_access_size = 8,
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+ },
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};
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};
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static const MemoryRegionOps tcx_rstip_ops = {
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static const MemoryRegionOps tcx_rstip_ops = {
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.read = tcx_stip_readl,
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.read = tcx_stip_readl,
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.write = tcx_rstip_writel,
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.write = tcx_rstip_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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- .valid = {
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+ .impl = {
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.min_access_size = 4,
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.min_access_size = 4,
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.max_access_size = 4,
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.max_access_size = 4,
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},
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},
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+ .valid = {
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+ .min_access_size = 4,
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+ .max_access_size = 8,
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+ },
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};
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};
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static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
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static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
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@@ -651,10 +659,14 @@ static const MemoryRegionOps tcx_rblit_ops = {
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.read = tcx_blit_readl,
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.read = tcx_blit_readl,
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.write = tcx_rblit_writel,
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.write = tcx_rblit_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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- .valid = {
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+ .impl = {
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.min_access_size = 4,
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.min_access_size = 4,
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.max_access_size = 4,
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.max_access_size = 4,
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},
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},
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+ .valid = {
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+ .min_access_size = 4,
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+ .max_access_size = 8,
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+ },
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};
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};
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static void tcx_invalidate_cursor_position(TCXState *s)
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static void tcx_invalidate_cursor_position(TCXState *s)
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