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@@ -164,11 +164,12 @@ static uint32_t aspeed_scu_get_random(void)
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return num;
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return num;
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}
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}
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-static void aspeed_scu_set_apb_freq(AspeedSCUState *s)
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+uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
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{
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{
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AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
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AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
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+ uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]);
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- s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
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+ return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
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/ asc->apb_divider;
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/ asc->apb_divider;
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}
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}
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@@ -228,7 +229,6 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
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return;
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return;
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case CLK_SEL:
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case CLK_SEL:
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s->regs[reg] = data;
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s->regs[reg] = data;
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- aspeed_scu_set_apb_freq(s);
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break;
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break;
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case HW_STRAP1:
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case HW_STRAP1:
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if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
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if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
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@@ -290,11 +290,11 @@ static const uint32_t hpll_ast2400_freqs[][4] = {
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{ 400, 375, 350, 425 }, /* 25MHz */
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{ 400, 375, 350, 425 }, /* 25MHz */
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};
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};
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-static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s)
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+static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
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{
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{
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- uint32_t hpll_reg = s->regs[HPLL_PARAM];
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uint8_t freq_select;
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uint8_t freq_select;
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bool clk_25m_in;
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bool clk_25m_in;
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+ uint32_t clkin = aspeed_scu_get_clkin(s);
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if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
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if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
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return 0;
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return 0;
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@@ -311,7 +311,7 @@ static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s)
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multiplier = (2 - od) * ((n + 2) / (d + 1));
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multiplier = (2 - od) * ((n + 2) / (d + 1));
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}
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}
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- return s->clkin * multiplier;
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+ return clkin * multiplier;
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}
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}
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/* HW strapping */
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/* HW strapping */
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@@ -321,10 +321,10 @@ static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s)
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return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
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return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
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}
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}
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-static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s)
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+static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
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{
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{
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- uint32_t hpll_reg = s->regs[HPLL_PARAM];
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uint32_t multiplier = 1;
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uint32_t multiplier = 1;
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+ uint32_t clkin = aspeed_scu_get_clkin(s);
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if (hpll_reg & SCU_H_PLL_OFF) {
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if (hpll_reg & SCU_H_PLL_OFF) {
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return 0;
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return 0;
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@@ -338,7 +338,7 @@ static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s)
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multiplier = ((m + 1) / (n + 1)) / (p + 1);
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multiplier = ((m + 1) / (n + 1)) / (p + 1);
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}
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}
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- return s->clkin * multiplier;
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+ return clkin * multiplier;
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}
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}
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static void aspeed_scu_reset(DeviceState *dev)
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static void aspeed_scu_reset(DeviceState *dev)
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@@ -351,13 +351,6 @@ static void aspeed_scu_reset(DeviceState *dev)
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s->regs[HW_STRAP1] = s->hw_strap1;
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s->regs[HW_STRAP1] = s->hw_strap1;
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s->regs[HW_STRAP2] = s->hw_strap2;
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s->regs[HW_STRAP2] = s->hw_strap2;
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s->regs[PROT_KEY] = s->hw_prot_key;
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s->regs[PROT_KEY] = s->hw_prot_key;
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-
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- /*
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- * All registers are set. Now compute the frequencies of the main clocks
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- */
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- s->clkin = aspeed_scu_get_clkin(s);
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- s->hpll = asc->calc_hpll(s);
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- aspeed_scu_set_apb_freq(s);
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}
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}
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static uint32_t aspeed_silicon_revs[] = {
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static uint32_t aspeed_silicon_revs[] = {
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