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@@ -75,24 +75,30 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
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return loongson_ipi_core_readl(s, addr, data, size, attrs);
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}
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-static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
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-{
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#ifdef TARGET_LOONGARCH64
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+static AddressSpace *get_iocsr_as(CPUState *cpu)
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+{
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return LOONGARCH_CPU(cpu)->env.address_space_iocsr;
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+}
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#endif
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+
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#ifdef TARGET_MIPS
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+static AddressSpace *get_iocsr_as(CPUState *cpu)
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+{
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if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
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return &MIPS_CPU(cpu)->env.iocsr.as;
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}
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-#endif
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+
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return NULL;
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}
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+#endif
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static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
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uint64_t val, hwaddr addr, MemTxAttrs attrs)
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{
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+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
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int i, mask = 0, data = 0;
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- AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu);
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+ AddressSpace *iocsr_as = licc->get_iocsr_as(cpu);
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if (!iocsr_as) {
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return MEMTX_DECODE_ERROR;
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@@ -354,11 +360,13 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass);
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+ LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass);
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device_class_set_parent_realize(dc, loongson_ipi_realize,
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&lic->parent_realize);
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device_class_set_parent_unrealize(dc, loongson_ipi_unrealize,
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&lic->parent_unrealize);
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+ licc->get_iocsr_as = get_iocsr_as;
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}
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static const TypeInfo loongson_ipi_types[] = {
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