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@@ -42,6 +42,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
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MO_32 | devend_memop(endian), attrs);
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} else {
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/* RAM case */
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+ fuzz_dma_read_cb(addr, 4, mr, false);
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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@@ -110,6 +111,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
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MO_64 | devend_memop(endian), attrs);
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} else {
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/* RAM case */
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+ fuzz_dma_read_cb(addr, 8, mr, false);
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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@@ -175,6 +177,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
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r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs);
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} else {
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/* RAM case */
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+ fuzz_dma_read_cb(addr, 1, mr, false);
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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val = ldub_p(ptr);
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r = MEMTX_OK;
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@@ -212,6 +215,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
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MO_16 | devend_memop(endian), attrs);
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} else {
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/* RAM case */
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+ fuzz_dma_read_cb(addr, 2, mr, false);
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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