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@@ -102,20 +102,34 @@ static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
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trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn);
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trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn);
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}
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}
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-static inline MemTxResult queue_read(SMMUQueue *q, void *data)
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+static inline MemTxResult queue_read(SMMUQueue *q, Cmd *cmd)
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{
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{
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dma_addr_t addr = Q_CONS_ENTRY(q);
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dma_addr_t addr = Q_CONS_ENTRY(q);
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+ MemTxResult ret;
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+ int i;
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- return dma_memory_read(&address_space_memory, addr, data, q->entry_size,
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- MEMTXATTRS_UNSPECIFIED);
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+ ret = dma_memory_read(&address_space_memory, addr, cmd, sizeof(Cmd),
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+ MEMTXATTRS_UNSPECIFIED);
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+ if (ret != MEMTX_OK) {
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+ return ret;
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+ }
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+ for (i = 0; i < ARRAY_SIZE(cmd->word); i++) {
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+ le32_to_cpus(&cmd->word[i]);
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+ }
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+ return ret;
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}
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}
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-static MemTxResult queue_write(SMMUQueue *q, void *data)
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+static MemTxResult queue_write(SMMUQueue *q, Evt *evt_in)
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{
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{
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dma_addr_t addr = Q_PROD_ENTRY(q);
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dma_addr_t addr = Q_PROD_ENTRY(q);
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MemTxResult ret;
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MemTxResult ret;
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+ Evt evt = *evt_in;
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+ int i;
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- ret = dma_memory_write(&address_space_memory, addr, data, q->entry_size,
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+ for (i = 0; i < ARRAY_SIZE(evt.word); i++) {
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+ cpu_to_le32s(&evt.word[i]);
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+ }
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+ ret = dma_memory_write(&address_space_memory, addr, &evt, sizeof(Evt),
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MEMTXATTRS_UNSPECIFIED);
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MEMTXATTRS_UNSPECIFIED);
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if (ret != MEMTX_OK) {
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if (ret != MEMTX_OK) {
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return ret;
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return ret;
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@@ -298,7 +312,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
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static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
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static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
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SMMUEventInfo *event)
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SMMUEventInfo *event)
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{
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{
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- int ret;
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+ int ret, i;
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trace_smmuv3_get_ste(addr);
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trace_smmuv3_get_ste(addr);
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/* TODO: guarantee 64-bit single-copy atomicity */
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/* TODO: guarantee 64-bit single-copy atomicity */
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@@ -311,6 +325,9 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
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event->u.f_ste_fetch.addr = addr;
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event->u.f_ste_fetch.addr = addr;
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return -EINVAL;
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return -EINVAL;
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}
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}
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+ for (i = 0; i < ARRAY_SIZE(buf->word); i++) {
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+ le32_to_cpus(&buf->word[i]);
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+ }
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return 0;
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return 0;
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}
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}
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@@ -320,7 +337,7 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
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CD *buf, SMMUEventInfo *event)
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CD *buf, SMMUEventInfo *event)
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{
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{
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dma_addr_t addr = STE_CTXPTR(ste);
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dma_addr_t addr = STE_CTXPTR(ste);
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- int ret;
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+ int ret, i;
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trace_smmuv3_get_cd(addr);
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trace_smmuv3_get_cd(addr);
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/* TODO: guarantee 64-bit single-copy atomicity */
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/* TODO: guarantee 64-bit single-copy atomicity */
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@@ -333,6 +350,9 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
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event->u.f_ste_fetch.addr = addr;
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event->u.f_ste_fetch.addr = addr;
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return -EINVAL;
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return -EINVAL;
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}
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}
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+ for (i = 0; i < ARRAY_SIZE(buf->word); i++) {
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+ le32_to_cpus(&buf->word[i]);
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+ }
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return 0;
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return 0;
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}
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}
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@@ -569,7 +589,7 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
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return -EINVAL;
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return -EINVAL;
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}
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}
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if (s->features & SMMU_FEATURE_2LVL_STE) {
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if (s->features & SMMU_FEATURE_2LVL_STE) {
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- int l1_ste_offset, l2_ste_offset, max_l2_ste, span;
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+ int l1_ste_offset, l2_ste_offset, max_l2_ste, span, i;
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dma_addr_t l1ptr, l2ptr;
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dma_addr_t l1ptr, l2ptr;
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STEDesc l1std;
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STEDesc l1std;
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@@ -593,6 +613,9 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
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event->u.f_ste_fetch.addr = l1ptr;
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event->u.f_ste_fetch.addr = l1ptr;
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return -EINVAL;
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return -EINVAL;
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}
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}
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+ for (i = 0; i < ARRAY_SIZE(l1std.word); i++) {
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+ le32_to_cpus(&l1std.word[i]);
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+ }
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span = L1STD_SPAN(&l1std);
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span = L1STD_SPAN(&l1std);
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