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@@ -439,43 +439,6 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
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qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
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}
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-static uint64_t spapr_io_read(void *opaque, hwaddr addr,
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- unsigned size)
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-{
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- switch (size) {
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- case 1:
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- return cpu_inb(addr);
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- case 2:
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- return cpu_inw(addr);
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- case 4:
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- return cpu_inl(addr);
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- }
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- assert(0);
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-}
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-
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-static void spapr_io_write(void *opaque, hwaddr addr,
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- uint64_t data, unsigned size)
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-{
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- switch (size) {
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- case 1:
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- cpu_outb(addr, data);
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- return;
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- case 2:
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- cpu_outw(addr, data);
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- return;
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- case 4:
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- cpu_outl(addr, data);
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- return;
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- }
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- assert(0);
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-}
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-
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-static const MemoryRegionOps spapr_io_ops = {
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- .endianness = DEVICE_LITTLE_ENDIAN,
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- .read = spapr_io_read,
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- .write = spapr_io_write
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-};
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-
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/*
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* MSI/MSIX memory region implementation.
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* The handler handles both MSI and MSIX.
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@@ -545,14 +508,9 @@ static int spapr_phb_init(SysBusDevice *s)
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* old_portion are updated */
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sprintf(namebuf, "%s.io", sphb->dtbusname);
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memory_region_init(&sphb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
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- /* FIXME: fix to support multiple PHBs */
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- memory_region_add_subregion(get_system_io(), 0, &sphb->iospace);
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- sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
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- memory_region_init_io(&sphb->iowindow, &spapr_io_ops, sphb,
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- namebuf, SPAPR_PCI_IO_WIN_SIZE);
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memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
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- &sphb->iowindow);
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+ &sphb->iospace);
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/* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
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* we need to allocate some memory to catch those writes coming
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