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@@ -74,8 +74,13 @@ static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
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Error **errp)
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{
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Q35PCIHost *s = Q35_HOST_DEVICE(obj);
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- uint32_t value = s->mch.pci_hole.begin;
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+ uint64_t val64;
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+ uint32_t value;
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+ val64 = range_is_empty(&s->mch.pci_hole)
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+ ? 0 : range_lob(&s->mch.pci_hole);
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+ value = val64;
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+ assert(value == val64);
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visit_type_uint32(v, name, &value, errp);
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}
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@@ -84,8 +89,13 @@ static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
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Error **errp)
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{
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Q35PCIHost *s = Q35_HOST_DEVICE(obj);
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- uint32_t value = s->mch.pci_hole.end;
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+ uint64_t val64;
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+ uint32_t value;
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+ val64 = range_is_empty(&s->mch.pci_hole)
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+ ? 0 : range_upb(&s->mch.pci_hole) + 1;
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+ value = val64;
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+ assert(value == val64);
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visit_type_uint32(v, name, &value, errp);
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}
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@@ -95,10 +105,11 @@ static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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Range w64;
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+ uint64_t value;
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pci_bus_get_w64_range(h->bus, &w64);
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-
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- visit_type_uint64(v, name, &w64.begin, errp);
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+ value = range_is_empty(&w64) ? 0 : range_lob(&w64);
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+ visit_type_uint64(v, name, &value, errp);
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}
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static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
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@@ -107,10 +118,11 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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Range w64;
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+ uint64_t value;
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pci_bus_get_w64_range(h->bus, &w64);
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-
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- visit_type_uint64(v, name, &w64.end, errp);
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+ value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
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+ visit_type_uint64(v, name, &value, errp);
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}
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static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name,
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@@ -205,9 +217,9 @@ static void q35_host_initfn(Object *obj)
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* it's not a power of two, which means an MTRR
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* can't cover it exactly.
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*/
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- s->mch.pci_hole.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
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- MCH_HOST_BRIDGE_PCIEXBAR_MAX;
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- s->mch.pci_hole.end = IO_APIC_DEFAULT_ADDRESS;
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+ range_set_bounds(&s->mch.pci_hole,
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+ MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX,
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+ IO_APIC_DEFAULT_ADDRESS - 1);
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}
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static const TypeInfo q35_host_info = {
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@@ -275,10 +287,7 @@ static void mch_update_pciexbar(MCHPCIState *mch)
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break;
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case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
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default:
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- enable = 0;
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- length = 0;
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abort();
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- break;
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}
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addr = pciexbar & addr_mask;
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pcie_host_mmcfg_update(pehb, enable, addr, length);
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@@ -288,9 +297,13 @@ static void mch_update_pciexbar(MCHPCIState *mch)
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* which means an MTRR can't cover it exactly.
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*/
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if (enable) {
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- mch->pci_hole.begin = addr + length;
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+ range_set_bounds(&mch->pci_hole,
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+ addr + length,
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+ IO_APIC_DEFAULT_ADDRESS - 1);
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} else {
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- mch->pci_hole.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
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+ range_set_bounds(&mch->pci_hole,
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+ MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT,
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+ IO_APIC_DEFAULT_ADDRESS - 1);
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}
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}
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