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@@ -58,6 +58,7 @@
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#include "semihosting/semihost.h"
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#include "semihosting/semihost.h"
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#include "hw/mips/cps.h"
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#include "hw/mips/cps.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-clock.h"
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+#include "trace.h"
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#define ENVP_PADDR 0x2000
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#define ENVP_PADDR 0x2000
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#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
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#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
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@@ -120,12 +121,14 @@ static void malta_fpga_update_display_leds(MaltaFPGAState *s)
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}
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}
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leds_text[8] = '\0';
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leds_text[8] = '\0';
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+ trace_malta_fpga_leds(leds_text);
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qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
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qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
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leds_text);
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leds_text);
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}
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}
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static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
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static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
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{
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{
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+ trace_malta_fpga_display(s->display_text);
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qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
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qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
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s->display_text);
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s->display_text);
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}
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}
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