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@@ -73,10 +73,9 @@ typedef struct APBState {
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uint32_t obio_irq_map[32];
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uint32_t obio_irq_map[32];
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qemu_irq pci_irqs[32];
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qemu_irq pci_irqs[32];
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uint32_t reset_control;
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uint32_t reset_control;
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+ unsigned int nr_resets;
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} APBState;
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} APBState;
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-static unsigned int nr_resets;
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-
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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uint32_t val)
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{
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{
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@@ -108,7 +107,7 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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s->reset_control &= ~(val & RESET_WCMASK);
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s->reset_control &= ~(val & RESET_WCMASK);
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s->reset_control |= val & RESET_WMASK;
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s->reset_control |= val & RESET_WMASK;
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if (val & SOFT_POR) {
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if (val & SOFT_POR) {
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- nr_resets = 0;
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+ s->nr_resets = 0;
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qemu_system_reset_request();
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qemu_system_reset_request();
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} else if (val & SOFT_XIR) {
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} else if (val & SOFT_XIR) {
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qemu_system_reset_request();
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qemu_system_reset_request();
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@@ -374,7 +373,7 @@ static void pci_pbm_reset(DeviceState *d)
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s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
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}
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}
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- if (nr_resets++ == 0) {
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+ if (s->nr_resets++ == 0) {
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/* Power on reset */
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/* Power on reset */
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s->reset_control = POR;
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s->reset_control = POR;
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}
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}
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