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@@ -705,16 +705,20 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0x300f: /* addv Rm,Rn */
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{
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- TCGv t0, t1, t2;
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- t0 = tcg_temp_new();
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- tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8));
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+ TCGv Rn = REG(B11_8);
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+ TCGv Rm = REG(B7_4);
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+ TCGv result, t1, t2;
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+
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+ result = tcg_temp_new();
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t1 = tcg_temp_new();
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- tcg_gen_xor_i32(t1, t0, REG(B11_8));
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t2 = tcg_temp_new();
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- tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8));
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+ tcg_gen_add_i32(result, Rm, Rn);
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+ /* T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31 */
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+ tcg_gen_xor_i32(t1, result, Rn);
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+ tcg_gen_xor_i32(t2, Rm, Rn);
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tcg_gen_andc_i32(cpu_sr_t, t1, t2);
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tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31);
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- tcg_gen_mov_i32(REG(B7_4), t0);
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+ tcg_gen_mov_i32(Rn, result);
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}
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return;
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case 0x2009: /* and Rm,Rn */
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@@ -929,16 +933,20 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0x300b: /* subv Rm,Rn */
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{
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- TCGv t0, t1, t2;
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- t0 = tcg_temp_new();
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- tcg_gen_sub_i32(t0, REG(B11_8), REG(B7_4));
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+ TCGv Rn = REG(B11_8);
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+ TCGv Rm = REG(B7_4);
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+ TCGv result, t1, t2;
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+
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+ result = tcg_temp_new();
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t1 = tcg_temp_new();
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- tcg_gen_xor_i32(t1, t0, REG(B7_4));
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t2 = tcg_temp_new();
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- tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4));
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+ tcg_gen_sub_i32(result, Rn, Rm);
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+ /* T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31 */
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+ tcg_gen_xor_i32(t1, result, Rn);
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+ tcg_gen_xor_i32(t2, Rn, Rm);
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tcg_gen_and_i32(t1, t1, t2);
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tcg_gen_shri_i32(cpu_sr_t, t1, 31);
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- tcg_gen_mov_i32(REG(B11_8), t0);
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+ tcg_gen_mov_i32(Rn, result);
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}
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return;
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case 0x2008: /* tst Rm,Rn */
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