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@@ -22,25 +22,17 @@
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#include "sysemu/sysemu.h"
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#include "sysemu/char.h"
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-//#define DEBUG_SERIAL 1
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-#ifdef DEBUG_SERIAL
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-#define DPRINTF(fmt, args...) \
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-do { printf("%s: " fmt , TYPE_IMX_SERIAL, ##args); } while (0)
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-#else
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-#define DPRINTF(fmt, args...) do {} while (0)
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+#ifndef DEBUG_IMX_UART
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+#define DEBUG_IMX_UART 0
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#endif
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-/*
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- * Define to 1 for messages about attempts to
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- * access unimplemented registers or similar.
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- */
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-//#define DEBUG_IMPLEMENTATION 1
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-#ifdef DEBUG_IMPLEMENTATION
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-# define IPRINTF(fmt, args...) \
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- do { fprintf(stderr, "%s: " fmt, TYPE_IMX_SERIAL, ##args); } while (0)
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-#else
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-# define IPRINTF(fmt, args...) do {} while (0)
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-#endif
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+#define DPRINTF(fmt, args...) \
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+ do { \
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+ if (DEBUG_IMX_UART) { \
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+ fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
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+ __func__, ##args); \
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+ } \
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+ } while (0)
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static const VMStateDescription vmstate_imx_serial = {
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.name = TYPE_IMX_SERIAL,
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@@ -115,7 +107,8 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
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IMXSerialState *s = (IMXSerialState *)opaque;
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uint32_t c;
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- DPRINTF("read(offset=%x)\n", offset >> 2);
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+ DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
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+
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switch (offset >> 2) {
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case 0x0: /* URXD */
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c = s->readbuff;
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@@ -167,7 +160,8 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
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return 0x0; /* TODO */
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default:
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- IPRINTF("%s: bad offset: 0x%x\n", __func__, (int)offset);
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+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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+ HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
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return 0;
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}
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}
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@@ -178,9 +172,8 @@ static void imx_serial_write(void *opaque, hwaddr offset,
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IMXSerialState *s = (IMXSerialState *)opaque;
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unsigned char ch;
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- DPRINTF("write(offset=%x, value = %x) to %s\n",
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- offset >> 2,
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- (unsigned int)value, s->chr ? s->chr->label : "NODEV");
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+ DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
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+ offset, (unsigned int)value, s->chr ? s->chr->label : "NODEV");
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switch (offset >> 2) {
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case 0x10: /* UTXD */
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@@ -198,7 +191,9 @@ static void imx_serial_write(void *opaque, hwaddr offset,
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case 0x20: /* UCR1 */
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s->ucr1 = value & 0xffff;
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+
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DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
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+
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imx_update(s);
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break;
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@@ -266,12 +261,14 @@ static void imx_serial_write(void *opaque, hwaddr offset,
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case 0x2d: /* UTS1 */
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case 0x23: /* UCR4 */
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- IPRINTF("Unimplemented Register %x written to\n", offset >> 2);
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+ qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
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+ HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
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/* TODO */
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break;
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default:
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- IPRINTF("%s: Bad offset 0x%x\n", __func__, (int)offset);
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+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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+ HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
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}
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}
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@@ -284,7 +281,9 @@ static int imx_can_receive(void *opaque)
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static void imx_put_data(void *opaque, uint32_t value)
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{
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IMXSerialState *s = (IMXSerialState *)opaque;
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+
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DPRINTF("received char\n");
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+
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s->usr1 |= USR1_RRDY;
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s->usr2 |= USR2_RDR;
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s->uts1 &= ~UTS1_RXEMPTY;
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@@ -319,8 +318,7 @@ static void imx_serial_realize(DeviceState *dev, Error **errp)
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qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
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imx_event, s);
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} else {
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- DPRINTF("No char dev for uart at 0x%lx\n",
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- (unsigned long)s->iomem.ram_addr);
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+ DPRINTF("No char dev for uart\n");
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}
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}
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