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@@ -392,6 +392,660 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
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check_tlb_flush(env, false);
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}
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+static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
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+{
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+ CPUState *cs = CPU(cpu);
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+ CPUPPCState *env = &cpu->env;
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+ target_ulong msr, new_msr, vector;
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+ int srr0, srr1;
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+
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+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
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+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
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+ }
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+
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+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
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+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
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+ excp, env->error_code);
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+
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+ /* new srr1 value excluding must-be-zero bits */
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+ msr = env->msr & ~0x783f0000ULL;
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+
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+ /*
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+ * new interrupt handler msr preserves existing ME unless
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+ * explicitly overriden.
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+ */
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+ new_msr = env->msr & (((target_ulong)1 << MSR_ME));
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+
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+ /* target registers */
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+ srr0 = SPR_SRR0;
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+ srr1 = SPR_SRR1;
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+
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+ /*
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+ * Hypervisor emulation assistance interrupt only exists on server
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+ * arch 2.05 server or later.
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+ */
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+ if (excp == POWERPC_EXCP_HV_EMU) {
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+ excp = POWERPC_EXCP_PROGRAM;
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+ }
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+
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+ vector = env->excp_vectors[excp];
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+ if (vector == (target_ulong)-1ULL) {
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+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
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+ excp);
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+ }
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+
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+ vector |= env->excp_prefix;
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+
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+ switch (excp) {
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+ case POWERPC_EXCP_CRITICAL: /* Critical input */
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+ srr0 = SPR_40x_SRR2;
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+ srr1 = SPR_40x_SRR3;
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+ break;
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+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
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+ if (msr_me == 0) {
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+ /*
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+ * Machine check exception is not enabled. Enter
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+ * checkstop state.
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+ */
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+ fprintf(stderr, "Machine check while not allowed. "
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+ "Entering checkstop state\n");
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+ if (qemu_log_separate()) {
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+ qemu_log("Machine check while not allowed. "
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+ "Entering checkstop state\n");
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+ }
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+ cs->halted = 1;
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+ cpu_interrupt_exittb(cs);
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+ }
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+
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+ /* machine check exceptions don't have ME set */
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+ new_msr &= ~((target_ulong)1 << MSR_ME);
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+
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+ srr0 = SPR_40x_SRR2;
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+ srr1 = SPR_40x_SRR3;
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+ break;
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+ case POWERPC_EXCP_DSI: /* Data storage exception */
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+ trace_ppc_excp_dsi(env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
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+ break;
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+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
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+ trace_ppc_excp_isi(msr, env->nip);
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+ break;
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+ case POWERPC_EXCP_EXTERNAL: /* External input */
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+ break;
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+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
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+ break;
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+ case POWERPC_EXCP_PROGRAM: /* Program exception */
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+ switch (env->error_code & ~0xF) {
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+ case POWERPC_EXCP_FP:
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+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
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+ trace_ppc_excp_fp_ignore();
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+ cs->exception_index = POWERPC_EXCP_NONE;
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+ env->error_code = 0;
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+ return;
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+ }
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+ env->spr[SPR_40x_ESR] = ESR_FP;
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+ break;
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+ case POWERPC_EXCP_INVAL:
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+ trace_ppc_excp_inval(env->nip);
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+ env->spr[SPR_40x_ESR] = ESR_PIL;
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+ break;
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+ case POWERPC_EXCP_PRIV:
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+ env->spr[SPR_40x_ESR] = ESR_PPR;
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+ break;
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+ case POWERPC_EXCP_TRAP:
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+ env->spr[SPR_40x_ESR] = ESR_PTR;
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+ break;
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+ default:
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+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
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+ env->error_code);
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+ break;
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+ }
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+ break;
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+ case POWERPC_EXCP_SYSCALL: /* System call exception */
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+ dump_syscall(env);
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+
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+ /*
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+ * We need to correct the NIP which in this case is supposed
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+ * to point to the next instruction
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+ */
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+ env->nip += 4;
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+ break;
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+ case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
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+ trace_ppc_excp_print("FIT");
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+ break;
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+ case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
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+ trace_ppc_excp_print("WDT");
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+ break;
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+ case POWERPC_EXCP_DTLB: /* Data TLB error */
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+ case POWERPC_EXCP_ITLB: /* Instruction TLB error */
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+ break;
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+ case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
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+ trace_ppc_excp_print("PIT");
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+ break;
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+ case POWERPC_EXCP_DEBUG: /* Debug interrupt */
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+ cpu_abort(cs, "%s exception not implemented\n",
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+ powerpc_excp_name(excp));
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+ break;
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+ default:
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+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
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+ break;
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+ }
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+
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+ /* Sanity check */
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+ if (!(env->msr_mask & MSR_HVB)) {
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+ if (new_msr & MSR_HVB) {
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+ cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
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+ "no HV support\n", excp);
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+ }
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+ if (srr0 == SPR_HSRR0) {
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+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
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+ "no HV support\n", excp);
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+ }
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+ }
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+
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+ /* Save PC */
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+ env->spr[srr0] = env->nip;
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+
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+ /* Save MSR */
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+ env->spr[srr1] = msr;
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+
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+ powerpc_set_excp_state(cpu, vector, new_msr);
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+}
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+
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+static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
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+{
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+ CPUState *cs = CPU(cpu);
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+ CPUPPCState *env = &cpu->env;
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+ target_ulong msr, new_msr, vector;
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+
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+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
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+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
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+ }
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+
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+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
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+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
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+ excp, env->error_code);
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+
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+ /* new srr1 value excluding must-be-zero bits */
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+ msr = env->msr & ~0x783f0000ULL;
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+
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+ /*
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+ * new interrupt handler msr preserves existing ME unless
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+ * explicitly overriden
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+ */
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+ new_msr = env->msr & ((target_ulong)1 << MSR_ME);
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+
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+ /*
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+ * Hypervisor emulation assistance interrupt only exists on server
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+ * arch 2.05 server or later.
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+ */
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+ if (excp == POWERPC_EXCP_HV_EMU) {
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+ excp = POWERPC_EXCP_PROGRAM;
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+ }
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+
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+ vector = env->excp_vectors[excp];
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+ if (vector == (target_ulong)-1ULL) {
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+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
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+ excp);
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+ }
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+
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+ vector |= env->excp_prefix;
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+
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+ switch (excp) {
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+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
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+ if (msr_me == 0) {
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+ /*
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+ * Machine check exception is not enabled. Enter
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+ * checkstop state.
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+ */
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+ fprintf(stderr, "Machine check while not allowed. "
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+ "Entering checkstop state\n");
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+ if (qemu_log_separate()) {
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+ qemu_log("Machine check while not allowed. "
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+ "Entering checkstop state\n");
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+ }
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+ cs->halted = 1;
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+ cpu_interrupt_exittb(cs);
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+ }
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+
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+ /* machine check exceptions don't have ME set */
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+ new_msr &= ~((target_ulong)1 << MSR_ME);
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+
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+ break;
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+ case POWERPC_EXCP_DSI: /* Data storage exception */
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+ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
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+ break;
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+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
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+ trace_ppc_excp_isi(msr, env->nip);
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+ msr |= env->error_code;
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+ break;
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+ case POWERPC_EXCP_EXTERNAL: /* External input */
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+ break;
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+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
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+ /* Get rS/rD and rA from faulting opcode */
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+ /*
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+ * Note: the opcode fields will not be set properly for a
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+ * direct store load/store, but nobody cares as nobody
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+ * actually uses direct store segments.
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+ */
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+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
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+ break;
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+ case POWERPC_EXCP_PROGRAM: /* Program exception */
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+ switch (env->error_code & ~0xF) {
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+ case POWERPC_EXCP_FP:
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+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
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+ trace_ppc_excp_fp_ignore();
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+ cs->exception_index = POWERPC_EXCP_NONE;
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+ env->error_code = 0;
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+ return;
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+ }
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+
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+ /*
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+ * FP exceptions always have NIP pointing to the faulting
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+ * instruction, so always use store_next and claim we are
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+ * precise in the MSR.
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+ */
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+ msr |= 0x00100000;
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+ break;
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+ case POWERPC_EXCP_INVAL:
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+ trace_ppc_excp_inval(env->nip);
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+ msr |= 0x00080000;
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+ break;
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+ case POWERPC_EXCP_PRIV:
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+ msr |= 0x00040000;
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+ break;
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+ case POWERPC_EXCP_TRAP:
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+ msr |= 0x00020000;
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+ break;
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+ default:
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+ /* Should never occur */
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+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
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+ env->error_code);
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+ break;
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+ }
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+ break;
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+ case POWERPC_EXCP_SYSCALL: /* System call exception */
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+ {
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+ int lev = env->error_code;
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+
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+ if ((lev == 1) && cpu->vhyp) {
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+ dump_hcall(env);
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+ } else {
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+ dump_syscall(env);
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+ }
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+
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+ /*
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+ * We need to correct the NIP which in this case is supposed
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+ * to point to the next instruction
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+ */
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+ env->nip += 4;
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+
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+ /*
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+ * The Virtual Open Firmware (VOF) relies on the 'sc 1'
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+ * instruction to communicate with QEMU. The pegasos2 machine
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+ * uses VOF and the 74xx CPUs, so although the 74xx don't have
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+ * HV mode, we need to keep hypercall support.
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+ */
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+ if ((lev == 1) && cpu->vhyp) {
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+ PPCVirtualHypervisorClass *vhc =
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+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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+ vhc->hypercall(cpu->vhyp, cpu);
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+ return;
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+ }
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+
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+ break;
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+ }
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+ case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
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+ case POWERPC_EXCP_DECR: /* Decrementer exception */
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+ break;
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+ case POWERPC_EXCP_RESET: /* System reset exception */
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+ if (msr_pow) {
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+ cpu_abort(cs, "Trying to deliver power-saving system reset "
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+ "exception %d with no HV support\n", excp);
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+ }
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+ break;
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+ case POWERPC_EXCP_TRACE: /* Trace exception */
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+ break;
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+ case POWERPC_EXCP_VPU: /* Vector unavailable exception */
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+ break;
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+ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
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+ case POWERPC_EXCP_SMI: /* System management interrupt */
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+ case POWERPC_EXCP_THERM: /* Thermal interrupt */
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+ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
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+ case POWERPC_EXCP_VPUA: /* Vector assist exception */
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+ cpu_abort(cs, "%s exception not implemented\n",
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+ powerpc_excp_name(excp));
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+ break;
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+ default:
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+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
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+ break;
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+ }
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+
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+ /* Sanity check */
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+ if (!(env->msr_mask & MSR_HVB)) {
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+ if (new_msr & MSR_HVB) {
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+ cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
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+ "no HV support\n", excp);
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+ }
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+ }
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+
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+ /*
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+ * Sort out endianness of interrupt, this differs depending on the
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+ * CPU, the HV mode, etc...
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+ */
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+ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
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+ new_msr |= (target_ulong)1 << MSR_LE;
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+ }
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+
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+ /* Save PC */
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+ env->spr[SPR_SRR0] = env->nip;
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+
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+ /* Save MSR */
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+ env->spr[SPR_SRR1] = msr;
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+
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+ powerpc_set_excp_state(cpu, vector, new_msr);
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+}
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+
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+#ifdef TARGET_PPC64
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+static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
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+{
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+ CPUState *cs = CPU(cpu);
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+ CPUPPCState *env = &cpu->env;
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+ int excp_model = env->excp_model;
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+ target_ulong msr, new_msr, vector;
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+ int srr0, srr1, lev = -1;
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+
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+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
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+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
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+ }
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+
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+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
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+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
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+ excp, env->error_code);
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+
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+ /* new srr1 value excluding must-be-zero bits */
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+ msr = env->msr & ~0x783f0000ULL;
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+
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+ /*
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+ * new interrupt handler msr preserves existing HV and ME unless
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+ * explicitly overriden
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+ */
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+ new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
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+
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+ /* target registers */
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+ srr0 = SPR_SRR0;
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+ srr1 = SPR_SRR1;
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+
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+ /*
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+ * check for special resume at 0x100 from doze/nap/sleep/winkle on
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+ * P7/P8/P9
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+ */
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+ if (env->resume_as_sreset) {
|
|
|
+ excp = powerpc_reset_wakeup(cs, env, excp, &msr);
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * We don't want to generate a Hypervisor Emulation Assistance
|
|
|
+ * Interrupt if we don't have HVB in msr_mask (PAPR mode).
|
|
|
+ */
|
|
|
+ if (excp == POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB)) {
|
|
|
+ excp = POWERPC_EXCP_PROGRAM;
|
|
|
+ }
|
|
|
+
|
|
|
+ vector = env->excp_vectors[excp];
|
|
|
+ if (vector == (target_ulong)-1ULL) {
|
|
|
+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
|
|
|
+ excp);
|
|
|
+ }
|
|
|
+
|
|
|
+ vector |= env->excp_prefix;
|
|
|
+
|
|
|
+ switch (excp) {
|
|
|
+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
|
|
|
+ if (msr_me == 0) {
|
|
|
+ /*
|
|
|
+ * Machine check exception is not enabled. Enter
|
|
|
+ * checkstop state.
|
|
|
+ */
|
|
|
+ fprintf(stderr, "Machine check while not allowed. "
|
|
|
+ "Entering checkstop state\n");
|
|
|
+ if (qemu_log_separate()) {
|
|
|
+ qemu_log("Machine check while not allowed. "
|
|
|
+ "Entering checkstop state\n");
|
|
|
+ }
|
|
|
+ cs->halted = 1;
|
|
|
+ cpu_interrupt_exittb(cs);
|
|
|
+ }
|
|
|
+ if (env->msr_mask & MSR_HVB) {
|
|
|
+ /*
|
|
|
+ * ISA specifies HV, but can be delivered to guest with HV
|
|
|
+ * clear (e.g., see FWNMI in PAPR).
|
|
|
+ */
|
|
|
+ new_msr |= (target_ulong)MSR_HVB;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* machine check exceptions don't have ME set */
|
|
|
+ new_msr &= ~((target_ulong)1 << MSR_ME);
|
|
|
+
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_DSI: /* Data storage exception */
|
|
|
+ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
|
|
|
+ trace_ppc_excp_isi(msr, env->nip);
|
|
|
+ msr |= env->error_code;
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_EXTERNAL: /* External input */
|
|
|
+ {
|
|
|
+ bool lpes0;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * LPES0 is only taken into consideration if we support HV
|
|
|
+ * mode for this CPU.
|
|
|
+ */
|
|
|
+ if (!env->has_hv_mode) {
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
|
|
|
+
|
|
|
+ if (!lpes0) {
|
|
|
+ new_msr |= (target_ulong)MSR_HVB;
|
|
|
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
|
|
+ srr0 = SPR_HSRR0;
|
|
|
+ srr1 = SPR_HSRR1;
|
|
|
+ }
|
|
|
+
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
|
|
|
+ /* Get rS/rD and rA from faulting opcode */
|
|
|
+ /*
|
|
|
+ * Note: the opcode fields will not be set properly for a
|
|
|
+ * direct store load/store, but nobody cares as nobody
|
|
|
+ * actually uses direct store segments.
|
|
|
+ */
|
|
|
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_PROGRAM: /* Program exception */
|
|
|
+ switch (env->error_code & ~0xF) {
|
|
|
+ case POWERPC_EXCP_FP:
|
|
|
+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
|
|
|
+ trace_ppc_excp_fp_ignore();
|
|
|
+ cs->exception_index = POWERPC_EXCP_NONE;
|
|
|
+ env->error_code = 0;
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * FP exceptions always have NIP pointing to the faulting
|
|
|
+ * instruction, so always use store_next and claim we are
|
|
|
+ * precise in the MSR.
|
|
|
+ */
|
|
|
+ msr |= 0x00100000;
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_INVAL:
|
|
|
+ trace_ppc_excp_inval(env->nip);
|
|
|
+ msr |= 0x00080000;
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_PRIV:
|
|
|
+ msr |= 0x00040000;
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_TRAP:
|
|
|
+ msr |= 0x00020000;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ /* Should never occur */
|
|
|
+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
|
|
|
+ env->error_code);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_SYSCALL: /* System call exception */
|
|
|
+ lev = env->error_code;
|
|
|
+
|
|
|
+ if ((lev == 1) && cpu->vhyp) {
|
|
|
+ dump_hcall(env);
|
|
|
+ } else {
|
|
|
+ dump_syscall(env);
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * We need to correct the NIP which in this case is supposed
|
|
|
+ * to point to the next instruction
|
|
|
+ */
|
|
|
+ env->nip += 4;
|
|
|
+
|
|
|
+ /* "PAPR mode" built-in hypercall emulation */
|
|
|
+ if ((lev == 1) && cpu->vhyp) {
|
|
|
+ PPCVirtualHypervisorClass *vhc =
|
|
|
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
|
|
+ vhc->hypercall(cpu->vhyp, cpu);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ if (lev == 1) {
|
|
|
+ new_msr |= (target_ulong)MSR_HVB;
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
|
|
|
+ lev = env->error_code;
|
|
|
+ dump_syscall(env);
|
|
|
+ env->nip += 4;
|
|
|
+ new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
|
|
|
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
|
|
+
|
|
|
+ vector += lev * 0x20;
|
|
|
+
|
|
|
+ env->lr = env->nip;
|
|
|
+ env->ctr = msr;
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
|
|
|
+ case POWERPC_EXCP_DECR: /* Decrementer exception */
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_RESET: /* System reset exception */
|
|
|
+ /* A power-saving exception sets ME, otherwise it is unchanged */
|
|
|
+ if (msr_pow) {
|
|
|
+ /* indicate that we resumed from power save mode */
|
|
|
+ msr |= 0x10000;
|
|
|
+ new_msr |= ((target_ulong)1 << MSR_ME);
|
|
|
+ }
|
|
|
+ if (env->msr_mask & MSR_HVB) {
|
|
|
+ /*
|
|
|
+ * ISA specifies HV, but can be delivered to guest with HV
|
|
|
+ * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
|
|
|
+ */
|
|
|
+ new_msr |= (target_ulong)MSR_HVB;
|
|
|
+ } else {
|
|
|
+ if (msr_pow) {
|
|
|
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
|
|
|
+ "exception %d with no HV support\n", excp);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_DSEG: /* Data segment exception */
|
|
|
+ case POWERPC_EXCP_ISEG: /* Instruction segment exception */
|
|
|
+ case POWERPC_EXCP_TRACE: /* Trace exception */
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
|
|
|
+ msr |= env->error_code;
|
|
|
+ /* fall through */
|
|
|
+ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
|
|
|
+ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
|
|
|
+ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
|
|
|
+ case POWERPC_EXCP_HV_EMU:
|
|
|
+ case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
|
|
|
+ srr0 = SPR_HSRR0;
|
|
|
+ srr1 = SPR_HSRR1;
|
|
|
+ new_msr |= (target_ulong)MSR_HVB;
|
|
|
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_VPU: /* Vector unavailable exception */
|
|
|
+ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
|
|
|
+ case POWERPC_EXCP_FU: /* Facility unavailable exception */
|
|
|
+ env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
|
|
|
+ env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
|
|
|
+ srr0 = SPR_HSRR0;
|
|
|
+ srr1 = SPR_HSRR1;
|
|
|
+ new_msr |= (target_ulong)MSR_HVB;
|
|
|
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_THERM: /* Thermal interrupt */
|
|
|
+ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
|
|
|
+ case POWERPC_EXCP_VPUA: /* Vector assist exception */
|
|
|
+ case POWERPC_EXCP_MAINT: /* Maintenance exception */
|
|
|
+ case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */
|
|
|
+ case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */
|
|
|
+ cpu_abort(cs, "%s exception not implemented\n",
|
|
|
+ powerpc_excp_name(excp));
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Sanity check */
|
|
|
+ if (!(env->msr_mask & MSR_HVB)) {
|
|
|
+ if (new_msr & MSR_HVB) {
|
|
|
+ cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
|
|
|
+ "no HV support\n", excp);
|
|
|
+ }
|
|
|
+ if (srr0 == SPR_HSRR0) {
|
|
|
+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
|
|
|
+ "no HV support\n", excp);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Sort out endianness of interrupt, this differs depending on the
|
|
|
+ * CPU, the HV mode, etc...
|
|
|
+ */
|
|
|
+ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
|
|
|
+ new_msr |= (target_ulong)1 << MSR_LE;
|
|
|
+ }
|
|
|
+
|
|
|
+ new_msr |= (target_ulong)1 << MSR_SF;
|
|
|
+
|
|
|
+ if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
|
|
|
+ /* Save PC */
|
|
|
+ env->spr[srr0] = env->nip;
|
|
|
+
|
|
|
+ /* Save MSR */
|
|
|
+ env->spr[srr1] = msr;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* This can update new_msr and vector if AIL applies */
|
|
|
+ ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
|
|
|
+
|
|
|
+ powerpc_set_excp_state(cpu, vector, new_msr);
|
|
|
+}
|
|
|
+#else
|
|
|
+static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
|
|
|
+{
|
|
|
+ g_assert_not_reached();
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
/*
|
|
|
* Note that this function should be greatly optimized when called
|
|
|
* with a constant excp, from ppc_hw_interrupt
|
|
|
@@ -768,7 +1422,6 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
|
|
|
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
|
|
|
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
|
|
|
switch (excp_model) {
|
|
|
- case POWERPC_EXCP_602:
|
|
|
case POWERPC_EXCP_603:
|
|
|
case POWERPC_EXCP_G2:
|
|
|
/* Swap temporary saved registers with GPRs */
|
|
|
@@ -872,6 +1525,19 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
switch (env->excp_model) {
|
|
|
+ case POWERPC_EXCP_40x:
|
|
|
+ powerpc_excp_40x(cpu, excp);
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_74xx:
|
|
|
+ powerpc_excp_74xx(cpu, excp);
|
|
|
+ break;
|
|
|
+ case POWERPC_EXCP_970:
|
|
|
+ case POWERPC_EXCP_POWER7:
|
|
|
+ case POWERPC_EXCP_POWER8:
|
|
|
+ case POWERPC_EXCP_POWER9:
|
|
|
+ case POWERPC_EXCP_POWER10:
|
|
|
+ powerpc_excp_books(cpu, excp);
|
|
|
+ break;
|
|
|
default:
|
|
|
powerpc_excp_legacy(cpu, excp);
|
|
|
}
|
|
|
@@ -1155,7 +1821,6 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
|
|
|
(env->spr[SPR_PSSCR] & PSSCR_EC);
|
|
|
}
|
|
|
#endif /* defined(TARGET_PPC64) */
|
|
|
-#endif /* CONFIG_TCG */
|
|
|
|
|
|
static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
|
|
|
{
|
|
|
@@ -1164,6 +1829,10 @@ static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
|
|
|
/* MSR:POW cannot be set by any form of rfi */
|
|
|
msr &= ~(1ULL << MSR_POW);
|
|
|
|
|
|
+ /* MSR:TGPR cannot be set by any form of rfi */
|
|
|
+ if (env->flags & POWERPC_FLAG_TGPR)
|
|
|
+ msr &= ~(1ULL << MSR_TGPR);
|
|
|
+
|
|
|
#if defined(TARGET_PPC64)
|
|
|
/* Switching to 32-bit ? Crop the nip */
|
|
|
if (!msr_is_64bit(env, msr)) {
|
|
|
@@ -1188,7 +1857,6 @@ static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
|
|
|
check_tlb_flush(env, false);
|
|
|
}
|
|
|
|
|
|
-#ifdef CONFIG_TCG
|
|
|
void helper_rfi(CPUPPCState *env)
|
|
|
{
|
|
|
do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
|
Peter Maydell