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@@ -2995,10 +2995,13 @@ MemTxResult address_space_write_cached_slow(MemoryRegionCache *cache,
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int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr);
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int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr);
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bool prepare_mmio_access(MemoryRegion *mr);
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bool prepare_mmio_access(MemoryRegion *mr);
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-static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
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+static inline bool memory_region_supports_direct_access(MemoryRegion *mr)
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{
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{
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/* ROM DEVICE regions only allow direct access if in ROMD mode. */
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/* ROM DEVICE regions only allow direct access if in ROMD mode. */
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- if (!memory_region_is_ram(mr) && !memory_region_is_romd(mr)) {
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+ if (memory_region_is_romd(mr)) {
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+ return true;
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+ }
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+ if (!memory_region_is_ram(mr)) {
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return false;
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return false;
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}
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}
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/*
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/*
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@@ -3006,7 +3009,12 @@ static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
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* be MMIO and access using mempy can be wrong (e.g., using instructions not
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* be MMIO and access using mempy can be wrong (e.g., using instructions not
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* intended for MMIO access). So we treat this as IO.
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* intended for MMIO access). So we treat this as IO.
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*/
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*/
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- if (memory_region_is_ram_device(mr)) {
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+ return !memory_region_is_ram_device(mr);
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+}
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+
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+static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
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+{
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+ if (!memory_region_supports_direct_access(mr)) {
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return false;
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return false;
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}
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}
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if (is_write) {
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if (is_write) {
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